From nobody Sat Apr 27 17:11:01 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1486976315025480.27803549986095; Mon, 13 Feb 2017 00:58:35 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D758982118; Mon, 13 Feb 2017 00:58:31 -0800 (PST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2BFC882115 for ; Mon, 13 Feb 2017 00:58:30 -0800 (PST) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2017 00:58:29 -0800 Received: from zwei4-mobl.ccr.corp.intel.com ([10.239.198.23]) by orsmga004.jf.intel.com with ESMTP; 13 Feb 2017 00:58:29 -0800 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,155,1484035200"; d="scan'208";a="58027974" From: zwei4 To: edk2-devel@lists.01.org Date: Mon, 13 Feb 2017 16:58:21 +0800 Message-Id: <20170213085821.32144-1-david.wei@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3] SPI Flash Lock. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Wei MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cleanup code about locking SPI Flash; Change the default value of BIOS Lock= setup option to FALSE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei --- .../PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c | 4 +- .../Library/PeiPolicyUpdateLib/PeiScPolicyUpdate.c | 39 +----------- .../PlatformSetupDxe/SouthClusterConfig.vfi | 4 +- .../BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c | 71 ------------------= ---- 4 files changed, 5 insertions(+), 113 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib= /PeiFspScPolicyInitLib.c b/Platform/BroxtonPlatformPkg/Common/Library/PeiFs= pPolicyInitLib/PeiFspScPolicyInitLib.c index 47ec70600..640900688 100644 --- a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFsp= ScPolicyInitLib.c +++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFsp= ScPolicyInitLib.c @@ -1,7 +1,7 @@ /** @file Implementation of Fsp SC Policy Initialization. =20 - Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -601,7 +601,7 @@ PeiFspScPolicyInit ( // Flash Protection Range Register initialization // for (Index =3D 0; Index < SC_FLASH_PROTECTED_RANGES; Index++) { - FspsUpd->FspsConfig.WriteProtectionEnable[Index] =3D TRUE; + FspsUpd->FspsConfig.WriteProtectionEnable[Index] =3D SystemConf= iguration->ScBiosLock =3D=3D TRUE ? TRUE : FALSE; FspsUpd->FspsConfig.ReadProtectionEnable[Index] =3D FALSE; } =20 diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/= PeiScPolicyUpdate.c b/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyU= pdateLib/PeiScPolicyUpdate.c index 6d9fc52de..c98a8df65 100644 --- a/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPo= licyUpdate.c +++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiPolicyUpdateLib/PeiScPo= licyUpdate.c @@ -1,7 +1,7 @@ /** @file This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. =20 - Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2004 - 2017, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -277,13 +277,11 @@ UpdatePeiScPolicy ( UINT16 BoardId; UINTN VariableSize; SYSTEM_CONFIGURATION SystemConfiguration; - UINT8 Index; UINT8 PortIndex; UINT32 SpiHsfsReg; UINT32 SpiFdodReg; UINT8 DevIndex; UINT8 HdaIndex; - BOOLEAN FlashProtectionEnabled; SC_GENERAL_CONFIG *GeneralConfig; SC_SATA_CONFIG *SataConfig; SC_PCIE_CONFIG *PcieConfig; @@ -729,41 +727,6 @@ UpdatePeiScPolicy ( } PmConfig->PowerButterDebounceMode =3D SystemConfiguration.PowerButterDeb= ounceMode; =20 - if ((GetBxtSeries() =3D=3D BxtP) && (IsSpiBoot ())) { - // - // Configure Flash Protection Range Registers - // - FlashProtectionEnabled =3D SystemConfiguration.FprrEnable =3D=3D TRUE = ? TRUE : FALSE; - - // - // Enabling Flash Protection Range Registers - // Enable FPRR policy and set up ranges on non-Capsule Update flow wit= h Flash Wear-Out Protection enabled - // PrintFlashProtectionConfig() dumps FPRR information during ScPrintP= olicyPpi() - // FPRR bit is enabled by default as per Platform policy, except that= when system is in recovery mode or FDO is enabled. In this case this will = be disabled as part of Firmware Update / Recovery update - // - if (FlashProtectionEnabled && (FdoEnabledGuidHob =3D=3D NULL)) { - // - // Flash Protection Range Register initialization - // - for (Index =3D 0; Index < SC_FLASH_PROTECTED_RANGES; Index++) { - FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnable = =3D TRUE; - FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable = =3D FALSE; - } - - DEBUG ((EFI_D_INFO, "IbbOffset =3D %x , IbbSize =3D %x\n", FixedPcdG= et32 (PcdFlashIbbRegionMappedBase), FixedPcdGet32 (PcdFlashIbbRegionSize))); - DEBUG ((EFI_D_INFO, "ObbOffset =3D %x , ObbSize =3D %x\n", FixedPcdG= et32 (PcdFlashObbRegionMappedBase), FixedPcdGet32 (PcdFlashObbRegionSize))); - - // - // Assign FPRR ranges - // - FlashProtectionConfig->ProtectRange[0].ProtectedRangeBase =3D (UI= NT16) ((FixedPcdGet32 (PcdFlashIbbRegionMappedBase) - FixedPcdGet32 (PcdFla= shAreaBaseAddress)) >> 12); - FlashProtectionConfig->ProtectRange[0].ProtectedRangeLimit =3D (UI= NT16) ((FixedPcdGet32 (PcdFlashIbbRegionMappedBase) - FixedPcdGet32 (PcdFla= shAreaBaseAddress) + FixedPcdGet32 (PcdFlashIbbRegionSize) - 1) >> 12); - FlashProtectionConfig->ProtectRange[1].ProtectedRangeBase =3D (UI= NT16) ((FixedPcdGet32 (PcdFlashObbRegionMappedBase) - FixedPcdGet32 (PcdFla= shAreaBaseAddress)) >> 12); - FlashProtectionConfig->ProtectRange[1].ProtectedRangeLimit =3D (UI= NT16) ((FixedPcdGet32 (PcdFlashObbRegionMappedBase) - FixedPcdGet32 (PcdFla= shAreaBaseAddress) + FixedPcdGet32 (PcdFlashObbRegionSize) - 1) >> 12); - } else { - DEBUG ((DEBUG_INFO, " BIOS FPRR is not done -FDO ASSERT Status ")); - } - } =20 DciConfig->DciEn =3D SystemConfiguration.DciEn; DciConfig->DciAutoDetect =3D SystemConfiguration.DciAutoDetect; diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSe= tupDxe/SouthClusterConfig.vfi b/Platform/BroxtonPlatformPkg/Common/Platform= Settings/PlatformSetupDxe/SouthClusterConfig.vfi index 411006b38..f2a09c236 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/= SouthClusterConfig.vfi +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/= SouthClusterConfig.vfi @@ -145,8 +145,8 @@ form formid =3D MISC_OPTIONS_FORM_ID, oneof varid =3D Setup.ScBiosLock, prompt =3D STRING_TOKEN(STR_PCH_BLE_PROMPT), help =3D STRING_TOKEN(STR_PCH_BLE_HELP), - option text =3D STRING_TOKEN(STR_DISABLED), value =3D 0, flags =3D RES= ET_REQUIRED; - option text =3D STRING_TOKEN(STR_ENABLED), value =3D 1, flags =3D DEFA= ULT | MANUFACTURING | RESET_REQUIRED; + option text =3D STRING_TOKEN(STR_DISABLED), value =3D 0, flags =3D DEF= AULT | MANUFACTURING | RESET_REQUIRED; + option text =3D STRING_TOKEN(STR_ENABLED), value =3D 1, flags =3D RESE= T_REQUIRED; endoneof; oneof varid =3D Setup.RtcLock, prompt =3D STRING_TOKEN(STR_PCH_RTC_LOCK_PROMPT), diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit= .c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c index c4a9d5088..9620dacfb 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c @@ -624,22 +624,17 @@ ScOnEndOfDxe ( ) { EFI_STATUS Status; - UINTN Index; UINT32 FuncDisableReg; - UINT32 Data32; UINT32 Data32And; UINT32 Data32Or; UINT16 AcpiBaseAddr; UINT32 PmcBase; UINT8 NumOfDevltrOverride; - UINT32 DlockValue; UINTN PciLpcRegBase; UINTN PciSpiRegBase; - UINTN SpiBar0; BXT_SERIES BxtSeries; UINT8 Data8; SC_LOCK_DOWN_CONFIG *LockDownConfig; - SC_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; UINT16 Data16And; UINT16 Data16Or; SI_POLICY_HOB *SiPolicyHob; @@ -680,72 +675,6 @@ ScOnEndOfDxe ( (VOID *) (UINTN) (PmcBase + R_PMC_PMIR) ); =20 - if (BxtSeries =3D=3D BxtP){ - SpiBar0 =3D MmioRead32 (PciSpiRegBase + R_SPI_BASE) & ~(B_SPI_BAR0_MAS= K); - Status =3D GetConfigBlock ((VOID *) mScPolicy, &gFlashProtectionConfig= Guid, (VOID *) &FlashProtectionConfig); - ASSERT_EFI_ERROR (Status); - - // - // Program the Flash Protection Range Register based on policy - // - DlockValue =3D MmioRead32 (SpiBar0 + R_SPI_DLOCK); - - FlashProtectionConfig->ProtectRange[0].ProtectedRangeBase =3D (UINT= 16) ((FixedPcdGet32 (PcdFlashIbbRegionMappedBase) - FixedPcdGet32 (PcdFlash= AreaBaseAddress)) >> 12); - FlashProtectionConfig->ProtectRange[0].ProtectedRangeLimit =3D (UINT= 16) ((FixedPcdGet32 (PcdFlashIbbRegionMappedBase) - FixedPcdGet32 (PcdFlash= AreaBaseAddress) + FixedPcdGet32 (PcdFlashIbbRegionSize) - 1) >> 12); - FlashProtectionConfig->ProtectRange[1].ProtectedRangeBase =3D (UINT= 16) ((FixedPcdGet32 (PcdFlashObbRegionMappedBase) - FixedPcdGet32 (PcdFlash= AreaBaseAddress)) >> 12); - FlashProtectionConfig->ProtectRange[1].ProtectedRangeLimit =3D (UINT= 16) ((FixedPcdGet32 (PcdFlashObbRegionMappedBase) - FixedPcdGet32 (PcdFlash= AreaBaseAddress) + FixedPcdGet32 (PcdFlashObbRegionSize) - 1) >> 12); - - for (Index =3D 0; Index < SC_FLASH_PROTECTED_RANGES; ++Index) { - if ((FlashProtectionConfig->ProtectRange[Index].WriteProtectionEnabl= e || - FlashProtectionConfig->ProtectRange[Index].ReadProtectionEnable= ) !=3D TRUE) { - continue; - } - - // - // Proceed to program the register after ensure it is enabled - // - Data32 =3D 0; - Data32 |=3D (FlashProtectionConfig->ProtectRange[Index].WriteProtect= ionEnable =3D=3D TRUE) ? B_SPI_PRX_WPE : 0; - Data32 |=3D (FlashProtectionConfig->ProtectRange[Index].ReadProtecti= onEnable =3D=3D TRUE) ? B_SPI_PRX_RPE : 0; - Data32 |=3D ((UINT32) FlashProtectionConfig->ProtectRange[Index].Pro= tectedRangeLimit << N_SPI_PRX_PRL) & B_SPI_PRX_PRL_MASK; - Data32 |=3D ((UINT32) FlashProtectionConfig->ProtectRange[Index].Pro= tectedRangeBase << N_SPI_PRX_PRB) & B_SPI_PRX_PRB_MASK; - DEBUG ((DEBUG_INFO, "Protected range %d: 0x%08x \n", Index, Data32)); - - DlockValue |=3D (UINT32) (B_SPI_DLOCK_PR0LOCKDN << Index); - MmioWrite32 ((UINTN) (SpiBar0 + (R_SPI_PR0 + (Index * S_SPI_PRX))), = Data32); - S3BootScriptSaveMemWrite ( - S3BootScriptWidthUint32, - (UINTN) (SpiBar0 + (R_SPI_PR0 + (Index * S_SPI_PRX))), - 1, - (VOID *) (UINTN) (SpiBar0 + (R_SPI_PR0 + (Index * S_SPI_PRX))) - ); - } - - // - // Program DLOCK register - // - MmioWrite32 ((UINTN) (SpiBar0 + R_SPI_DLOCK), DlockValue); - S3BootScriptSaveMemWrite ( - S3BootScriptWidthUint32, - (UINTN) (SpiBar0 + R_SPI_DLOCK), - 1, - (VOID *) (UINTN) (SpiBar0 + R_SPI_DLOCK) - ); - - // - // In SPI controller the BIOS should set the Flash Configuration Lock-= Down bit - // (SPI_BAR0 + 04[15]) at end of post. When set to 1, those Flash Pro= gram Registers - // that are locked down by this FLOCKDN bit cannot be written. - // - MmioOr32 ((UINTN) (SpiBar0 + R_SPI_HSFS), (UINT32) (B_SPI_HSFS_FLOCKDN= )); - S3BootScriptSaveMemWrite ( - EfiBootScriptWidthUint32, - (UINTN) (SpiBar0 + R_SPI_HSFS), - 1, - (VOID *) (UINTN) (SpiBar0 + R_SPI_HSFS) - ); - } - Status =3D GetConfigBlock ((VOID *) mScPolicy, &gLockDownConfigGuid, (VO= ID *) &LockDownConfig); ASSERT_EFI_ERROR (Status); if (LockDownConfig->GlobalSmi =3D=3D TRUE) { --=20 2.11.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel