From nobody Thu May 2 15:25:28 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1492140483797946.3856538409526; Thu, 13 Apr 2017 20:28:03 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A0B7A21A04830; Thu, 13 Apr 2017 20:28:01 -0700 (PDT) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9826921A04811 for ; Thu, 13 Apr 2017 20:28:00 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 13 Apr 2017 20:27:59 -0700 Received: from shwdeopenpsi011.ccr.corp.intel.com (HELO SHWDEOPENPSI011.local) ([10.239.9.7]) by FMSMGA003.fm.intel.com with SMTP; 13 Apr 2017 20:27:58 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,197,1488873600"; d="scan'208";a="845902578" Date: Fri, 14 Apr 2017 11:27:59 +0800 From: lushifex To: edk2-devel@lists.01.org Message-ID: <1bc7ae64-f854-4fcd-adec-73e1d6f2707a@SHWDEOPENPSI011.local> X-Mailer: TortoiseGit MIME-Version: 1.0 Subject: [edk2] [Patch][edk2-platforms/devel-MinnowBoard3] Configure GPIO. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: , david.wei@intel.com Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" GPIO configuration for Low Speed Expander and System Feature Expander pins. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex Reviewed-by: zwei4 --- .../MinnowBoard3/BoardInitPostMem/BoardGpios.h | 24 +++++++++++-------= ---- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMe= m/BoardGpios.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPo= stMem/BoardGpios.h index 0928e16..692fbf7 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Gpios.h +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPostMem/Board= Gpios.h @@ -96,8 +96,8 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_N[] =3D BXT_GPIO_PAD_CONF(L"GPIO_31", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x00F8, NORTH),//Feature: SUSCLK1 BXT_GPIO_PAD_CONF(L"GPIO_32", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0100, NORTH),// Net in= Sch: SUSCLK2 BXT_GPIO_PAD_CONF(L"GPIO_33", M5 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0108, NORTH),//Feature: SUSCLK3 - BXT_GPIO_PAD_CONF(L"GPIO_34 PWM0", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0110, NORTH),//Feature: PWM - BXT_GPIO_PAD_CONF(L"GPIO_35 PWM1", M0 , GPO , GPIO_D,= HI , NA , Wake_Disabled, P_5K_H , NA , NA, NA , = NA, GPIO_PADBAR+0x0118, NORTH),//Feature:Power Enable Net in= Sch: TCH_PNL_PG + BXT_GPIO_PAD_CONF(L"GPIO_34 PWM0", M0 , GPIO , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0110, NORTH), + BXT_GPIO_PAD_CONF(L"GPIO_35 PWM1", M0 , GPIO , NA ,= NA , NA , Wake_Disabled, P_5K_H , NA , NA, NA , = NA, GPIO_PADBAR+0x0118, NORTH), BXT_GPIO_PAD_CONF(L"GPIO_36 PWM2", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA, NA , = NA, GPIO_PADBAR+0x0120, NORTH),//Feature: PWM BXT_GPIO_PAD_CONF(L"GPIO_38 LPSS_UART0_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, HizRx1I,D= isPuPd, GPIO_PADBAR+0x0130, NORTH), BXT_GPIO_PAD_CONF(L"GPIO_39 LPSS_UART0_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,Last_Value,D= isPuPd, GPIO_PADBAR+0x0138, NORTH), @@ -214,15 +214,15 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_NW [] =3D BXT_GPIO_PAD_CONF(L"GPIO_109 GP_SSP_0_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x0200, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_110 GP_SSP_0_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA,HizRx0I , = EnPd, GPIO_PADBAR+0x0208, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_111 GP_SSP_1_CLK", M0 , GPI ,GPIO_D, = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,NA , = NA, GPIO_PADBAR+0x0210, NORTHWEST),//Not used on RVP - BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0218, NORTHWEST),//Feature: LPSS UART Hdr - BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M0 , GPI ,GPIO_D, = NA , NA ,Wake_Disabled, P_20K_L, NA , NA ,Last_Value, = SAME, GPIO_PADBAR+0x0220, NORTHWEST),//Not used on RVP + BXT_GPIO_PAD_CONF(L"GPIO_112 GP_SSP_1_FS0", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0218, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_113 GP_SSP_1_FS1", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0220, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_116 GP_SSP_1_RXD", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0228, NORTHWEST),//Feature: LPSS UART Hdr BXT_GPIO_PAD_CONF(L"GPIO_117 GP_SSP_1_TXD", M2 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0230, NORTHWEST),//Feature: LPSS UART Hdr - BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0238, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0240, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0248, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0250, NORTHWEST), - BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0258, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_118 GP_SSP_2_CLK", M0 , GPIO , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0238, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_119 GP_SSP_2_FS0", M0 , GPIO , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0240, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_120 GP_SSP_2_FS1", M0 , GPIO , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0248, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_121 GP_SSP_2_FS2", M0 , GPIO , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0250, NORTHWEST), + BXT_GPIO_PAD_CONF(L"GPIO_122 GP_SSP_2_RXD", M0 , GPIO , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0258, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_123 GP_SSP_2_TXD", M1 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0260, NORTHWEST), BXT_GPIO_PAD_CONF(L"GPIO_191 DBI_SDA", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0020, NORTHWEST),//Feature: DBI_SDA BXT_GPIO_PAD_CONF(L"GPIO_192 DBI_SCL", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA, GPIO_PADBAR+0x0028, NORTHWEST),//Feature: DBI_SCL @@ -251,9 +251,9 @@ BXT_GPIO_PAD_INIT mBXT_GpioInitData_W [] =3D BXT_GPIO_PAD_CONF(L"GPIO_133 LPSS_I2C4_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D1RxDRx1I, = EnPu, GPIO_PADBAR+0x0048, WEST), BXT_GPIO_PAD_CONF(L"GPIO_138 LPSS_I2C7_SDA", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D0RxDRx0I, = EnPu, GPIO_PADBAR+0x0070, WEST),// RFKILL_N BXT_GPIO_PAD_CONF(L"GPIO_139 LPSS_I2C7_SCL", M1 , NA , NA , = NA , NA , Wake_Disabled, P_1K_H , NA , NA, D0RxDRx0I, = EnPu, GPIO_PADBAR+0x0078, WEST),//HALL_STATE - BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0080, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0088, WEST), - BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0090, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_146 ISH_GPIO_0", M0 , GPIO , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0080, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_147 ISH_GPIO_1", M0 , GPIO , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0088, WEST), + BXT_GPIO_PAD_CONF(L"GPIO_148 ISH_GPIO_2", M0 , GPIO , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0090, WEST), BXT_GPIO_PAD_CONF(L"GPIO_149 ISH_GPIO_3", M3 , NA , NA , = NA , NA , Wake_Disabled, P_20K_L, NA , NA,IOS_Masked, = SAME, GPIO_PADBAR+0x0098, WEST), BXT_GPIO_PAD_CONF(L"GPIO_150 ISH_GPIO_4", M2 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00A0, WEST),//Feature: AVS_I2S5_BCLK BXT_GPIO_PAD_CONF(L"GPIO_151 ISH_GPIO_5", M0 , GPO ,GPIO_D, = HI , NA , Wake_Disabled, P_20K_L, NA , NA,NA , = NA , GPIO_PADBAR+0x00A8, WEST),//Feature: RF_KILL_WWAN Net in= Sch: NGFF_WWAN_RF_KILL_1P8_N --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel