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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id m29-v6sm6485484lfj.45.2018.07.13.01.12.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 01:12:24 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::242; helo=mail-lj1-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1WMFvMKgds8sS2w71W2m+LjNzNUfOiKqEulmDq+dk9w=; b=QLL+6FcM5z600K4el+cZHT0ooUw4hVnnNEUImFEKm+XkIx4w3/LrjVWUa9DggRjhHe 8jrShRKz6c7lxzLTcebjQ1Tdm0stKbU6jnIk/arZp5kFiB2iTAvUCZUjf4EB3ck5uzn6 sVg8xzsXzKo02bmGZ5ufyxZbxJpAvLY3l9DFObXhxoZzLjVGWCy+YJt9S2FpYja7nuTJ WnAOfQErI18vHboq/C1qPxVbg5lfOXPJKnUIRutMxUSiENFQ04iwIdf52y2FtOLmzMEe jHsj72CqUzCM5kxl8ltQKsvQ8h3Yf6/6LGBU8EbIT5YvVpGJ7RmFOmPgYBu5qOshAnYQ SNaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1WMFvMKgds8sS2w71W2m+LjNzNUfOiKqEulmDq+dk9w=; b=GP85i56e90JPBVSej1SsILPV+nGlkMbr7xtOj+fM6Byn3IJV7UanOLX+qVwsRC0Qfa kIy1odmdrKeolgqKBN2iRWv4dYs4aVtfWR2J7ppMR5j+6vTwjAiQSPpCDdH1855jXLE0 9kvmE/z0acoX88vNUBkGJjsrGRceFahc979H9AmElUk8/YQpBk5vbkDp61c2S5j15+pK wmiOtsaCgzmuHW7asISIJnhe/p6tcZmmmzRavaBm/s3YByyrNzMhNkZMa2vjO0DZHAs1 PIpw4mtLz73YKP+qz6KXWdZV4lPPaPTpQwCnq9mHMlaY04kvR0JsnZ5PHRQQiL+mq5dN 2KTg== X-Gm-Message-State: AOUpUlEZR7vv6bQH+gt7mqnRNGfGMWA1/z1yRtEpLhdgmxqy/c5mXg4b pH/szmmz2r8mD3cY+hIElWOFp1Pmw90= X-Google-Smtp-Source: AAOMgpfyxCIUDFzVBwvSRAgF6GpGTvkFHOEgc1nwcWRJrwTw8u764qk1f4P2ZpPrIUGeiJUuzhWrrw== X-Received: by 2002:a2e:9d0e:: with SMTP id t14-v6mr2526205lji.112.1531469545459; Fri, 13 Jul 2018 01:12:25 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 13 Jul 2018 10:12:08 +0200 Message-Id: <1531469533-31787-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531469533-31787-1-git-send-email-mw@semihalf.com> References: <1531469533-31787-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 1/6] Marvell/Armada70x0Db: Set correct CP110 count X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" As a preparation for adding the ICU (Interrupt Consolidation Unit) library implementation a correct CP110 count is required. Do it for Armada70x0Db and fix depending XHCI/AHCI PCD's accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 5ccee1b..2240a57 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -53,6 +53,9 @@ # ##########################################################################= ###### [PcdsFixedAtBuild.common] + #CP110 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|2 =20 @@ -129,8 +132,8 @@ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } =20 #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 11:32:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531469553909753.7089066395121; Fri, 13 Jul 2018 01:12:33 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8BA8920986AAD; Fri, 13 Jul 2018 01:12:30 -0700 (PDT) Received: from mail-lj1-x244.google.com (mail-lj1-x244.google.com [IPv6:2a00:1450:4864:20::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C4AE7209831FA for ; Fri, 13 Jul 2018 01:12:28 -0700 (PDT) Received: by mail-lj1-x244.google.com with SMTP id f8-v6so6221502ljk.1 for ; Fri, 13 Jul 2018 01:12:28 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m29-v6sm6485484lfj.45.2018.07.13.01.12.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 01:12:25 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::244; helo=mail-lj1-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=t4HsFEoxxzIsbRkrGaBXawZ/eDBomOIGKJxqqTcrfBY=; b=reGDqGIwYaJLuSFajn6SQDeDKGdnH3b33Z/k5suu7P6+zR8SNeYhn8uZBkgbYfmkEd r5q3Ui7j6yqJaB+lDLFYmDrzHQeg1XcQieEtO1NjS1Mz1vzAOWJMgHn6jOAqsdeh9lUk vv/+tSqDQalJsk9FOuzsIvJamK7D7YfDIZgzRt+ctTZDBjEyi1XPfR+hVg+GzVltU2cZ J2fdLjTlHd0EclJ6hzHrIwVn4kaJOxok8yFUptxEStBstWbO/0BNFtauiS2kduJX5Enf 5/NZ4og6pyF45gbwSS7HaFAOxu9ba11XTC5dgjfo1hrGAWOf/94dQS7k+tNecSd5guiO n/5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=t4HsFEoxxzIsbRkrGaBXawZ/eDBomOIGKJxqqTcrfBY=; b=Qg9rhUzyLvLCZOVw5gpYdYO6SgK3MbSxCOm4ScPmQomvBy1bwwjxm47tP07RU5VMpS BqivwF5TyeZCbl1ioVSEiWTjkRfEWkOo7QS022Q/zcNCxKWNHOQjH8PhsADvz4G58F2h FNF7s6Wlt3sQPhOsTiLZIlrCcif6oXRfSQ7CxARrr1QRfTQl6HTxV0Gf71kZgisKRjH5 0m4kiBX5yhVbPDCI7X+R2C2TBThHIiXywObFQofl/MhDll9o3ztPZ/3i++pN65Ats9k9 me/+rxEbbb+6DtObpoThqKoro7txgOXUN2Hzbrce6ctTXN0V/Oa2hFCnqyrOGcUI0Ugj zb5g== X-Gm-Message-State: AOUpUlFcwb2r+uvmOAjSWcUsATBYUO3dms+GMiekuKu9hmgitwCEICsX qbUQbLXjwyqYXgh6sWtM54PlL2Cli7c= X-Google-Smtp-Source: AAOMgpeivKPjKUnpFN6O4YeCo1xjAg+ocS0dbT1ateYaV9AZVOOpsrUHYd0WBKvRs83H9v0sghkieA== X-Received: by 2002:a2e:4951:: with SMTP id b17-v6mr2518732ljd.67.1531469546672; Fri, 13 Jul 2018 01:12:26 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 13 Jul 2018 10:12:09 +0200 Message-Id: <1531469533-31787-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531469533-31787-1-git-send-email-mw@semihalf.com> References: <1531469533-31787-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 2/6] Marvell/Library: Introduce ArmadaIcuLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" ICU (Interrupt Consolidation Unit) is a mechanism, that allows to send a message-based interrupts from the CP110 unit (South Bridge) to the Application Processor hardware block. After dispatching the interrupts in the GIC are generated. This patch adds a basic version of the library, that allows to configure a static mapping between CP110 interfaces and GIC. It is required for the cases, where the OS does not support the ICU controller on its own (e.g. ACPI boot). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Marvell.dec | 1 + Silicon/Marvell/Include/Library/ArmadaIcuLib.h | 45 ++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 Silicon/Marvell/Include/Library/ArmadaIcuLib.h diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 4def897..616624e 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -61,6 +61,7 @@ =20 [LibraryClasses] ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h + ArmadaIcuLib|Include/Library/ArmadaIcuLib.h ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h SampleAtResetLib|Include/Library/SampleAtResetLib.h =20 diff --git a/Silicon/Marvell/Include/Library/ArmadaIcuLib.h b/Silicon/Marve= ll/Include/Library/ArmadaIcuLib.h new file mode 100644 index 0000000..426734e --- /dev/null +++ b/Silicon/Marvell/Include/Library/ArmadaIcuLib.h @@ -0,0 +1,45 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#ifndef __ARMADA_ICU_LIB_H__ +#define __ARMADA_ICU_LIB_H__ + +typedef enum { + IcuIrqTypeLevel =3D 0, + IcuIrqTypeEdge =3D 1 +} ICU_IRQ_TYPE; + +typedef struct { + UINTN IcuId; + UINTN SpiId; + ICU_IRQ_TYPE IrqType; +} ICU_IRQ; + +typedef struct { + const ICU_IRQ *Map; + UINTN Size; +} ICU_CONFIG_ENTRY; + +typedef struct { + ICU_CONFIG_ENTRY NonSecure; + ICU_CONFIG_ENTRY Sei; + ICU_CONFIG_ENTRY Rei; +} ICU_CONFIG; + +EFI_STATUS +EFIAPI +ArmadaIcuInitialize ( + VOID + ); + +#endif /* __ARMADA_ICU_LIB_H__ */ --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 11:32:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531469557866904.5033749938204; Fri, 13 Jul 2018 01:12:37 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B2E7320986AB5; Fri, 13 Jul 2018 01:12:32 -0700 (PDT) Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0008320985980 for ; Fri, 13 Jul 2018 01:12:29 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id r13-v6so23904221ljg.10 for ; Fri, 13 Jul 2018 01:12:29 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m29-v6sm6485484lfj.45.2018.07.13.01.12.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 01:12:27 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::22a; helo=mail-lj1-x22a.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XLXN4jIlWOzkPlx1YKNYnTWA1nfCVctRngHTegcD0lk=; b=JT0nfzzlp6WpG2L6vgceHF/JOSaOcCqY7rSxKx9WQVBA4StxSc8+8/kfNNqxLz/qyj av8PlYLFLuGu5VLjh8UJKL5u39Ple4JoQUhTVSBuqX+r0Xgl3wU62fsfrseagBAEX9M5 CwRSKSFWvGAFj6XFdQnfbh9S4PhNFwmlFkXMNCFPgsd8jqLSBEqLYH4ssTQ1kUy7A6hy rZ3TC63Q7V0Y7sjKhQYHa8yG47naSSjUUEB4GSPcDMslf2eYG/Itsj/HADtmH1L/4e8a u3HVQkc0b6Grlbvp8iR8JbTb1DOjMOBdudiczuRKT/wLOeZdhgmDlvTWVFVtk9QQ0Xx5 DU9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XLXN4jIlWOzkPlx1YKNYnTWA1nfCVctRngHTegcD0lk=; b=lGivjG+6QTPUqC08ugvIwL0W1sKs9Av/EE46BHfb4x7uk9oVt6i9J6hqBY2v9ErR/E /I+C9Ne3kLq9p+LF06VmXP7vAmvbo7X2GI2LBwDdYwZEJTgiF/TNil4vs9jVzlM39Ppj F3w9ZCUpMKfdcMPWNRy1Y3hDCbuUd6iS8LxsAA2hyKTcYwLMIZC2MvRIIHaCxY3ZcwG9 0obwsCedI+ztJ8iM/7/CFDLdHKLRnC7AXhGAv7TzjoIPyFF1oXPsy9s8qTFuzGFFH/dY op1ay+mQrHWGDPG8WTaAwzduSBMaOlzwuBH9SPRoD2dh1DpPO1kwlAbTnmLqMNepHb4w t/gQ== X-Gm-Message-State: AOUpUlFLH/MEvrpC2heft+6FCeymjzncTURUwVJYtvcd82XQAIgqYYB+ pIIrGSysnokNN1jkf3auOPNouUYVyuc= X-Google-Smtp-Source: AAOMgpebfVmwG2di8Ttf2roxpacgpJeBRLWIMsWJMjPfZjhgYG0Eh17l6lsMbZvTf7tABEi5La20BA== X-Received: by 2002:a2e:144f:: with SMTP id 15-v6mr2502996lju.122.1531469547897; Fri, 13 Jul 2018 01:12:27 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 13 Jul 2018 10:12:10 +0200 Message-Id: <1531469533-31787-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531469533-31787-1-git-send-email-mw@semihalf.com> References: <1531469533-31787-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 3/6] Marvell/Library: Armada7k8kSoCDescLib: Enable getting CP base address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" For upcoming patches there is a need to get the CP110 base address, introduce according getter function for it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 9 +++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 11 +++++++++++ 2 files changed, 20 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index d2bcf2a..30e6378 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -37,6 +37,15 @@ ArmadaSoCDescComPhyGet ( ); =20 // +// South Bridge description +// +EFI_PHYSICAL_ADDRESS +EFIAPI +ArmadaSoCDescCpBaseGet ( + IN UINTN CpIndex + ); + +// // I2C // typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 6ce6bad..7184ab6 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -61,6 +61,17 @@ ArmadaSoCDescComPhyGet ( return EFI_SUCCESS; } =20 +EFI_PHYSICAL_ADDRESS +EFIAPI +ArmadaSoCDescCpBaseGet ( + IN UINTN CpIndex + ) +{ + ASSERT (CpIndex < FixedPcdGet8 (PcdMaxCpCount)); + + return MV_SOC_CP_BASE (CpIndex); +} + EFI_STATUS EFIAPI ArmadaSoCDescI2cGet ( --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 11:32:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531469560929124.6717718319187; Fri, 13 Jul 2018 01:12:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D98A221BADAB9; Fri, 13 Jul 2018 01:12:32 -0700 (PDT) Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2276A20986AB2 for ; Fri, 13 Jul 2018 01:12:31 -0700 (PDT) Received: by mail-lj1-x243.google.com with SMTP id 1-v6so23872995ljv.9 for ; Fri, 13 Jul 2018 01:12:30 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m29-v6sm6485484lfj.45.2018.07.13.01.12.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 01:12:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4864:20::243; helo=mail-lj1-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ru2MJzHCsl8VSXcxUO4Bc7R3QXzGeOdTatqL62mo55s=; b=Kk/uTr6+CTCXqCwK7cusIiI0uUqyKCxvxRdCbzyzwKbjVrzQHoBC+2RD/JrlLU0kf0 QpOY+L8MUt3nOyNd3GUIYJf9CmaM7pDlIlgW0F3HBVUFzV8gCIraEtEG0QFiEpbxPH5h K5iE9MgdTmnxJtemuB5oWvPhjCLHvRWGMiSYeYWZQlVxHoSHfb4EHFVZitQdq+pLSGtm T+C/guyuSc0l8+Wl99lqWAw3Y+45DamtEIdmRZ+NY0osXbow3ISdXHC2V5RiUAmfpxpS WJAwfHHqKAXzKdM9pXMjAvovf+vYQV1pQWvv6W4sM4db620snBnz6Nf56C1BEhR5AnUC ThnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ru2MJzHCsl8VSXcxUO4Bc7R3QXzGeOdTatqL62mo55s=; b=QfFVWkEpJMB4w9L+gzUwbxeu7sSBlnuOvn6PjKCDwDhtxl8qc4vVfHYNPEnmVuuJtU 0PHoemb+MgFXdYXyd5bULBSgUm330hSioi9tx4rmxn4fVRZIJxAnw9EdvloGioCIGREq DVQB7+dEcOAaiJQD/tDaFT+BMr7PKfRJacrfXxTEV8rJHXzvE8RzpwDDNg9g/IwdotwB ImwYrM4s3CiT6BXdGhMa0TGlE/bTNKHgn8aqqH55Xm6BiDEGVHQCdOI4RjpCdTKLEUX5 kSltojGOfOec7XttQew1oojb+As4A26/Ym0rLvvGMQ8Y/mlavVEAb1ySa7V2L/F2nL5k vGXw== X-Gm-Message-State: AOUpUlFhicCSG8bbsDplrLP7niaxNrE7c7yxFs3vShiGePYU0qct6r+I 2SnhbDDQRyCtTLAl8QW5SUUSkZ/K/H8= X-Google-Smtp-Source: AAOMgpdFIz0qw3oS4eZlEl7gCaDr1Stqwv/RvUdAK2yYLxF++Lkb/rlp+jeyQP77ZC1bPBVU62kGMw== X-Received: by 2002:a2e:291c:: with SMTP id u28-v6mr2591843lje.70.1531469549095; Fri, 13 Jul 2018 01:12:29 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 13 Jul 2018 10:12:11 +0200 Message-Id: <1531469533-31787-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531469533-31787-1-git-send-email-mw@semihalf.com> References: <1531469533-31787-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 4/6] Marvell/Library: Armada7k8kSoCDescLib: Introduce ICU information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescIcuGet ()), which dynamically allocates and fills MV_SOC_ICU_DESC structure with the SoC description of ICU (Interrupt Consolidation Unit). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 12 ++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 30 +++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 39 ++++++++++++++++++++ 3 files changed, 81 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 3072883..c14b985 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -44,6 +44,18 @@ #define MV_SOC_I2C_BASE(I2c) (0x701000 + ((I2c) * 0x100)) =20 // +// Platform description of ICU (Interrupt Consolidation Unit) controllers +// +#define ICU_GIC_MAPPING_OFFSET 0 +#define ICU_NSR_SET_SPI_BASE 0xf03f0040 +#define ICU_NSR_CLEAR_SPI_BASE 0xf03f0048 +#define ICU_SEI_SET_SPI_BASE 0xf03f0230 +#define ICU_SEI_CLEAR_SPI_BASE 0xf03f0230 +#define ICU_REI_SET_SPI_BASE 0xf03f0270 +#define ICU_REI_CLEAR_SPI_BASE 0xf03f0270 +#define ICU_GROUP_UNSUPPORTED 0x0 + +// // Platform description of MDIO controllers // #define MV_SOC_MDIO_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x12A200) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 30e6378..cdfb51b 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -61,6 +61,36 @@ ArmadaSoCDescI2cGet ( ); =20 // +// ICU (Interrupt Consolidation Unit) +// +typedef enum { + IcuGroupNsr =3D 0, + IcuGroupSr =3D 1, + IcuGroupLpi =3D 2, + IcuGroupVlpi =3D 3, + IcuGroupSei =3D 4, + IcuGroupRei =3D 5, + IcuGroupMax, +} ICU_GROUP; + +typedef struct { + ICU_GROUP Group; + UINTN SetSpiAddr; + UINTN ClrSpiAddr; +} ICU_MSI; + +typedef struct { + UINTN IcuSpiBase; + ICU_MSI IcuMsi[IcuGroupMax]; +} MV_SOC_ICU_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescIcuGet ( + IN OUT MV_SOC_ICU_DESC **IcuDesc + ); + +// // MDIO // typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 7184ab6..6902fda 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -103,6 +103,45 @@ ArmadaSoCDescI2cGet ( return EFI_SUCCESS; } =20 +// +// Allocate the MSI address per interrupt Group, +// unsupported Groups get NULL address. +// +STATIC +MV_SOC_ICU_DESC mA7k8kIcuDescTemplate =3D { + ICU_GIC_MAPPING_OFFSET, + { + /* Non secure interrupts */ + { IcuGroupNsr, ICU_NSR_SET_SPI_BASE, ICU_NSR_CLEAR_SPI_BASE }, + /* Secure interrupts */ + { IcuGroupSr, ICU_GROUP_UNSUPPORTED, ICU_GROUP_UNSUPPORTED }, + /* LPI interrupts */ + { IcuGroupLpi, ICU_GROUP_UNSUPPORTED, ICU_GROUP_UNSUPPORTED }, + /* Virtual LPI interrupts */ + { IcuGroupVlpi, ICU_GROUP_UNSUPPORTED, ICU_GROUP_UNSUPPORTED }, + /* System error interrupts */ + { IcuGroupSei, ICU_SEI_SET_SPI_BASE, ICU_SEI_CLEAR_SPI_BASE }, + /* RAM error interrupts */ + { IcuGroupRei, ICU_REI_SET_SPI_BASE, ICU_REI_CLEAR_SPI_BASE }, + } +}; + +EFI_STATUS +EFIAPI +ArmadaSoCDescIcuGet ( + IN OUT MV_SOC_ICU_DESC **IcuDesc + ) +{ + *IcuDesc =3D AllocateCopyPool (sizeof (mA7k8kIcuDescTemplate), + &mA7k8kIcuDescTemplate); + if (*IcuDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + return EFI_SUCCESS; +} + EFI_STATUS EFIAPI ArmadaSoCDescMdioGet ( --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 11:32:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531469565263364.7266196305851; Fri, 13 Jul 2018 01:12:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0A283209831EA; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id m29-v6sm6485484lfj.45.2018.07.13.01.12.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 01:12:29 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BQXNZX+tK0f0zTVaGvuugteuhhwYIf1zipypbi+gx9U=; b=IW7KitCze79TSZt0Jy9WoOSzymiBp1sIfXBLKrizcQAc38WnhzZbDHCH5CV6NnAb7e vURcoSCp3dvyH697zHaRPdsl/nClidc4Qe83XtAdalq6xQdXkXhbL048AW+BnmLVoe3h otd+3yt3drt6N2ZyPlQrXv+hyFhuBd9iEcpjO0RDDB86GVDcdhOzvxrvzi1qptvqix9O LRGx5HG7XYphy6j/cLbzgW7i/Z5for8mS69DJN/4DQS5SfZJRG+oAbo47ymg2Q083Fae uSPcUWnkdntE2hXWoEexsc0l1Ey5++5zrKtuc7ukF/cZDcfin8RoJSu1anhFgxhn9gQ4 dXDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BQXNZX+tK0f0zTVaGvuugteuhhwYIf1zipypbi+gx9U=; b=UhPvG1L5a3nzydqFL+UVJnprMN5M0khiNtmTKjcXtc6Js/TRdVtMjuGkjVDyztwwgK LenuEAtZ4fwGze1wlzrggAWxybBPT+dyTkajaydroFfuSJ2iNulPFwOVtPOpI2N0NpyF Tz5fcnMXbklgNsLUfqTjvUWJwKQrLvWYc6/1/C+z0eHVa/TAnrL23VPLaXa2eHeVCtmy fmkUJtF/+wV+tSP5zCG5mfvGExq17WIpQ33F+0oWvg/9GOth+86KyaS+mDiqfXGnA75w REZ14a6w3MDWQOPVcWNYBBZeIktCx65HX2UM+fdYKTraEbt7LEAEkSPVUnMw9sgxu0cL JPrA== X-Gm-Message-State: AOUpUlET8ikiYUhsu9PFhZijrkJHWyFnXh4gUc+vGEUmhDjwkXSQyWpv gSUk0bHlDluHu2XZtSsWj6U53TxCZbw= X-Google-Smtp-Source: AAOMgpdWoHTuTmiQU9Tb/uDVaayzvWpez7wSNUAKOIYIwGu8mfqhKTGvJJ0pzlQkAx5OxPgTTc6Rwg== X-Received: by 2002:a19:9d92:: with SMTP id g140-v6mr4501726lfe.85.1531469550366; Fri, 13 Jul 2018 01:12:30 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 13 Jul 2018 10:12:12 +0200 Message-Id: <1531469533-31787-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531469533-31787-1-git-send-email-mw@semihalf.com> References: <1531469533-31787-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 5/6] Marvell/Library: Implement common ArmadaIcuLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" ICU (Interrupt Consolidation Unit) is a mechanism, that allows to send-message based interrupts from the CP110 unit (South Bridge) to the Application Processor hardware block. After dispatching the interrupts in the GIC are generated. This patch adds a basic version of the library, that allows to configure a static mapping between CP110 interfaces and GICv2 of the Armada7k8k SoC family. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Library/IcuLib/IcuLib.inf | 38 +++ Silicon/Marvell/Library/IcuLib/IcuLib.h | 47 +++ Silicon/Marvell/Library/IcuLib/IcuLib.c | 317 ++++++++++++++++++++ 3 files changed, 402 insertions(+) create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.inf create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.h create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.c diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.inf b/Silicon/Marvell/Li= brary/IcuLib/IcuLib.inf new file mode 100644 index 0000000..0010141 --- /dev/null +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.inf @@ -0,0 +1,38 @@ +## @file +# +# Copyright (C) 2018, Marvell International Ltd. and its affiliates
+# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D IcuLib + FILE_GUID =3D 0301c9cb-43e6-40a8-96bf-41bd0501e86d + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaIcuLib + +[Sources] + IcuLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + ArmadaSoCDescLib + DebugLib + IoLib + PcdLib + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.h b/Silicon/Marvell/Libr= ary/IcuLib/IcuLib.h new file mode 100644 index 0000000..fba1115 --- /dev/null +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.h @@ -0,0 +1,47 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implemen= tation: +* ICU - Interrupt Consolidation Unit +* AP - Application Processor hardware block (Armada 7k8k incorporates AP8= 06) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ICU_REG_BASE(Cp) ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E0000 + +#define ICU_GROUP_REGISTER_BASE_OFFSET 0x10 +#define ICU_SET_SPI_AL(x) (0x10 + (ICU_GROUP_REGISTER_BASE_OFFSET * = x)) +#define ICU_SET_SPI_AH(x) (0x14 + (ICU_GROUP_REGISTER_BASE_OFFSET * = x)) +#define ICU_CLR_SPI_AL(x) (0x18 + (ICU_GROUP_REGISTER_BASE_OFFSET * = x)) +#define ICU_CLR_SPI_AH(x) (0x1c + (ICU_GROUP_REGISTER_BASE_OFFSET * = x)) +#define ICU_INT_CFG(x) (0x100 + (sizeof (UINT32) * x)) + +#define ICU_INT_ENABLE_OFFSET 24 +#define ICU_IS_EDGE_OFFSET 28 +#define ICU_GROUP_OFFSET 29 + +#define ICU_MAX_SUPPORTED_UNITS 2 +#define ICU_MAX_IRQS_PER_CP 64 + +#define MAX_ICU_IRQS 207 diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Libr= ary/IcuLib/IcuLib.c new file mode 100644 index 0000000..e88337c --- /dev/null +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c @@ -0,0 +1,317 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implemen= tation: +* ICU - Interrupt Consolidation Unit +* AP - Application Processor hardware block (Armada 7k8k incorporates AP8= 06) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +* +**/ + +#include "IcuLib.h" + +STATIC EFI_EVENT mEfiExitBootServicesEvent; + +STATIC CONST ICU_IRQ IrqMapNonSecure[] =3D { + {22, 0, IcuIrqTypeLevel}, /* PCIx4 INT A interrupt */ + {23, 1, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */ + {24, 2, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */ + {27, 3, IcuIrqTypeLevel}, /* SD/MMC */ + {33, 4, IcuIrqTypeLevel}, /* PPv2 DBG AXI monitor */ + {34, 4, IcuIrqTypeLevel}, /* HB1 AXI monitor */ + {35, 4, IcuIrqTypeLevel}, /* AP AXI monitor */ + {36, 4, IcuIrqTypeLevel}, /* PPv2 AXI monitor */ + {39, 5, IcuIrqTypeLevel}, /* PPv2 Irq */ + {40, 6, IcuIrqTypeLevel}, /* PPv2 Irq */ + {41, 7, IcuIrqTypeLevel}, /* PPv2 Irq */ + {43, 8, IcuIrqTypeLevel}, /* PPv2 Irq */ + {44, 9, IcuIrqTypeLevel}, /* PPv2 Irq */ + {45, 10, IcuIrqTypeLevel}, /* PPv2 Irq */ + {47, 11, IcuIrqTypeLevel}, /* PPv2 Irq */ + {48, 12, IcuIrqTypeLevel}, /* PPv2 Irq */ + {49, 13, IcuIrqTypeLevel}, /* PPv2 Irq */ + {51, 14, IcuIrqTypeLevel}, /* PPv2 Irq */ + {52, 15, IcuIrqTypeLevel}, /* PPv2 Irq */ + {53, 16, IcuIrqTypeLevel}, /* PPv2 Irq */ + {55, 17, IcuIrqTypeLevel}, /* PPv2 Irq */ + {56, 18, IcuIrqTypeLevel}, /* PPv2 Irq */ + {57, 19, IcuIrqTypeLevel}, /* PPv2 Irq */ + {59, 20, IcuIrqTypeLevel}, /* PPv2 Irq */ + {60, 21, IcuIrqTypeLevel}, /* PPv2 Irq */ + {61, 22, IcuIrqTypeLevel}, /* PPv2 Irq */ + {63, 23, IcuIrqTypeLevel}, /* PPv2 Irq */ + {64, 24, IcuIrqTypeLevel}, /* PPv2 Irq */ + {65, 25, IcuIrqTypeLevel}, /* PPv2 Irq */ + {67, 26, IcuIrqTypeLevel}, /* PPv2 Irq */ + {68, 27, IcuIrqTypeLevel}, /* PPv2 Irq */ + {69, 28, IcuIrqTypeLevel}, /* PPv2 Irq */ + {71, 29, IcuIrqTypeLevel}, /* PPv2 Irq */ + {72, 30, IcuIrqTypeLevel}, /* PPv2 Irq */ + {73, 31, IcuIrqTypeLevel}, /* PPv2 Irq */ + {78, 32, IcuIrqTypeLevel}, /* MG Irq */ + {79, 33, IcuIrqTypeLevel}, /* GPIO 56-63 */ + {80, 34, IcuIrqTypeLevel}, /* GPIO 48-55 */ + {81, 35, IcuIrqTypeLevel}, /* GPIO 40-47 */ + {82, 36, IcuIrqTypeLevel}, /* GPIO 32-39 */ + {83, 37, IcuIrqTypeLevel}, /* GPIO 24-31 */ + {84, 38, IcuIrqTypeLevel}, /* GPIO 16-23 */ + {85, 39, IcuIrqTypeLevel}, /* GPIO 8-15 */ + {86, 40, IcuIrqTypeLevel}, /* GPIO 0-7 */ + {88, 41, IcuIrqTypeLevel}, /* EIP-197 ring-0 */ + {89, 42, IcuIrqTypeLevel}, /* EIP-197 ring-1 */ + {90, 43, IcuIrqTypeLevel}, /* EIP-197 ring-2 */ + {91, 44, IcuIrqTypeLevel}, /* EIP-197 ring-3 */ + {92, 45, IcuIrqTypeLevel}, /* EIP-197 int */ + {95, 46, IcuIrqTypeLevel}, /* EIP-150 Irq */ + {102, 47, IcuIrqTypeLevel}, /* USB3 Device Irq */ + {105, 48, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */ + {106, 49, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */ + {107, 50, IcuIrqTypeLevel}, /* SATA Host-1 Irq */ + {109, 50, IcuIrqTypeLevel}, /* SATA Host-0 Irq */ + {115, 52, IcuIrqTypeLevel}, /* NAND Irq */ + {117, 53, IcuIrqTypeLevel}, /* SPI-1 Irq */ + {118, 54, IcuIrqTypeLevel}, /* SPI-0 Irq */ + {120, 55, IcuIrqTypeLevel}, /* I2C 0 Irq */ + {121, 56, IcuIrqTypeLevel}, /* I2C 1 Irq */ + {122, 57, IcuIrqTypeLevel}, /* UART 0 Irq */ + {123, 58, IcuIrqTypeLevel}, /* UART 1 Irq */ + {124, 59, IcuIrqTypeLevel}, /* UART 2 Irq */ + {125, 60, IcuIrqTypeLevel}, /* UART 3 Irq */ + {127, 61, IcuIrqTypeLevel}, /* GOP-3 Irq */ + {128, 62, IcuIrqTypeLevel}, /* GOP-2 Irq */ + {129, 63, IcuIrqTypeLevel}, /* GOP-0 Irq */ +}; + +/* + * SEI - System Error Interrupts + * Note: SPI ID 0-20 are reserved for North-Bridge + */ +STATIC ICU_IRQ IrqMapSei[] =3D { + {11, 21, IcuIrqTypeLevel}, /* SEI error CP-2-CP */ + {15, 22, IcuIrqTypeLevel}, /* PIDI-64 SOC */ + {16, 23, IcuIrqTypeLevel}, /* D2D error Irq */ + {17, 24, IcuIrqTypeLevel}, /* D2D Irq */ + {18, 25, IcuIrqTypeLevel}, /* NAND error */ + {19, 26, IcuIrqTypeLevel}, /* PCIx4 error */ + {20, 27, IcuIrqTypeLevel}, /* PCIx1_0 error */ + {21, 28, IcuIrqTypeLevel}, /* PCIx1_1 error */ + {25, 29, IcuIrqTypeLevel}, /* SDIO reg error */ + {75, 30, IcuIrqTypeLevel}, /* IOB error */ + {94, 31, IcuIrqTypeLevel}, /* EIP150 error */ + {97, 32, IcuIrqTypeLevel}, /* XOR-1 system error */ + {99, 33, IcuIrqTypeLevel}, /* XOR-0 system error */ + {108, 34, IcuIrqTypeLevel}, /* SATA-1 error */ + {110, 35, IcuIrqTypeLevel}, /* SATA-0 error */ + {114, 36, IcuIrqTypeLevel}, /* TDM-MC error */ + {116, 37, IcuIrqTypeLevel}, /* DFX server Irq */ + {117, 38, IcuIrqTypeLevel}, /* Device bus error */ + {147, 39, IcuIrqTypeLevel}, /* Audio error */ + {171, 40, IcuIrqTypeLevel}, /* PIDI Sync error */ +}; + +/* REI - RAM Error Interrupts */ +STATIC CONST ICU_IRQ IrqMapRei[] =3D { + {12, 0, IcuIrqTypeLevel}, /* REI error CP-2-CP */ + {26, 1, IcuIrqTypeLevel}, /* SDIO memory error */ + {87, 2, IcuIrqTypeLevel}, /* EIP-197 ECC error */ + {93, 3, IcuIrqTypeEdge}, /* EIP-150 RAM error */ + {96, 4, IcuIrqTypeLevel}, /* XOR-1 memory Irq */ + {98, 5, IcuIrqTypeLevel}, /* XOR-0 memory Irq */ + {100, 6, IcuIrqTypeEdge}, /* USB3 device tx parity */ + {101, 7, IcuIrqTypeEdge}, /* USB3 device rq parity */ + {103, 8, IcuIrqTypeEdge}, /* USB3H-1 RAM error */ + {104, 9, IcuIrqTypeEdge}, /* USB3H-0 RAM error */ +}; + +STATIC CONST ICU_CONFIG IcuInitialConfig =3D { + .NonSecure =3D { IrqMapNonSecure, ARRAY_SIZE (IrqMapNonSecure) }, + .Sei =3D { IrqMapSei, ARRAY_SIZE (IrqMapSei) }, + .Rei =3D { IrqMapRei, ARRAY_SIZE (IrqMapRei) }, +}; + +STATIC +VOID +IcuClearIrq ( + IN UINTN IcuBase, + IN UINTN Nr +) +{ + MmioWrite32 (IcuBase + ICU_INT_CFG (Nr), 0); +} + +STATIC +VOID +IcuSetIrq ( + IN UINTN IcuBase, + IN CONST ICU_IRQ *Irq, + IN UINTN SpiBase, + IN ICU_GROUP Group + ) +{ + UINT32 IcuInt; + + IcuInt =3D (Irq->SpiId + SpiBase) | (1 << ICU_INT_ENABLE_OFFSET); + IcuInt |=3D Irq->IrqType << ICU_IS_EDGE_OFFSET; + IcuInt |=3D Group << ICU_GROUP_OFFSET; + + MmioWrite32 (IcuBase + ICU_INT_CFG (Irq->IcuId), IcuInt); +} + +STATIC +VOID +IcuConfigure ( + IN UINTN CpIndex, + IN MV_SOC_ICU_DESC *IcuDesc, + IN CONST ICU_CONFIG *Config + ) +{ + UINTN IcuBase, Index, SpiOffset, SpiBase; + CONST ICU_IRQ *Irq; + ICU_MSI *Msi; + + /* Get ICU registers base address */ + IcuBase =3D ICU_REG_BASE (CpIndex); + /* Get the base of the GIC SPI ID in the MSI message */ + SpiBase =3D IcuDesc->IcuSpiBase; + /* Get multiple CP110 instances SPI ID shift */ + SpiOffset =3D CpIndex * ICU_MAX_IRQS_PER_CP; + /* Get MSI addresses per interrupt group */ + Msi =3D IcuDesc->IcuMsi; + + /* Set the address for SET_SPI and CLR_SPI registers in AP */ + for (Index =3D 0; Index < IcuGroupMax; Index++, Msi++) { + MmioWrite32 (IcuBase + ICU_SET_SPI_AL (Msi->Group), + Msi->SetSpiAddr & 0xFFFFFFFF); + MmioWrite32 (IcuBase + ICU_SET_SPI_AH (Msi->Group), Msi->SetSpiAddr >>= 32); + MmioWrite32 (IcuBase + ICU_CLR_SPI_AL (Msi->Group), + Msi->ClrSpiAddr & 0xFFFFFFFF); + MmioWrite32 (IcuBase + ICU_CLR_SPI_AH (Msi->Group), Msi->ClrSpiAddr >>= 32); + } + + /* Mask all ICU interrupts */ + for (Index =3D 0; Index < MAX_ICU_IRQS; Index++) { + IcuClearIrq (IcuBase, Index); + } + + /* Configure the ICU interrupt lines */ + Irq =3D Config->NonSecure.Map; + for (Index =3D 0; Index < Config->NonSecure.Size; Index++, Irq++) { + IcuSetIrq (IcuBase, Irq, SpiBase + SpiOffset, IcuGroupNsr); + } + + Irq =3D Config->Sei.Map; + for (Index =3D 0; Index < Config->Sei.Size; Index++, Irq++) { + IcuSetIrq (IcuBase, Irq, SpiBase, IcuGroupSei); + } + + Irq =3D Config->Rei.Map; + for (Index =3D 0; Index < Config->Rei.Size; Index++, Irq++) { + IcuSetIrq (IcuBase, Irq, SpiBase, IcuGroupRei); + } +} + +STATIC +VOID +IcuClearGicSpi ( + IN UINTN CpIndex, + IN MV_SOC_ICU_DESC *IcuDesc + ) +{ + CONST ICU_CONFIG *Config; + UINTN Index, SpiOffset, SpiBase; + CONST ICU_IRQ *Irq; + ICU_MSI *Msi; + + Config =3D &IcuInitialConfig; + + /* Get the base of the GIC SPI ID in the MSI message */ + SpiBase =3D IcuDesc->IcuSpiBase; + /* Get multiple CP110 instances SPI ID shift */ + SpiOffset =3D CpIndex * ICU_MAX_IRQS_PER_CP; + /* Get MSI addresses per interrupt group */ + Msi =3D IcuDesc->IcuMsi; + + /* Clear ICU-generated GIC SPI interrupts */ + Irq =3D Config->NonSecure.Map; + for (Index =3D 0; Index < Config->NonSecure.Size; Index++, Irq++) { + MmioWrite32 (Msi->ClrSpiAddr, Irq->SpiId + SpiBase + SpiOffset); + } +} + +VOID +EFIAPI +IcuCleanUp ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + MV_SOC_ICU_DESC *IcuDesc; + UINTN CpCount, CpIndex; + + IcuDesc =3D Context; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + if (CpCount > ICU_MAX_SUPPORTED_UNITS) { + CpCount =3D ICU_MAX_SUPPORTED_UNITS; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + IcuClearGicSpi (CpIndex, IcuDesc); + } +} + +EFI_STATUS +EFIAPI +ArmadaIcuInitialize ( + ) +{ + MV_SOC_ICU_DESC *IcuDesc; + UINTN CpCount, CpIndex; + EFI_STATUS Status; + + /* + * Due to limited amount of interrupt lanes, only 2 units can be + * wired to the GIC. + */ + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + if (CpCount > ICU_MAX_SUPPORTED_UNITS) { + DEBUG ((DEBUG_ERROR, + "%a: Default ICU to GIC mapping is available for maximum %d CP110 un= its", + ICU_MAX_SUPPORTED_UNITS, + __FUNCTION__)); + CpCount =3D ICU_MAX_SUPPORTED_UNITS; + } + + /* Obtain SoC description of the ICU */ + Status =3D ArmadaSoCDescIcuGet (&IcuDesc); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Configure default ICU to GIC interrupt mapping for each CP110 */ + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + IcuConfigure (CpIndex, IcuDesc, &IcuInitialConfig); + } + + /* + * In order to be immune to the OS capability of clearing ICU-generated + * GIC interrupts, register ExitBootServices event, that will + * make sure they remain disabled during OS boot. + */ + Status =3D gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + IcuCleanUp, + IcuDesc, + &mEfiExitBootServicesEvent); + + return Status; +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 11:32:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1531469569301362.16631286273696; Fri, 13 Jul 2018 01:12:49 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 34FCA20986AC0; Fri, 13 Jul 2018 01:12:35 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A228F209831EA for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id m29-v6sm6485484lfj.45.2018.07.13.01.12.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 01:12:30 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4xVjUC5Zz/Ns+a8DbrJpbgKHs7eiuKY0WO9b2UZDMtY=; b=SmdzJ7rf0/GT1I7/1oJHQdb6xLsepRT/GycAUHN2ucRcobAReSdoqBg0oEUrFEQFfU E4xpWG3HFxrbb2dnUbIru+fQ2FcRrMOfkH0vTkS1BNt9NGZbWHystNYOfRER9sEGVBc9 OPrexyqz8SuarEAwp6mvypUE7kbXmYfqZ2R4rkOAHY76MdKXvA9XCqcxOMqhNxNk7976 s0hneWlhG3aSfSPe7x30gvGo6UXJD0upciTxV9/uV+nRaA48uiUYno1IzzNzZeCzUqzP EdAcKGI6AM8vmvNnRutpIkrf/ORT4pB9bWLkju2vEV5xZ1MMYKR3kD4DFTRmCjkXKhWg 07jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4xVjUC5Zz/Ns+a8DbrJpbgKHs7eiuKY0WO9b2UZDMtY=; b=H9k4mwhQeChiQdchqef81pRHXV70BC9HPjXlHoG4oeuHUIGgiTjKUoV4JM300I9dUv tntDjAiBOwp5tW404ZK9S/eC+jP7zinSQUSb14iZFt9tDExPFJL0yl/paav/9o7oABCP WKrsMoln1yr59Zz1f48Y4SoDxMk+JJ2BgwQ6JnE8qNwmzxRcNqXyYrYKIuJ/OPaps/QY yF6JlQIvsKTtNjJA6FPB4UpQzSZAd5Ig/BGYaJOpdkyx7/tZkuGhvZi0nc17KtYZgXwI Gbewnj3pYzNxlAtq5gFBuhX8ebHwV+3wipi4BxJ/jgZg6I9jNnbjC+GOS95V59pISIP3 BIlw== X-Gm-Message-State: AOUpUlFQbtQwccGPWSWfgkj3acjZJBR6x0m+MLQ5TQPm+HE/HOpJgQu/ LSSZWsCWYG4AARK0wLDACaMYQIRMYW8= X-Google-Smtp-Source: AAOMgpehc27f6xDv3zesrjlazEhAEyYR99dLVyRogedBGrQRLItEgMRzwY4oQux4m6sI56edVfNvZw== X-Received: by 2002:a19:6801:: with SMTP id d1-v6mr4401597lfc.8.1531469551631; Fri, 13 Jul 2018 01:12:31 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 13 Jul 2018 10:12:13 +0200 Message-Id: <1531469533-31787-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531469533-31787-1-git-send-email-mw@semihalf.com> References: <1531469533-31787-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 6/6] Marvell/Armada7k8k: Enable ICU configuration X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jaz@semihalf.com, hannah@marvell.com, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch enables the ICU (Interrupt Consolidation Unit) configuration in the common platform initialization driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 + Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf | 1 + Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index a9d67a2..27b14ed 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -32,6 +32,7 @@ #SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # [LibraryClasses.common] + ArmadaIcuLib|Silicon/Marvell/Library/IcuLib/IcuLib.inf ArmadaSoCDescLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.inf ArmPlatformLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k= 8kLib.inf ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf= b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf index 803dc6e..5503463 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -30,6 +30,7 @@ Silicon/Marvell/Marvell.dec =20 [LibraryClasses] + ArmadaIcuLib ComPhyLib DebugLib MppLib diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c b= /Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c index 1efad77..18b6783 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c @@ -12,6 +12,7 @@ =20 **/ =20 +#include #include #include #include @@ -40,6 +41,7 @@ ArmadaPlatInitDxeEntryPoint ( MvComPhyInit (); UtmiPhyInit (); MppInitialize (); + ArmadaIcuInitialize (); =20 return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel