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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.58.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:58:59 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uC8ehs3vn4/x5anhCPtGcfolGeG4A3qKocYcrAD1ykg=; b=zrKDs4TCAfKlhyeT7jl4+Tcpn0VCeRU9GEHn7QSZ8hbVQ+BmypxoJXfDYLFQOhPBPZ hrjEvosCpdI3uwHE9ZcUFUzZRR+dfTT1FuCZLp7YyLzrYg/WUTDM+avnGsJeQCI3iwjO taD8qWyZdfzXchpZeKIVT2Ukn7aW1zzhWgrjEOJDOfHEqNNS/fuSu029Rc0duiXejSCu ULI21CVPjblmjp96MSCiMZfeFo7h8wke05aLmBmqjUh8EkqAo4vE6xgEcnDNMASOF35p h0yeQTBKwBZtb09vWwzsBbN3ranTdpZ2RkiEiy6gACq229ES/pRPh4Ekb3TIKs3+BLxj /HPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uC8ehs3vn4/x5anhCPtGcfolGeG4A3qKocYcrAD1ykg=; b=W1bYfaXNRqN7TZ6ScVaDPH4ofIFTzLESsElQHUS3dRGDL2JaTFVw5D/0ASwiGnDwFj 9ogOipVKN0krhzzf+4Pj7rJuate051E69Px8ySAHRnocvVh+lC5fxWMDWpwQTcseyDO/ A4Onf1qkL0JljIU7cuQLEpdTqc4eTHX8eq5bH1cunbbp9OPwsf0F7d3C8MUUD54aN9ib /2jBDlFBD8vr8sUvkmZ7ntYFAUCgYMGzesHJtJVly+3dRB5ggPJxvnBRHsz4hqq8+Hvs /wr58FNljHCiBFdaMGcQQnnt2MY4BWCYJhr0fnUkcMrlzqfN7VGN3pSoMkBLrHiUgVXl DClg== X-Gm-Message-State: APt69E1YzcmlVentoFdOVZcWKZFOiJhwKEIAvVHzffeQPuIy8NzbPx0s jXh8lAbRn/xfX+gZwbdXyeNgQbWiL3I= X-Google-Smtp-Source: ADUXVKLaJeegjuz8oOi8g9xeenQsWv37qtuDX7/1xz0ToGPoyCv5Zh0ryR8YXFvafXNJfm7Le1BXxw== X-Received: by 2002:a2e:1bcb:: with SMTP id c72-v6mr9801455ljf.99.1529362740263; Mon, 18 Jun 2018 15:59:00 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:20 +0200 Message-Id: <1529362724-9244-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 01/25] Marvell/Library: Introduce ArmadaSoCDescLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua ArmadaSoCDescLib is a per SoC family library, which provides SoC description, like register base of some hardware module controller, COMPHY/I2C/NETWORK etc., which right now is hardcoded in MvHwDescLib.h. There will be a new protocol, which gets SoC description from this library, and provides board description based on enable/disable values of each hardware module controller in dsc file. As a first example implement obtaining UTMI controllers information. Remaining interfaces will be added in follow-up commits. This patch introduces new library callback (ArmadaSoCDescUtmiGet ()), which dynamically allocates and fills MV_SOC_UTMI_DESC structure, SoC description of UTMI PHYs. A new PCD is introduced (PcdMaxCpCount) which stores maximal amount of CP110 blocks in the SoC family. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Marvell.dec = | 4 ++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.inf | 37 +++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 35 +++++++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 33 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 65 ++++++++++++++++++++ 5 files changed, 174 insertions(+) create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.inf create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.h create mode 100644 Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.c diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index be74b4e..2a92eff 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -60,6 +60,7 @@ gMarvellSpiFlashDxeGuid =3D { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, = 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } =20 [LibraryClasses] + ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h SampleAtResetLib|Include/Library/SampleAtResetLib.h =20 [Protocols] @@ -68,6 +69,9 @@ gMarvellPlatformInitCompleteProtocolGuid =3D { 0x465b8cf7, 0x016f, 0x4ba= 6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } } =20 [PcdsFixedAtBuild.common] +#Board description + gMarvellTokenSpaceGuid.PcdMaxCpCount|0x2|UINT8|0x30000072 + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001 =20 diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLi= b/Armada7k8kSoCDescLib.inf new file mode 100644 index 0000000..2b73b73 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.inf @@ -0,0 +1,37 @@ +## @file +# +# Copyright (C) 2018, Marvell International Ltd. and its affiliates
+# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Armada7k8kDescLib + FILE_GUID =3D c64f0048-4ca3-4573-b0a6-c2e9e6457285 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmadaSoCDescLib + +[Sources] + Armada7k8kSoCDescLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + PcdLib + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h new file mode 100644 index 0000000..c5711b0 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -0,0 +1,35 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implemen= tation: +* AP - Application Processor hardware block (Armada 7k8k incorporates AP8= 06) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +**/ + +#ifndef __ARMADA7K8K_SOC_DESC_LIB_H__ +#define __ARMADA7K8K_SOC_DESC_LIB_H__ + +// +// Common macros +// +#define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000)) + +// +// Platform description of UTMI PHY's +// +#define MV_SOC_UTMI_PER_CP_COUNT 2 +#define MV_SOC_UTMI_ID(Utmi) (Utmi) +#define MV_SOC_UTMI_BASE(Utmi) (0x580000 + ((Utmi) * 0x1000)) +#define MV_SOC_UTMI_CFG_BASE 0x440440 +#define MV_SOC_UTMI_USB_CFG_BASE 0x440420 + +#endif diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h new file mode 100644 index 0000000..0d45684 --- /dev/null +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -0,0 +1,33 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#ifndef __ARMADA_SOC_DESC_LIB_H__ +#define __ARMADA_SOC_DESC_LIB_H__ + +// +// UTMI PHY devices SoC description +// +typedef struct { + UINT8 UtmiPhyId; + UINTN UtmiBaseAddress; + UINTN UtmiConfigAddress; + UINTN UsbConfigAddress; +} MV_SOC_UTMI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescUtmiGet ( + IN OUT MV_SOC_UTMI_DESC **UtmiDesc, + IN OUT UINTN *DescCount + ); +#endif /* __ARMADA_SOC_DESC_LIB_H__ */ diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c new file mode 100644 index 0000000..63fb224 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -0,0 +1,65 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implemen= tation: +* AP - Application Processor hardware block (Armada 7k8k incorporates AP8= 06) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +**/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "Armada7k8kSoCDescLib.h" + +EFI_STATUS +EFIAPI +ArmadaSoCDescUtmiGet ( + IN OUT MV_SOC_UTMI_DESC **UtmiDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_UTMI_DESC *Desc; + UINTN CpCount, CpIndex, Index, UtmiIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *DescCount =3D CpCount * MV_SOC_UTMI_PER_CP_COUNT; + Desc =3D AllocateZeroPool (*DescCount * sizeof (MV_SOC_UTMI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *UtmiDesc =3D Desc; + + UtmiIndex =3D 0; + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_UTMI_PER_CP_COUNT; Index++) { + Desc->UtmiPhyId =3D MV_SOC_UTMI_ID (UtmiIndex); + Desc->UtmiBaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_BAS= E (Index); + Desc->UtmiConfigAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_C= FG_BASE; + Desc->UsbConfigAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_UTMI_US= B_CFG_BASE; + Desc++; + UtmiIndex++; + } + } + + return EFI_SUCCESS; +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362748997123.25847013390785; Mon, 18 Jun 2018 15:59:08 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1502121109FE6; Mon, 18 Jun 2018 15:59:06 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6DD93211093AB for ; Mon, 18 Jun 2018 15:59:03 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id u5-v6so5931995lff.13 for ; Mon, 18 Jun 2018 15:59:03 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:00 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+lN9UQE+rRm5n1BZPza6g+loU+Hw3BoX8N8yXY24gZ4=; b=SLFOVfFNO87NKbKjRCaNN3xmv4vbYgqRQ3+ggbw0aM8xkRNZt5ZMBZcovhUtvGrYNK QlnfpNzgJFDjcp7dOXtlYMq8Nug72OUbQGfaIpfBFFLBIpF/fPmRieFfKP4ivAHEOiBF FW0JQg0lm/PkI1m0kDxchA0l0r1+a4mjD/Bs/d0Wj23//nX1byuFzmjMGxL9vTcN/EXq b8LdUkFUb5PopbxxxCGcmXEFmAwe3Tp5c0iXqyP+P4FwAqEn6SbUPoEseAkdrvdHJ+ww JG/dXlmi6sXk8hfHWxtBdti2zl1GKpj9/AYzpudIM0zH/re0OJKpsQ6+51/uD/jV0Igk 8PnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+lN9UQE+rRm5n1BZPza6g+loU+Hw3BoX8N8yXY24gZ4=; b=OFW+u2MOVA9b/fMuUjLJTr7DzCz2zpf6JMgAEnu+439pl/bGomBpuzpJsRdO0WVQPY e5mIEzwCE8bpmG6qdjdG3Qz2FusMS2rHQWzRDpESMM3FlkrikHnHlhsgw75/BMKnvfDz hHlilvm78ce1FFBVaBZrQdIf1F/yWgBNi3PRqxDNkEk09P7Lgt6juGvDOA2Ho8ZikLpu GeEduG7iS/QDQmH7aPb7APU8cX9anSarDF9LGqqsHsWIgAKRI8hcPh5uJwzsP0ZPn86P MmuNj9+SLniTKzpgN2Jbd3Vy8TOwrgU7sXnkDeRn5O94h6eywvkKP3P0PCW6qZW33w4W 0wFA== X-Gm-Message-State: APt69E1R8S/dBuVfV8qxi2u1x/wW5nAZTJYO542cDB56Jcyf8ZcBUosa MXS/Yk3ajjz10aZiM1Ayd58dLRPwBkY= X-Google-Smtp-Source: ADUXVKI4urL/2XUj9wsqeC6l7Sy9yyzdWpP4q8B0c0CdJy2RejVmD1tovWedj45LbHbQck7t2sMklw== X-Received: by 2002:a2e:2ac3:: with SMTP id q186-v6mr9710110ljq.44.1529362741441; Mon, 18 Jun 2018 15:59:01 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:21 +0200 Message-Id: <1529362724-9244-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 02/25] Marvell/Library: Introduce ArmadaBoardDescLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds a new library class that will be helpful to describe a per-board information, which will be processed by BoardDesc protocol. Together with ArmadaSoCDescLib data it will be a flexible solution allowing to provide complete information to the drivers, replacing faulty MvHwDescLib.h. Initially ArmadaBoardDescLib defines per-board UTMI PHYs information structure. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Marvell.dec | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 27 ++++++++++++++++= ++++ 2 files changed, 28 insertions(+) create mode 100644 Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 2a92eff..db49300 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -60,6 +60,7 @@ gMarvellSpiFlashDxeGuid =3D { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, = 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } =20 [LibraryClasses] + ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h SampleAtResetLib|Include/Library/SampleAtResetLib.h =20 diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h new file mode 100644 index 0000000..068535a --- /dev/null +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -0,0 +1,27 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates +* +* This program and the accompanying materials are licensed and made avail= able +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#ifndef __ARMADA_BOARD_DESC_LIB_H__ +#define __ARMADA_BOARD_DESC_LIB_H__ + +#include + +// +// UTMI PHY devices per-board description +// +typedef struct { + MV_SOC_UTMI_DESC *SoC; + UINTN UtmiDevCount; + UINTN UtmiPortType; +} MV_BOARD_UTMI_DESC; +#endif /* __ARMADA_SOC_DESC_LIB_H__ */ --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362752065530.9893748697012; Mon, 18 Jun 2018 15:59:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 476E421109FEA; Mon, 18 Jun 2018 15:59:07 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 969BE21109FE1 for ; Mon, 18 Jun 2018 15:59:04 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id x13-v6so11719271lff.10 for ; Mon, 18 Jun 2018 15:59:04 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:01 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0gFR3RZNLnWaUVpSHyLHVf/k77e6Vnjviw3V+GPJIC8=; b=qmuDuxgus1VCoidTXos2jx0f+sMD3gKAG9upaqEalh1wUkHGyRxyxE+Brk2VZQFIKn WzY8uTelk5pC23nYxU9ZTtH54VUSCw/4cLUsAozp2opxtJVfXISLvry3zYoHLKccshf1 JOSOG9v3W0Emn5RK0fqqWFf6e0xJmiRIhQzeKnR9LjpVhoo04Tg071eJDw+5M53/gbgX K9KSfRouDcw2ZuDOVl8u8ANVS0NLL1WeLATeeINfpPLMW1LJWELLRyWsXve49Vt4REoV XLZBzJDx1bQ1aeoIFvDgjKYfGGjwBLEI+UhjidMPvHPFXXBJoChmU30sXBV1gSF1l4uJ AiLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0gFR3RZNLnWaUVpSHyLHVf/k77e6Vnjviw3V+GPJIC8=; b=X/sUz32YK+kxlJaSBkKSpcnfAA7b9LBzirDmoRwrqfSf5xp77aa0Ntc22t7kaSqf8b RoCdsa9KtX3tseG/BKrCq5qk8Xx2riIX/23daXTpUv+tlJgU0YkgB0b9glt78QKls38S hHMxS80/POrPhnW8osgLR9R5RTrPDciCKx7grGDOtg0eHHsuTqIaK34vqH8zwT9R9V+5 XU3HI3zZytwnA9ApdiclWcb/RBmBx2XDRaSkPGUyJgCcmqHWcIqTMZTADJN5cHGzGvat Je7j+mP9QS5zwdJbgybuoQWoprZAafJuJDVP7j2Wc0Ri2kUpqPfJCotWJ3d9mtw0GJvd SBzQ== X-Gm-Message-State: APt69E3hukitXXe+VxfTRNlRdkiB4X+gce9sErXf1uglYizkGQ/6jqCz ZYNzyz4DvSzKM2LbphxsaYC0cjFLUks= X-Google-Smtp-Source: ADUXVKIRrTTIkJIjnUBJIFVkQg2i+iVRneVvDr4TKmlwrzMfJDHQ6MIkbsGU0Ry19+g6zpmj9eLF5Q== X-Received: by 2002:a2e:2408:: with SMTP id k8-v6mr2065563ljk.95.1529362742645; Mon, 18 Jun 2018 15:59:02 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:22 +0200 Message-Id: <1529362724-9244-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 03/25] Marvell: Introduce MARVELL_BOARD_DESC_PROTOCOL X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua This patch introduces protocol that exposes generic API to get board description. It uses ArmadaSoCDescLib library, which is implemented per SoC family to get the SoC level description for hardware module controller. Together with the information obtained from ArmadaBoardDescLib the protocol allows the drivers to get per-board information about used hardware and settings. As a first usage a UTMI information obtaining is implemented. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Marvell.dec | 1 + Silicon/Marvell/Include/Protocol/BoardDesc.h | 62 ++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 Silicon/Marvell/Include/Protocol/BoardDesc.h diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index db49300..6861cc4 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -212,6 +212,7 @@ gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001 =20 [Protocols] + gMarvellBoardDescProtocolGuid =3D { 0xebed8738, 0xd4a6, 0x400= 1, { 0xa9, 0xc9, 0x52, 0xb0, 0xcb, 0x7d, 0xdb, 0xf9 }} gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} gMarvellPhyProtocolGuid =3D { 0x32f48a43, 0x37e3, 0x4ac= f, { 0x93, 0xc4, 0x3e, 0x57, 0xa7, 0xb0, 0xfb, 0xdc }} diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h new file mode 100644 index 0000000..f8a2902 --- /dev/null +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -0,0 +1,62 @@ +/*************************************************************************= ****** +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ +#ifndef __MARVELL_BOARD_DESC_PROTOCOL_H__ +#define __MARVELL_BOARD_DESC_PROTOCOL_H__ + +#include +#include + +extern EFI_GUID gMarvellBoardDescProtocolGuid; + +typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOARD_DESC_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_UTMI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_UTMI_DESC **UtmiDesc + ); + +typedef +VOID +(EFIAPI *MV_BOARD_DESC_FREE) ( + IN VOID *BoardDesc + ); + +struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; + MV_BOARD_DESC_FREE BoardDescFree; +}; + +#endif // __MARVELL_BOARD_DESC_PROTOCOL_H__ --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362755222610.4603152846431; Mon, 18 Jun 2018 15:59:15 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 783F021107850; Mon, 18 Jun 2018 15:59:09 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E42C921109FE1 for ; Mon, 18 Jun 2018 15:59:05 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id d24-v6so27166243lfa.8 for ; Mon, 18 Jun 2018 15:59:05 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:03 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P+osxdU7MCPtvT4atWOBrg8T5d7Gctp0DkhTVObEp9g=; b=LZlhzymK+xNqCGtNyoFDAdACK5E7P66AjKYyVd3MAfoi8hz+H5WxPLaFVJKF9qaBV5 oGiqjPWTQBwaIy0wvqxm/1YyThoiT5HLLOhG2T0JBu2d/BlA1sfR1q9KKcPcZ/B/+uk6 FTMXMEDNlqILKpiw85/r7VZ3ser96rk0sMzbndMGWVeTvgXHaFXszXvs4YRiSGk5TtyX YNNAXqajwxVVm/6lGIGE3/fXeLrC68rt/KH9ReAUc/ncMTD1XouUmBg2u8lUSQeDsoZI uAmajwq6YLTtQcG2IWVTOd8vJXRrqisPoouWqYomnitKBdlYLXDb4KskCUcGIhLUR/Ew 1Y+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P+osxdU7MCPtvT4atWOBrg8T5d7Gctp0DkhTVObEp9g=; b=r1g8KForsh3Yc0wfZOGLmhkweTv/Lx+hnWELaolfH5RUANdgs3wxdVxT7rkTUDgIHG r9GOeCBibeR/DMk1Gluz8HcPlNRTG8XO6jKvUEY9CgB4rzflLiGj9nNxU61lFK+y+FQq HsK4Js5Rk3lQbvfflKa9/xhoixknlXWczJv8UibFb8vqzRyotAtBVDN1baKPfjsAiVaz +XlQ3Knkmmp3eaIi3/G0rzbZZHig1GfLPxyJM+ribbTuFuL4hSWIY2fWKNVqOzL8M0XS qFuey4l6X01wl5rbp5U3vEHH+bichVWmqm9DXTlunn4wJJMHwd33OG13GZ2Y9wtfIeyB S69w== X-Gm-Message-State: APt69E22vmauahdBV1mPcsG0/tXBDEYvMpFTOQtkUbtwa9GJmnWAE01B /GW82OxxiAG8GRCEhu4hLfMakV0Gexo= X-Google-Smtp-Source: ADUXVKIjkCGNNquDYsUQJeGXWnJKgjR3bvjmKLeH9n6Wd03d4sj7bMkvmSM7WcOeWBjIUo/2v/O3ZA== X-Received: by 2002:a2e:5d5d:: with SMTP id r90-v6mr9176063ljb.125.1529362743911; Mon, 18 Jun 2018 15:59:03 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:23 +0200 Message-Id: <1529362724-9244-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 04/25] Marvell/Drivers: MvBoardDesc: Introduce board description driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua This patch introduces a producer of MARVELL_BOARD_DESC_PROTOCOL, which gets SoC description from ArmadaSoCDescLib, then based on dsc file, provide only enabled hardware module controllers for the consumers, which are typically controllers' drivers. Thanks to that there is a separation between obtaining the platform description and the drivers. A first example of the board description callback is information about UTMI controllers and type. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 65 ++++++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h | 57 +++++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 176 +++++++++++++++= +++++ 3 files changed, 298 insertions(+) create mode 100644 Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf create mode 100644 Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h create mode 100644 Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf new file mode 100644 index 0000000..5da5f21 --- /dev/null +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -0,0 +1,65 @@ +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute +# and/or modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are m= et: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPO= SE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE +# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTI= AL +# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS = OR +# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEV= ER +# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABI= LITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF TH= E USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D BoardDescDxe + FILE_GUID =3D 4ed385f9-5d2c-4774-95c5-d5d9d70b3c37 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D MvBoardDescEntryPoint + +[Sources] + MvBoardDescDxe.c + MvBoardDescDxe.h + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + ArmadaSoCDescLib + DebugLib + MemoryAllocationLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gMarvellBoardDescProtocolGuid + +[Pcd] + gMarvellTokenSpaceGuid.PcdPciEXhci + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled + gMarvellTokenSpaceGuid.PcdUtmiPortType + +[Depex] + TRUE diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.h new file mode 100644 index 0000000..2813f0d --- /dev/null +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.h @@ -0,0 +1,57 @@ +/*************************************************************************= ****** +Copyright (C) 2018 Marvell International Ltd. +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ +#ifndef __MV_BOARD_DESC_H__ +#define __MV_BOARD_DESC_H__ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#define MV_BOARD_DESC_SIGNATURE SIGNATURE_64 ('M', 'V', 'B', 'R', 'D', 'D'= , 'S', 'C') + +typedef struct { + MARVELL_BOARD_DESC_PROTOCOL BoardDescProtocol; + UINTN Signature; + EFI_HANDLE Handle; + EFI_LOCK Lock; +} MV_BOARD_DESC; + +#endif // __MV_BOARD_DESC_H__ diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c new file mode 100644 index 0000000..0232a21 --- /dev/null +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -0,0 +1,176 @@ +/*************************************************************************= ****** +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ +#include "MvBoardDescDxe.h" + +MV_BOARD_DESC *mBoardDescInstance; + +STATIC +EFI_STATUS +MvBoardDescUtmiGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_UTMI_DESC **UtmiDesc + ) +{ + UINT8 *UtmiDeviceEnabled, *XhciDeviceEnabled, *UtmiPortType; + UINTN UtmiCount, UtmiDeviceTableSize, UtmiIndex, Index; + MV_BOARD_UTMI_DESC *BoardDesc; + MV_SOC_UTMI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available UTMI controllers */ + Status =3D ArmadaSoCDescUtmiGet (&SoCDesc, &UtmiCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled Utmi PHY's, + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + UtmiDeviceEnabled =3D PcdGetPtr (PcdUtmiControllersEnabled); + if (UtmiDeviceEnabled =3D=3D NULL) { + /* No UTMI PHY on platform */ + return EFI_SUCCESS; + } + + /* Make sure XHCI controllers table is present */ + XhciDeviceEnabled =3D PcdGetPtr (PcdPciEXhci); + if (XhciDeviceEnabled =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Missing PcdPciEXhci\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + UtmiDeviceTableSize =3D PcdGetSize (PcdUtmiControllersEnabled); + + /* Check if PCD with UTMI PHYs is correctly defined */ + if ((UtmiDeviceTableSize > UtmiCount) || + (UtmiDeviceTableSize > PcdGetSize (PcdPciEXhci))) { + DEBUG ((DEBUG_ERROR, + "%a: Wrong PcdUtmiControllersEnabled format\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Obtain port type table - also stored as UINT8 array */ + UtmiPortType =3D PcdGetPtr (PcdUtmiPortType); + if ((UtmiPortType =3D=3D NULL) || + (PcdGetSize (PcdUtmiPortType) !=3D UtmiDeviceTableSize)) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdUtmiPortType format\n", __FUNCTION_= _)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (UtmiDeviceTableSize * sizeof (MV_BOARD_U= TMI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + UtmiIndex =3D 0; + for (Index =3D 0; Index < UtmiDeviceTableSize; Index++) { + if (!UtmiDeviceEnabled[Index]) { + continue; + } + + /* UTMI PHY without enabled XHCI controller is useless */ + if (!XhciDeviceEnabled[Index]) { + DEBUG ((DEBUG_ERROR, + "%a: Disabled Xhci controller %d\n", + Index, + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + BoardDesc[UtmiIndex].SoC =3D &SoCDesc[Index]; + BoardDesc[UtmiIndex].UtmiPortType =3D UtmiPortType[Index]; + UtmiIndex++; + } + + BoardDesc->UtmiDevCount =3D UtmiIndex; + + *UtmiDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +VOID +MvBoardDescFree ( + IN VOID *BoardDesc + ) +{ + FreePool (BoardDesc); +} + +STATIC +EFI_STATUS +MvBoardDescInitProtocol ( + IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol + ) +{ + BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; + BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MvBoardDescEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mBoardDescInstance =3D AllocateZeroPool (sizeof (MV_BOARD_DESC)); + if (mBoardDescInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + MvBoardDescInitProtocol (&mBoardDescInstance->BoardDescProtocol); + + mBoardDescInstance->Signature =3D MV_BOARD_DESC_SIGNATURE; + + Status =3D gBS->InstallMultipleProtocolInterfaces (&(mBoardDescInstance-= >Handle), + &gMarvellBoardDescProtocolGuid, + &(mBoardDescInstance->BoardDescProtocol)); + if (EFI_ERROR (Status)) { + FreePool (mBoardDescInstance); + return Status; + } + + return EFI_SUCCESS; +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362759285969.7224860180345; Mon, 18 Jun 2018 15:59:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A179921109FE5; Mon, 18 Jun 2018 15:59:09 -0700 (PDT) Received: from mail-lf0-x22d.google.com (mail-lf0-x22d.google.com [IPv6:2a00:1450:4010:c07::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3B21221107850 for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:04 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22d; helo=mail-lf0-x22d.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jHyLU6pJ4bjvfqrgmpnKgGJ967IDyvah5WGbCpUPnkE=; b=Xb6zHy2v58e3YnrlFFhxiahQgite2y5uYyBaE03E1CJLXGt6q/PFhsBPnRXiL+k5Xo BnCqoIe35JYd6N6259WVuioukBLFOCJkkE2MVJZ+oRwSrWQQI4UFytGpd+E5a9MZ1vWd B3m7+dJ9/D4GgY+/y27L389Azw9B0t7DdL8qTJ8nqESiwrKwrIwNZpFYF9AS4z1aPMxp zvrwrERq63Y/yDM2FLWwvWVeLDrFDqFXKei+QfL+u+rFkmPECTmhraqVIdtiD6futmCZ PQR63ixf6gpsUGDsZwhxxVqbcx8AdkA7JDA3/1SVXdDNRJw4YtskHNDI/bIjbTke2NQc 1Zhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jHyLU6pJ4bjvfqrgmpnKgGJ967IDyvah5WGbCpUPnkE=; b=twDHquFD6nW3Ufz81lGbwFq+mGPQGK8AqJc+17FN2v/z1hiKTxfTcmGQs9V2Y3dpc1 Uu92IIC6zdpY87dQxu2g3kroW1t1blTx8diVc+DvTpqPOsch8xW2A1CYvBoCJdxfE9Wq uHdmpBC0sfCQS6nnNAtK0T/zw5C/0HistfRMeaHIxBF84jbNzCj6FlG5oQyRI7jMC2Zr Fh0okiupxESYDmT5A8zsdiBjvulr4HiQZ8Ipe276DlIHty8NT8d/aq1vjYZI9KWWvbOc CXSDKPv/nBKwdjmP8nSl3/B2vhCKTcW5OrW7N2R6aoMaW2b0QBBJ9GfpVL6LP78KNiWE s2dw== X-Gm-Message-State: APt69E3osW1lZJF7HgcI3dKiE2pIVQ6R4IXkdcMybDcP7tdA2+eBSpt4 YYKH1XDB2loOVTM2V3PqAdbkOYM/vmk= X-Google-Smtp-Source: ADUXVKIruuQ44Zk/6rjmVQoGpM1TTc024RRHIcYnlCt1fQ29s2DphdtO3pOr8EgJjyHq2e0RDlP/OA== X-Received: by 2002:a19:7:: with SMTP id 7-v6mr9039208lfa.62.1529362745147; Mon, 18 Jun 2018 15:59:05 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:24 +0200 Message-Id: <1529362724-9244-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 05/25] Marvell/Armada7k8k: Enable board description driver compilation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: jinghua This patch enables compilation of MvBoardDescDxe driver for Armada70x0-DB, Armada80x0-DB and Armada80x0McBin. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 2 ++ Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 1 + 2 files changed, 3 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 75fa3d4..a9d67a2 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -32,6 +32,7 @@ #SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # [LibraryClasses.common] + ArmadaSoCDescLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib= /Armada7k8kSoCDescLib.inf ArmPlatformLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k= 8kLib.inf ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf @@ -449,6 +450,7 @@ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf =20 # Platform Initialization + Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf =20 # Platform drivers diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf b/Silicon/Marvell/Ar= mada7k8k/Armada7k8k.fdf index 180b6c9..18d5d06 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf @@ -106,6 +106,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c # # Platform Initialization # + INF Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf INF Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf =20 # PI DXE Drivers producing Architectural Protocols (EFI Services) --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 15293627624707.800774666037455; Mon, 18 Jun 2018 15:59:22 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CB99E21109FFC; Mon, 18 Jun 2018 15:59:11 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8AEE221106A26 for ; Mon, 18 Jun 2018 15:59:08 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id u5-v6so5932204lff.13 for ; Mon, 18 Jun 2018 15:59:08 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:05 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TAtE7VEjUKzZp16sVpTG1jivhBdQ7OZzl6m6Mkwnpao=; b=FOUXma2bhflQgwn6qdR9GkjJZdUFgznFARQNuqFm/KKBzqnkp2TbzOcR19rFxinT8u Semc4FwN1BEp3j72vAZAYzIelI3l3OPdlW0Szwd/kQKCu8fPw8gwEBRPzidYR3dTQA8/ 0nVYu6Ve6qDvP61qYCan8PiZi2olCwDXOHc74d1w3ceTqt+3nwLhBfbKUtLnHsJD9Qpk gTzv477G3fU8ziFKnwvxLkghHLU2xc/C7P7nexj8X+eQqXAGXv4S9WrcvVtq7/mVGaI+ IvLdtFWYRS+mx8eXjSOZl954lKPepmZV4hCnDWiS5apOcBNRIhqJsQ5sSHQvmT72GfHq PpHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TAtE7VEjUKzZp16sVpTG1jivhBdQ7OZzl6m6Mkwnpao=; b=Sne1bTm69dyG7E7kM30ma+SJOcLhHB7HX4X2fNfPXxSksa84MjUNUPKTlAJK8ehYj8 NoU3WViFWjf5+d61VoFL6AdIaDkyhMf+edRsfAhiBlyR+WfAeV+jGm8JBwMvYhfi6had HmEeVQtOrbtmQbeq5xZKq0Z6sxUy6tXGUWVwes0WOgLkRP7QCeSeCH7N9dHIUx7snV30 e09uwQauCun24L87rMcdttqH7bNX6VeCeSKhmY+4tfyaaY8crdh7QKiono2J01jxIKvM YfpOqRPSGryWCYvZpaiXLq3W5nprhJxec8upPeqK82fo2mNshcUQS6pPdDAHWfwssHDl vZAg== X-Gm-Message-State: APt69E0ZleSGMnaylODyFE1wwuyswoB9cwVhGP6+SiJ8xhW8K5ysgSsu I6A248QWnHaaFvpRQPDUivp0B4PXMQ0= X-Google-Smtp-Source: ADUXVKLxjoEINAB2/MYzCxun+RkwHtmy7ABR5WH6msk140dZO1KYYEwBFx5Sz7Zzfg9zg3+CWXlBHQ== X-Received: by 2002:a19:9486:: with SMTP id o6-v6mr767181lfk.38.1529362746406; Mon, 18 Jun 2018 15:59:06 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:25 +0200 Message-Id: <1529362724-9244-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 06/25] Marvell/Library: UtmiPhyLib: Switch to use MARVELL_BOARD_DESC protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" UTMI driver used to get Armada7k8k UTMI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get UTMI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Use the protocol and pass information to further to the library init routine. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 - Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 9 ++- Silicon/Marvell/Include/Library/MvHwDescLib.h | 47 --= ------------ Silicon/Marvell/Include/Library/UtmiPhyLib.h | 2 + Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 5 ++ Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 65 ++= +++++------------- 6 files changed, 32 insertions(+), 97 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index d38b467..f2c173c 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -51,7 +51,6 @@ DebugLib MemoryAllocationLib MppLib - UtmiPhyLib =20 [Sources.common] Armada7k8kLib.c diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf b/Silicon/Ma= rvell/Library/UtmiPhyLib/UtmiPhyLib.inf index 0876879..e2381f4 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf @@ -51,11 +51,10 @@ IoLib MemoryAllocationLib PcdLib + UefiBootServicesTableLib + +[Protocols] + gMarvellBoardDescProtocolGuid ## CONSUMES =20 [Sources.common] UtmiPhyLib.c - -[Pcd] - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled - gMarvellTokenSpaceGuid.PcdUtmiPortType - gMarvellTokenSpaceGuid.PcdPciEXhci diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 9ae03d0..e13814a 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -127,19 +127,6 @@ typedef struct { } MVHW_RTC_DESC; =20 // -// UTMI PHY's description template definition -// - -typedef struct { - UINT8 UtmiDevCount; - UINT32 UtmiPhyId[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiBaseAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiConfigAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiUsbConfigAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN UtmiMuxBitCount[MVHW_MAX_XHCI_DEVS]; -} MVHW_UTMI_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -253,38 +240,4 @@ MVHW_RTC_DESC mA7k8kRtcDescTemplate =3D {\ { SIZE_4KB, SIZE_4KB }\ } =20 -// -// Platform description of UTMI PHY's -// -#define MVHW_CP0_UTMI0_BASE 0xF2580000 -#define MVHW_CP0_UTMI0_CFG_BASE 0xF2440440 -#define MVHW_CP0_UTMI0_USB_CFG_BASE 0xF2440420 -#define MVHW_CP0_UTMI0_ID 0x0 -#define MVHW_CP0_UTMI1_BASE 0xF2581000 -#define MVHW_CP0_UTMI1_CFG_BASE 0xF2440444 -#define MVHW_CP0_UTMI1_USB_CFG_BASE 0xF2440420 -#define MVHW_CP0_UTMI1_ID 0x1 -#define MVHW_CP1_UTMI0_BASE 0xF4580000 -#define MVHW_CP1_UTMI0_CFG_BASE 0xF4440440 -#define MVHW_CP1_UTMI0_USB_CFG_BASE 0xF4440420 -#define MVHW_CP1_UTMI0_ID 0x0 -#define MVHW_CP1_UTMI1_BASE 0xF4581000 -#define MVHW_CP1_UTMI1_CFG_BASE 0xF4440444 -#define MVHW_CP1_UTMI1_USB_CFG_BASE 0xF4440420 -#define MVHW_CP1_UTMI1_ID 0x1 - -#define DECLARE_A7K8K_UTMI_TEMPLATE \ -STATIC \ -MVHW_UTMI_DESC mA7k8kUtmiDescTemplate =3D {\ - 4,\ - { MVHW_CP0_UTMI0_ID, MVHW_CP0_UTMI1_ID,\ - MVHW_CP1_UTMI0_ID, MVHW_CP1_UTMI1_ID },\ - { MVHW_CP0_UTMI0_BASE, MVHW_CP0_UTMI1_BASE,\ - MVHW_CP1_UTMI0_BASE, MVHW_CP1_UTMI1_BASE },\ - { MVHW_CP0_UTMI0_CFG_BASE, MVHW_CP0_UTMI1_CFG_BASE,\ - MVHW_CP1_UTMI0_CFG_BASE, MVHW_CP1_UTMI1_CFG_BASE },\ - { MVHW_CP0_UTMI0_USB_CFG_BASE, MVHW_CP0_UTMI1_USB_CFG_BASE,\ - MVHW_CP1_UTMI0_USB_CFG_BASE, MVHW_CP1_UTMI1_USB_CFG_BASE }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Include/Library/UtmiPhyLib.h b/Silicon/Marvell= /Include/Library/UtmiPhyLib.h index 7c62cba..6f4e355 100644 --- a/Silicon/Marvell/Include/Library/UtmiPhyLib.h +++ b/Silicon/Marvell/Include/Library/UtmiPhyLib.h @@ -35,6 +35,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __UTMIPHYLIB_H__ #define __UTMIPHYLIB_H__ =20 +#include + EFI_STATUS UtmiPhyInit ( VOID diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/Marv= ell/Library/UtmiPhyLib/UtmiPhyLib.h index 0d7d72e..7e56f1a 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h @@ -35,6 +35,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __UTMIPHY_H__ #define __UTMIPHY_H__ =20 +#include + #include #include #include @@ -42,6 +44,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include + +#include =20 #define UTMI_USB_CFG_DEVICE_EN_OFFSET 0 #define UTMI_USB_CFG_DEVICE_EN_MASK (0x1 << UTMI_USB_CFG_DEV= ICE_EN_OFFSET) diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/Marv= ell/Library/UtmiPhyLib/UtmiPhyLib.c index 2cd9cfa..cef1279 100644 --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c @@ -33,9 +33,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. **************************************************************************= *****/ =20 #include "UtmiPhyLib.h" -#include - -DECLARE_A7K8K_UTMI_TEMPLATE; =20 typedef struct { EFI_PHYSICAL_ADDRESS UtmiBaseAddr; @@ -288,67 +285,47 @@ UtmiPhyInit ( VOID ) { + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_UTMI_DESC *BoardDesc; UTMI_PHY_DATA UtmiData; - UINT8 *UtmiDeviceTable, *XhciDeviceTable, *UtmiPortType, Index; - MVHW_UTMI_DESC *Desc =3D &mA7k8kUtmiDescTemplate; - - /* Obtain table with enabled Utmi PHY's*/ - UtmiDeviceTable =3D (UINT8 *)PcdGetPtr (PcdUtmiControllersEnabled); - if (UtmiDeviceTable =3D=3D NULL) { - /* No UTMI PHY on platform */ - return EFI_SUCCESS; - } - - if (PcdGetSize (PcdUtmiControllersEnabled) > MVHW_MAX_XHCI_DEVS) { - DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiControllersEnabled format\n")= ); - return EFI_INVALID_PARAMETER; - } + EFI_STATUS Status; + UINTN Index; =20 - /* Make sure XHCI controllers table is present */ - XhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEXhci); - if (XhciDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "UTMI: Missing PcdPciEXhci\n")); - return EFI_INVALID_PARAMETER; + /* Obtain board description */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - /* Obtain port type table */ - UtmiPortType =3D (UINT8 *)PcdGetPtr (PcdUtmiPortType); - if (UtmiPortType =3D=3D NULL || - PcdGetSize (PcdUtmiPortType) !=3D PcdGetSize (PcdUtmiControllersEnab= led)) { - DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiPortType format\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescUtmiGet (BoardDescProtocol, &Boar= dDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdUtmiControllersEnabled); Index+= +) { - if (!MVHW_DEV_ENABLED (Utmi, Index)) { - continue; - } - - /* UTMI PHY without enabled XHCI controller is useless */ - if (!MVHW_DEV_ENABLED (Xhci, Index)) { - DEBUG ((DEBUG_ERROR, "UTMI: Disabled Xhci controller %d\n", Index)); - return EFI_INVALID_PARAMETER; - } - + for (Index =3D 0; Index < BoardDesc->UtmiDevCount; Index++) { /* Get base address of UTMI phy */ - UtmiData.UtmiBaseAddr =3D Desc->UtmiBaseAddresses[Index]; + UtmiData.UtmiBaseAddr =3D BoardDesc[Index].SoC->UtmiBaseAddress; =20 /* Get usb config address */ - UtmiData.UsbCfgAddr =3D Desc->UtmiUsbConfigAddresses[Index]; + UtmiData.UsbCfgAddr =3D BoardDesc[Index].SoC->UsbConfigAddress; =20 /* Get UTMI config address */ - UtmiData.UtmiCfgAddr =3D Desc->UtmiConfigAddresses[Index]; + UtmiData.UtmiCfgAddr =3D BoardDesc[Index].SoC->UtmiConfigAddress; =20 /* Get UTMI PHY ID */ - UtmiData.PhyId =3D Desc->UtmiPhyId[Index]; + UtmiData.PhyId =3D BoardDesc[Index].SoC->UtmiPhyId; =20 /* Get the usb port type */ - UtmiData.UtmiPhyPort =3D UtmiPortType[Index]; + UtmiData.UtmiPhyPort =3D BoardDesc[Index].UtmiPortType; =20 /* Currently only Cp110 is supported */ Cp110UtmiPhyInit (&UtmiData); } =20 + BoardDescProtocol->BoardDescFree (BoardDesc); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:06 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::231; helo=mail-lf0-x231.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xnONXDCn3YY9eWDSQ1sDzbqHt9ZFBilN3//e9F1/318=; b=Tem+p5waJyPtJwHReptoQ0DBs15/qYemDmbL/DKEFGtVQeaD7RXcv7+n2Mk1aj/10w BjRM38scZO1Qx5trx1xkk0L99LwdSFTg4v5NnlIwQM3LEV39HmFWAonwNvfmN5F7GyCF WyFFgSdihX5hbrE8f53A3G6+W8U2bPy5GPkA1HUVVvTkhVG7bqaGJ3NBFHdzBvRnCZ3W xmyQJVGNuwuwljkihHcGL2Mo3C2oUfCO/sr+e+dWdE5i9BAWgL3prRmRGUjfLKRiZPGf +G4irR7dnMn2Lw/83gwORrl79GOTfuLkpZa8ad2IvEoorJWZDAwbx9DKNadDYCdysKPi 1wgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xnONXDCn3YY9eWDSQ1sDzbqHt9ZFBilN3//e9F1/318=; b=QX5WPdEXGsC49XoExHDxsD93Q1Edi/ZUdLvFMkvt1U5vncFWieatGwBN3IS08SKFM7 07lkMEeacrk6ga+5BdytmgSbC2kq5w1BNpu4WBrThlV9giLn7sdfT9Z2nw9mQn0pvmVW s2Wqm3f+dIUFDDMRKSLFerjYTVoKaCf6wzPHTsEKGpNjQNfqN8ZbcVpDe+k1X+JAaOf6 sX9O+ho+XJ00zkgwkMsTZ8OuC3i7tMkjSSt88Whn2wdQVVmR/yp/fKWM2RvLr7zMZtaq 97s+D2AzQjWZgm8QJX929gynbl5lM7mpe7fslNzddpkx6wK3Zmt/iJR8rnEkrrw5a4i4 9LLg== X-Gm-Message-State: APt69E1ITqmCaA4ck0zJvF7iHIFBnaK+5z6aUoo8V4HXKUyFTrqtLCJx 3NGc+baFcqMPCtHiXeB+8jYOZiceKJ0= X-Google-Smtp-Source: ADUXVKJj5nw0BTRrt9rxGo8IJNTQBqHsLbb++WQU49ZdcrrcAUOunKxe6o083smfEDoXJxYxQyPZdA== X-Received: by 2002:a19:8e4e:: with SMTP id q75-v6mr9031663lfd.95.1529362747578; Mon, 18 Jun 2018 15:59:07 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:26 +0200 Message-Id: <1529362724-9244-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 07/25] Marvell/Library: RealTimeClockLib: Simplify obtaining base address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hitherto mechanism of obtaining RTC base address proved to be not flexible enough to support more than one SoC family. Because there can be a single controller in use anyway, this patch drops utilization of MvHwDescLib header with hardcoded structure and replace it with simple UINT64 PCD. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Marvell.dec |= 2 +- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc |= 2 +- Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc |= 2 +- Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc |= 2 +- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.inf |= 2 +- Silicon/Marvell/Include/Library/MvHwDescLib.h |= 25 ----------------- Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c |= 29 ++++---------------- 7 files changed, 11 insertions(+), 53 deletions(-) diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 6861cc4..4def897 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -195,7 +195,7 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT64|0x40000052 =20 #TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.dsc index 68813f8..5ccee1b 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -134,4 +134,4 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x1 } + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000 diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marv= ell/Armada80x0Db/Armada80x0Db.dsc index 582e939..2425c45 100644 --- a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc +++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc @@ -155,4 +155,4 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platfo= rm/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc index 8230d67..1baed88 100644 --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc @@ -146,4 +146,4 @@ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 #RTC - gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } + gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000 diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.inf index 59c71c4..1ecd444 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.= inf @@ -49,7 +49,7 @@ gEfiEventVirtualAddressChangeGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdRtcEnabled + gMarvellTokenSpaceGuid.PcdRtcBaseAddress =20 [Depex.common.DXE_RUNTIME_DRIVER] gEfiCpuArchProtocolGuid diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index e13814a..34d03d4 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -116,17 +116,6 @@ typedef struct { } MVHW_PP2_DESC; =20 // -// RealTimeClock devices description template definition -// -#define MVHW_MAX_RTC_DEVS 2 - -typedef struct { - UINT8 RtcDevCount; - UINTN RtcBaseAddresses[MVHW_MAX_RTC_DEVS]; - UINTN RtcMemSize[MVHW_MAX_RTC_DEVS]; -} MVHW_RTC_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -226,18 +215,4 @@ MVHW_PP2_DESC mA7k8kPp2DescTemplate =3D {\ { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \ } =20 -// -// Platform description of RealTimeClock devices -// -#define MVHW_CP0_RTC0_BASE 0xF2284000 -#define MVHW_CP1_RTC0_BASE 0xF4284000 - -#define DECLARE_A7K8K_RTC_TEMPLATE \ -STATIC \ -MVHW_RTC_DESC mA7k8kRtcDescTemplate =3D {\ - 2,\ - { MVHW_CP0_RTC0_BASE, MVHW_CP1_RTC0_BASE },\ - { SIZE_4KB, SIZE_4KB }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCl= ockLib.c b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeCloc= kLib.c index d671b6a..087bd9a 100644 --- a/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/RealTimeClockLib/RealTimeClockLib.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -34,7 +33,6 @@ #include #include "RealTimeClockLib.h" =20 -DECLARE_A7K8K_RTC_TEMPLATE; STATIC EFI_EVENT mRtcVirtualAddrChangeEvent; STATIC UINTN mArmadaRtcBase; =20 @@ -216,28 +214,13 @@ LibRtcInitialize ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_RTC_DESC *Desc =3D &mA7k8kRtcDescTemplate; - UINT8 *RtcDeviceTable, Index; EFI_HANDLE Handle; EFI_STATUS Status; =20 - // Pick RTC device and initialize its data - RtcDeviceTable =3D (UINT8 *) PcdGetPtr (PcdRtcEnabled); - if (RtcDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "RTC: Missing PcdRtcEnabled\n")); - return EFI_INVALID_PARAMETER; - } - - // Initialize only first of enabled controllers - for (Index =3D 0; Index < PcdGetSize (PcdRtcEnabled); Index++) { - if (MVHW_DEV_ENABLED (Rtc, Index)) { - DEBUG ((DEBUG_ERROR, "RTC: Initialize controller %d\n", Index)); - mArmadaRtcBase =3D Desc->RtcBaseAddresses[Index]; - break; - } - } + // Obtain RTC device base address + mArmadaRtcBase =3D PcdGet64 (PcdRtcBaseAddress); =20 - // Check if any of the controllers can be initialized + // Check if the controller can be initialized if (mArmadaRtcBase =3D=3D 0) { DEBUG ((DEBUG_ERROR, "RTC: None of controllers enabled\n")); return EFI_INVALID_PARAMETER; @@ -247,7 +230,7 @@ LibRtcInitialize ( Status =3D gDS->AddMemorySpace ( EfiGcdMemoryTypeMemoryMappedIo, mArmadaRtcBase, - Desc->RtcMemSize[Index], + SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ); if (EFI_ERROR (Status)) { @@ -257,7 +240,7 @@ LibRtcInitialize ( =20 Status =3D gDS->SetMemorySpaceAttributes ( mArmadaRtcBase, - Desc->RtcMemSize[Index], + SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ); if (EFI_ERROR (Status)) { @@ -304,7 +287,7 @@ LibRtcInitialize ( ErrEvent: gBS->UninstallProtocolInterface (Handle, &gEfiRealTimeClockArchProtocolG= uid, NULL); ErrSetMem: - gDS->RemoveMemorySpace (mArmadaRtcBase, Desc->RtcMemSize[Index]); + gDS->RemoveMemorySpace (mArmadaRtcBase, SIZE_4KB); =20 return Status; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:08 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::235; helo=mail-lf0-x235.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kJ+wJNwuiJZkFfwIP3Pv4TpjuL+onc5GIUHeO/EbzNg=; b=N98PnSMZscawAvTzTv0I7hqFnHVlOHje8vKDhWkpMaVdOvWyMQWimtUTuWgYNFJvPw lDnvEbZHnPcy5myjnMvkbT6dXpaC6C1mhKriXFFLjTRTm1+wgNCb9oLV3EXUv8TBY9IJ 4krIxrHaP/UZg7u4V2sb6nPICVtfO3wSJmoNyrSSRSupwztHwga4BvYLU1KdyCP1XByc ZOpzU3VsXsoavu1k0T7rkU57Lqle/kgk9ddwtL5j21TbpFow/QxvUUM3xIBFzAAYzkJM aR+4dncttGjADHQ55zwD7874xPSbCHumWWMqYrwwmNNneEgBLEkos1v09geknoRy7uLR 4QgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kJ+wJNwuiJZkFfwIP3Pv4TpjuL+onc5GIUHeO/EbzNg=; b=mCXUPEq0/KT/bGAlJCZntdJmf1L+3uqacDOS4N7CC/hWQVSEL1gpwj3b7TE1nhPCUF 5NpulzxPUe+EAZIF5oK2ye1amsX6k6JX921xKP/CHTIuobfwlXOnosqsujJQ+RHohLeB XmdGa/7zTeUj5j9iyaFbcuMHL4SBVVQjFE03RadVqbjSIYjZ18gHrYaxW8XSOQgImpL2 9vtKRzPSy00h8uF8VxuBBlKdBy3Yk2ip+L6KpwtlapI8rPRn6dT1zpGwPSeceXCcEnZS 9pHsdlLuS6igzhgPF3f37R2/tYpBJLCYyFzHQ0vSkamhjDnzYNa15wytayJekuGO241V Rc1g== X-Gm-Message-State: APt69E04zrxHDnU+LMrLJ5dpM1QKbiziuNM+b0ZZXEnnGZingxtzz2+S l+GmY5H3ktmcWt+5QmjtngYOwVHRy6U= X-Google-Smtp-Source: ADUXVKLcBGldufMRl8tlAAGeAIPxI1gxHSrX42f0Il28BddcWBBplmr4zNT0WP8FZSMra2/sPmEOsg== X-Received: by 2002:a19:e544:: with SMTP id c65-v6mr8905359lfh.134.1529362748912; Mon, 18 Jun 2018 15:59:08 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:27 +0200 Message-Id: <1529362724-9244-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 08/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with PP2 information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescPp2Get ()), which dynamically allocates and fills MV_SOC_PP2_DESC structure with the SoC description of PP2 NICs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 6 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 15 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 29 ++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index c5711b0..b899d29 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -24,6 +24,12 @@ #define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000)) =20 // +// Platform description of PP2 NIC +// +#define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) +#define MV_SOC_PP2_CLK_FREQ 333333333 + +// // Platform description of UTMI PHY's // #define MV_SOC_UTMI_PER_CP_COUNT 2 diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 0d45684..cafcc0f 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -15,6 +15,21 @@ #define __ARMADA_SOC_DESC_LIB_H__ =20 // +// PP2 NIC devices SoC description +// +typedef struct { + UINTN Pp2BaseAddress; + UINTN Pp2ClockFrequency; +} MV_SOC_PP2_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescPp2Get ( + IN OUT MV_SOC_PP2_DESC **Pp2Desc, + IN OUT UINTN *DescCount + ); + +// // UTMI PHY devices SoC description // typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 63fb224..61b4e30 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -30,6 +30,35 @@ =20 EFI_STATUS EFIAPI +ArmadaSoCDescPp2Get ( + IN OUT MV_SOC_PP2_DESC **Pp2Desc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_PP2_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_PP2_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].Pp2BaseAddress =3D MV_SOC_PP2_BASE (CpIndex); + Desc[CpIndex].Pp2ClockFrequency =3D MV_SOC_PP2_CLK_FREQ; + } + + *Pp2Desc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescUtmiGet ( IN OUT MV_SOC_UTMI_DESC **UtmiDesc, IN OUT UINTN *DescCount --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362772947893.7144719621967; Mon, 18 Jun 2018 15:59:32 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 61EDD21109FFA; Mon, 18 Jun 2018 15:59:14 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3C5B721109FF7 for ; Mon, 18 Jun 2018 15:59:12 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id g21-v6so27183401lfb.4 for ; Mon, 18 Jun 2018 15:59:12 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:09 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Mk8IXWd2/vVovp3hlSkFA97HoIgm+b4tN6ubhv0lUhQ=; b=RgMwHQ43CE3YtsMYgRZGtarvwzLhFJQuiN9mQZr0f9XS2FM6YwCjClxLuycyJGEgbi OuLmzUzf+xmsFlqIy+VVLG31dH+9liiIDKOWXyleWLXVYfZZGj9YHLwJt03Z7OVvb4B4 9tKceoCwvdXtfKSMD3Dm3adfJUNvc+2NsurxaBmjS5qXko6LUjlUEHBSasJTNx81mrJ0 CoP6iduBhZ6PKOjughPNEqRlPosgWK06IUSWkNJXbCzj6iIg6p894qMhcmdwF6gzZM82 eK54IzqRcFR1OQOwS3RqrgRkSdWOtG76X2Txi08zkWK8LIPFBRPESY7CX2iiGsWTqGV2 4j3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Mk8IXWd2/vVovp3hlSkFA97HoIgm+b4tN6ubhv0lUhQ=; b=hlBSHim+n7stWEuoqCtD0i7DiLJxe5KpHHoNAyY5TaaIiCgJUwZL1+WAnlk2WaHhCp yq8O5l/ZmLexqWs+4BJWmFotjaDi7i51gaMXl5BX9p66AIYBTZgU/mATWdwmjOdOnb9X YuSP1Kl9JmVnnoSr9H30CE2wUqlvMisNEI1/bROxa814lAXLYQu4A41anMW20ovrY4iH 61Xsg01W/ta6/m+xgwLKXerzLzWXw2fakBPM8gw+At8VOol2EGzmT1Afw1d1QRE3hWTu 45IS5Yjf7cLvJZaKiU+hFu1C3U3ltgi9Our5A3W4Kw33lJOF7VixQXSda6oAmIlYkFzZ dxtg== X-Gm-Message-State: APt69E3eyRVWLG4L5Gc+0V3dUxnjVkBhyheQSrXkP65dcRa9M6QNOaOO LqVw3dd6CKkN9PGPAeYAQ6PKGaoXzAw= X-Google-Smtp-Source: ADUXVKKsiPQkCuIf4npbbZFiUA196DPpec//AGS3cCk4/31cula4dI+vXofynfOX8T1osBy3u4XMdQ== X-Received: by 2002:a2e:18b:: with SMTP id f11-v6mr9308476lji.83.1529362750270; Mon, 18 Jun 2018 15:59:10 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:28 +0200 Message-Id: <1529362724-9244-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 09/25] Marvell/Drivers: MvBoardDesc: Extend protocol with PP2 support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about PP2 NICs to the Pp2Dxe driver. Extend ArmadaBoardDescLib with new structure MV_BOARD_PP2_DESC, for holding board specific data. In further steps it should be extended and replace PCD port's representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 8 +++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 63 ++++++++++++++++= ++++ 4 files changed, 80 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index 5da5f21..6f57f06 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -58,6 +58,7 @@ =20 [Pcd] gMarvellTokenSpaceGuid.PcdPciEXhci + gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled gMarvellTokenSpaceGuid.PcdUtmiPortType =20 diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 068535a..ab94877 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,14 @@ #include =20 // +// PP2 NIC devices per-board description +// +typedef struct { + MV_SOC_PP2_DESC *SoC; + UINT8 Pp2DevCount; +} MV_BOARD_PP2_DESC; + +// // UTMI PHY devices per-board description // typedef struct { diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index f8a2902..114a0ec 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,13 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_PP2_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PP2_DESC **Pp2Desc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_UTMI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_UTMI_DESC **UtmiDesc @@ -55,6 +62,7 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; MV_BOARD_DESC_FREE BoardDescFree; }; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 0232a21..7c0bc39 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,68 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescPp2Get ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_PP2_DESC **Pp2Desc + ) +{ + UINT8 *Pp2DeviceEnabled; + UINTN Pp2Count, Pp2DeviceTableSize, Pp2Index, Index; + MV_BOARD_PP2_DESC *BoardDesc; + MV_SOC_PP2_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available PP2 controllers */ + Status =3D ArmadaSoCDescPp2Get (&SoCDesc, &Pp2Count); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled Pp2 controllers, + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + Pp2DeviceEnabled =3D PcdGetPtr (PcdPp2Controllers); + if (Pp2DeviceEnabled =3D=3D NULL) { + /* No PP2 NIC on platform */ + return EFI_SUCCESS; + } + + Pp2DeviceTableSize =3D PcdGetSize (PcdPp2Controllers); + + /* Check if PCD with PP2 NICs is correctly defined */ + if (Pp2DeviceTableSize > Pp2Count) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPp2Controllers format\n", __FUNCTIO= N__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (Pp2DeviceTableSize * sizeof (MV_BOARD_PP= 2_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + Pp2Index =3D 0; + for (Index =3D 0; Index < Pp2DeviceTableSize; Index++) { + if (!Pp2DeviceEnabled[Index]) { + continue; + } + + BoardDesc[Pp2Index].SoC =3D &SoCDesc[Index]; + Pp2Index++; + } + + BoardDesc->Pp2DevCount =3D Pp2Index; + + *Pp2Desc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescUtmiGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_UTMI_DESC **UtmiDesc @@ -140,6 +202,7 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:10 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ag6qi/ZHHx6IR7akOXVNm/PIl53moxExvDj7wQ3kj9s=; b=N/yDATYtbXab3u4WBFaFuIqJwq3/TZxsD3BD+6zm+5bQ7MElPinZmxxOcTiFd/YW52 d49IG8uyaGeeNvrfHtn5DDxVbi2jFgcpMAvIbUpGxJqiBasY95hi+okTT/IDqPY133Dz FRpqlibXWru/N4bs3Ns0pD8u2n+MVb14n7jPDf71R/XemTtABSuXC+5iJ10L2aJBH5ha w7Z2ny/bU6As/DXUHTomiV8I2de4XL6UWHy9u2EUpvayj0McBPB9xTKRLa2Bo9G0OHeu FKCyBzGi0L7XlWwFnzfCF51PXEsMEBtdH122ARjC1I4luHLjZPJYqnuTE9XYmsr1RykV PRYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ag6qi/ZHHx6IR7akOXVNm/PIl53moxExvDj7wQ3kj9s=; b=s22xuD/36JsZY2o2HmdE+mHfC5CEoB7bpjjz5e7/j4VF73kyJJxT/OYmzLPOzfmsXt 7NNnKNkLcI8TbRWTJl5AfpCCH72nQ2qGh2vEYgVn6fsF74/AObBquAwkZNAz27C7Fee9 DVi0oMWk8HWUGANq2LJ47XXR92WQVUXjo2z1usTrTzxPZ1nitt29pH9s7LcMk2hW/iSy GeqeBm4Hqe2jxZ5BiJUhCraTfsrKwzCsB5Tl1A7qWfZTqZ5+7nvOYLNDdnskhN2/SYQw 9KhK+x9x1hqEc938RnqWV6scy3eMthrilT5qmSHMuNr4FUmhjs37/0lI/QvxVcjPMvQr DjAg== X-Gm-Message-State: APt69E2Tb4DxQsoAv6y8/qP/9O7B2BMG36G5BOyMbBTwYpu0VubyDDkc DRYK0q1MyK4k/fTNZL+LMfz2PhScEB0= X-Google-Smtp-Source: ADUXVKIM4/oG7cxxhAN8LLuRVIK/U6rfOHBNpPmZIjFxOmk+fjWtw0+R8Tlsua6b99ccdynQcMDZKg== X-Received: by 2002:a2e:330b:: with SMTP id d11-v6mr9135508ljc.67.1529362751419; Mon, 18 Jun 2018 15:59:11 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:29 +0200 Message-Id: <1529362724-9244-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 10/25] Marvell/Drivers: Pp2Dxe: Switch to use MARVELL_BOARD_DESC protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Pp2Dxe driver used to get Armada7k8k PP2 controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get PP2 controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 2 +- Silicon/Marvell/Include/Library/MvHwDescLib.h | 26 ------------ Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 43 ++++++++------------ 3 files changed, 19 insertions(+), 52 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Silicon/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index fcd0611..be536ab 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -67,11 +67,11 @@ gEfiSimpleNetworkProtocolGuid gEfiDevicePathProtocolGuid gEfiCpuArchProtocolGuid + gMarvellBoardDescProtocolGuid gMarvellMdioProtocolGuid gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 34d03d4..5fd514c 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -105,17 +105,6 @@ typedef struct { } MVHW_NONDISCOVERABLE_DESC; =20 // -// PP2 NIC devices description template definition -// -#define MVHW_MAX_PP2_DEVS 4 - -typedef struct { - UINT8 Pp2DevCount; - UINTN Pp2BaseAddresses[MVHW_MAX_PP2_DEVS]; - UINTN Pp2ClockFrequency[MVHW_MAX_PP2_DEVS]; -} MVHW_PP2_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -200,19 +189,4 @@ MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTem= plate =3D {\ { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent }\ } =20 -// -// Platform description of Pp2 NIC devices -// -#define MVHW_CP0_PP2_BASE 0xF2000000 -#define MVHW_CP1_PP2_BASE 0xF4000000 -#define MVHW_PP2_CLK_FREQ 333333333 - -#define DECLARE_A7K8K_PP2_TEMPLATE \ -STATIC \ -MVHW_PP2_DESC mA7k8kPp2DescTemplate =3D {\ - 2,\ - { MVHW_CP0_PP2_BASE, MVHW_CP1_PP2_BASE },\ - { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Silicon/Marvell/= Drivers/Net/Pp2Dxe/Pp2Dxe.c index 3ed10f6..02b2798 100644 --- a/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Silicon/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include #include @@ -42,7 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include #include #include #include @@ -54,8 +54,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #define ReturnUnlock(tpl, status) do { gBS->RestoreTPL (tpl); return (stat= us); } while(0) =20 -DECLARE_A7K8K_PP2_TEMPLATE; - STATIC PP2_DEVICE_PATH Pp2DevicePathTemplate =3D { { { @@ -1343,35 +1341,28 @@ Pp2DxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_PP2_DESC *Desc =3D &mA7k8kPp2DescTemplate; - UINT8 *Pp2DeviceTable, Index; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_PP2_DESC *Pp2BoardDesc; MVPP2_SHARED *Mvpp2Shared; EFI_STATUS Status; + UINTN Index; =20 /* Obtain table with enabled Pp2 devices */ - Pp2DeviceTable =3D (UINT8 *)PcdGetPtr (PcdPp2Controllers); - if (Pp2DeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdPp2Controllers\n")); - return EFI_INVALID_PARAMETER; - } - - if (PcdGetSize (PcdPp2Controllers) > MVHW_MAX_PP2_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdPp2Controllers format\n")); - return EFI_INVALID_PARAMETER; + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - /* Check amount of declared ports */ - if (PcdGetSize (PcdPp2Port2Controller) > Desc->Pp2DevCount * MVPP2_MAX_P= ORT) { - DEBUG ((DEBUG_ERROR, "Pp2Dxe: Wrong too many ports declared\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescPp2Get (BoardDescProtocol, + &Pp2BoardDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdPp2Controllers); Index++) { - if (!MVHW_DEV_ENABLED (Pp2, Index)) { - DEBUG ((DEBUG_ERROR, "Skip Pp2 controller %d\n", Index)); - continue; - } + for (Index =3D 0; Index < Pp2BoardDesc->Pp2DevCount; Index++) { =20 /* Initialize private data */ Mvpp2Shared =3D AllocateZeroPool (sizeof (MVPP2_SHARED)); @@ -1383,8 +1374,8 @@ Pp2DxeInitialise ( Status =3D Pp2DxeInitialiseController ( Index, Mvpp2Shared, - Desc->Pp2BaseAddresses[Index], - Desc->Pp2ClockFrequency[Index] + Pp2BoardDesc[Index].SoC->Pp2BaseAddress, + Pp2BoardDesc[Index].SoC->Pp2ClockFrequency ); if (EFI_ERROR(Status)) { FreePool (Mvpp2Shared); @@ -1393,5 +1384,7 @@ Pp2DxeInitialise ( } } =20 + BoardDescProtocol->BoardDescFree (Pp2BoardDesc); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=txk09sTQqre3aTdKy7V2FLnLT1pZhZIKmidgp+MAtio=; b=XNTliJbjnQaPcHGRkw8/vIHWnIRTNHTv0GiuUcexOKMMR8gs8af695mIQXt1Y8yr/+ jI3D/+EIJaq35Uwj/FTx3r4HsWjVMFgSfgh9rou3STM/mstgnyDuKTzHvfhKbIEUGvPG bcFbtjqQwttLAyQiMzT3abQnxLnvEqMjV06eVorvIbpbdmBzA/iagajtJlQvJuIBd5lR KKaaGk8pXk4FVDaz42C4geoxrvzLPBJ8MQrqevl0OKK9lZ312VMr5QAE4sWHD+v7SWWL GbMoeCr4mBxGTHFAgTnuSP+3JuL8z0wRV/38KDeUV1SrzAsk74tgMtkCgGN7dpSBZTnq ww9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=txk09sTQqre3aTdKy7V2FLnLT1pZhZIKmidgp+MAtio=; b=Hbq5YlZDX4oapVsfuwY+OGNz0WBo8atMEpkD5vHX5CILRG+77I0qVpKkytuEgfGyCW 8hGMzimqkvIrSMRzyiy1pwh/NFnBdqt0MvfaAl8G/7OMnfUrpgxHXntPPRoztFwTQCZO lq9/Du/o60Uso5ug3/wNc/Utw0qvisTglyqGISf3JpBcw+16lqUJfMHLdDzrG/Tt5KEz CuUZLpUnd0fyMjW2CDMr9JBG3htAjk8iiiSECD9RJRe5Vpnys+xumNO8nuK5fuk+hzHl 7gGl0UvHpMHudKHHpmD+3o1BEPhP+Sz1g6qSDrKSmAFuAFOqXeubkYKubal+LP0JPfP3 6fAA== X-Gm-Message-State: APt69E0PvFAbK5vpfZubOT1KjAl8XFv3WJn86nEPsyzPHl4/DaWoH6fC JkIs8G/ZMHp2jY9GujJGYa7xK2kVQ+I= X-Google-Smtp-Source: ADUXVKKDTc720DpAJl+02caa+AOMvFbVgpo0nM37mGrLdfs01nqghqXuVe9w/c3cHKxXlrOkfyUruA== X-Received: by 2002:a2e:428e:: with SMTP id h14-v6mr9850719ljf.136.1529362752844; Mon, 18 Jun 2018 15:59:12 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:30 +0200 Message-Id: <1529362724-9244-12-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 11/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callbacks for NonDiscoverable devices i.e. AHCI/XHCI/SDMMC. They dynamically allocate and fill according structures with the SoC description of the devices. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 18 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 48 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 92 ++++++++++++++++++++ 3 files changed, 158 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index b899d29..d7557e8 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -24,12 +24,24 @@ #define MV_SOC_CP_BASE(Cp) (0xF2000000 + ((Cp) * 0x2000000)) =20 // +// Platform description of AHCI controllers +// +#define MV_SOC_AHCI_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x540000) +#define MV_SOC_AHCI_ID(Cp) ((Cp) % 2) + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) #define MV_SOC_PP2_CLK_FREQ 333333333 =20 // +// Platform description of SDMMC controllers +// +#define MV_SOC_MAX_SDMMC_COUNT 2 +#define MV_SOC_SDMMC_BASE(Index) ((Index) =3D=3D 0 ? 0xF06E0000 : = 0xF2780000) + +// // Platform description of UTMI PHY's // #define MV_SOC_UTMI_PER_CP_COUNT 2 @@ -38,4 +50,10 @@ #define MV_SOC_UTMI_CFG_BASE 0x440440 #define MV_SOC_UTMI_USB_CFG_BASE 0x440420 =20 +// +// Platform description of XHCI controllers +// +#define MV_SOC_XHCI_PER_CP_COUNT 2 +#define MV_SOC_XHCI_BASE(Xhci) (0x500000 + ((Xhci) * 0x10000)) + #endif diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index cafcc0f..3b29d78 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -14,6 +14,54 @@ #ifndef __ARMADA_SOC_DESC_LIB_H__ #define __ARMADA_SOC_DESC_LIB_H__ =20 +#include + +// +// NonDiscoverable devices SoC description +// +// AHCI +typedef struct { + UINTN AhciId; + UINTN AhciBaseAddress; + UINTN AhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType; +} MV_SOC_AHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINTN *DescCount + ); + +// SDMMC +typedef struct { + UINTN SdMmcBaseAddress; + UINTN SdMmcMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE SdMmcDmaType; +} MV_SOC_SDMMC_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINTN *DescCount + ); + +// XHCI +typedef struct { + UINTN XhciBaseAddress; + UINTN XhciMemSize; + NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType; +} MV_SOC_XHCI_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINTN *DescCount + ); + // // PP2 NIC devices SoC description // diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 61b4e30..97fe3f8 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -30,6 +30,37 @@ =20 EFI_STATUS EFIAPI +ArmadaSoCDescAhciGet ( + IN OUT MV_SOC_AHCI_DESC **AhciDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_AHCI_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_AHCI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].AhciId =3D MV_SOC_AHCI_ID (CpIndex); + Desc[CpIndex].AhciBaseAddress =3D MV_SOC_AHCI_BASE (CpIndex); + Desc[CpIndex].AhciMemSize =3D SIZE_8KB; + Desc[CpIndex].AhciDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + } + + *AhciDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescPp2Get ( IN OUT MV_SOC_PP2_DESC **Pp2Desc, IN OUT UINTN *DescCount @@ -59,6 +90,34 @@ ArmadaSoCDescPp2Get ( =20 EFI_STATUS EFIAPI +ArmadaSoCDescSdMmcGet ( + IN OUT MV_SOC_SDMMC_DESC **SdMmcDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_SDMMC_DESC *Desc; + UINTN Index; + + Desc =3D AllocateZeroPool (MV_SOC_MAX_SDMMC_COUNT * sizeof (MV_SOC_SDMMC= _DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < MV_SOC_MAX_SDMMC_COUNT; Index++) { + Desc[Index].SdMmcBaseAddress =3D MV_SOC_SDMMC_BASE (Index); + Desc[Index].SdMmcMemSize =3D SIZE_1KB; + Desc[Index].SdMmcDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + } + + *SdMmcDesc =3D Desc; + *DescCount =3D MV_SOC_MAX_SDMMC_COUNT; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescUtmiGet ( IN OUT MV_SOC_UTMI_DESC **UtmiDesc, IN OUT UINTN *DescCount @@ -92,3 +151,36 @@ ArmadaSoCDescUtmiGet ( =20 return EFI_SUCCESS; } + +EFI_STATUS +EFIAPI +ArmadaSoCDescXhciGet ( + IN OUT MV_SOC_XHCI_DESC **XhciDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_XHCI_DESC *Desc; + UINTN CpCount, CpIndex, Index; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *DescCount =3D CpCount * MV_SOC_XHCI_PER_CP_COUNT; + Desc =3D AllocateZeroPool (*DescCount * sizeof (MV_SOC_XHCI_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *XhciDesc =3D Desc; + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_XHCI_PER_CP_COUNT; Index++) { + Desc->XhciBaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_XHCI_BAS= E (Index); + Desc->XhciMemSize =3D SIZE_16KB; + Desc->XhciDmaType =3D NonDiscoverableDeviceDmaTypeCoherent; + Desc++; + } + } + + return EFI_SUCCESS; +} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362784664151.241894991638; Mon, 18 Jun 2018 15:59:44 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DD9132110A015; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:13 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=frBe4ltSWg4Ji1gQ3Hmjo6wpdKkByon+Yq4y5bLWUpY=; b=t+r2Kaxl9lRG/xk23CBWzM2gwuFUYHc7PZRqztJ9hS5laFLcDoqGRbJ1HL+sFfqANy x0LB9JBHLMJy9WsskU2CGgWC92YoDWeetEp80uy2TQJo9NV+ZEyhSMgCIY52chKe6HPN arJMjRf5Eo34vu/5CsLwl+4DOrDl9djz8HkaIKkx3clqS7hPCJSOdua0TW9E+7UWP0BK PEEWs+v1hR/mjDQOLGcT7EHjmQlAKYx0MhWGTSDIXPBfq0EH/ZXyOu1ZCO0OHqJiAbNW 5FU6OitftpQZJClKDb9AaCKmAB/PIFfr04SnXR7NvCXnMXVxNjJPPaXujjMw70VFqp0f QJoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=frBe4ltSWg4Ji1gQ3Hmjo6wpdKkByon+Yq4y5bLWUpY=; b=hRCoDwBfLuJY/g/iAXeVxBKwSENHU8RUzFfwAqsyv77nqV3Q4mxsTZ6hbckCSVqGFx yLgqt25PQwWMjl7SKz2adCtWvaUZnV0CVdQy/7FiDKni7zoN7ZhbJGmZNkippoks70Df nyUtUEG4q2Wg/+Fyk1gmy0vbQMPOBpfjTvEht/KwDZgikX8Ts2Y6mfJ3FQ67TZjAAIdD ZEH03wZS0C0i48l7sip2tAGkZqDlyw8p5TpFwjIZrusxzF1e1Wk9tvgfH7USCA/Uif6L 8NFxqwAgrP2dDwH7K7ZCuiB4liRmGUWWNrV32GrUFx0UXCczTmY1tDZveP/0wk+cmm5Z fARg== X-Gm-Message-State: APt69E0vIxi6CgqHUucGl3x8sn0TeMmAV5jZnt6/p4LR6RkMcf1qye2K y2cUiCZNXyUXv3gbVFtSNvZYDE9Eqck= X-Google-Smtp-Source: ADUXVKKhtoMeFt2H1Nq+Cd/cLIHun3HaFumGLSRXfh9NCNuGEKlrNWMB0ZzU3zmhBavpG+HaLiN8kg== X-Received: by 2002:a2e:4dcc:: with SMTP id c73-v6mr9069639ljd.135.1529362754306; Mon, 18 Jun 2018 15:59:14 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:31 +0200 Message-Id: <1529362724-9244-13-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 12/25] Marvell/Drivers: MvBoardDesc: Extend protocol with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about NonDiscoverableDevices to the relevant drivers and libraries. Extend ArmadaBoardDescLib with new structures (MV_BOARD_AHCI_DESC/ MV_BOARD_SDMMC_DESC/MV_BOARD_XHCI_DESC) for holding board specific data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 2 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 28 +++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 24 +++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 192 +++++++++++++++= +++++ 4 files changed, 246 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index 6f57f06..cc0d9d4 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -57,6 +57,8 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] + gMarvellTokenSpaceGuid.PcdPciEAhci + gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdPciEXhci gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index ab94877..7e4fa4d 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,34 @@ #include =20 // +// NonDiscoverableDevices per-board description +// + +// +// AHCI devices per-board description +// +typedef struct { + MV_SOC_AHCI_DESC *SoC; + UINTN AhciDevCount; +} MV_BOARD_AHCI_DESC; + +// +// SDMMC devices per-board description +// +typedef struct { + MV_SOC_SDMMC_DESC *SoC; + UINTN SdMmcDevCount; +} MV_BOARD_SDMMC_DESC; + +// +// XHCI devices per-board description +// +typedef struct { + MV_SOC_XHCI_DESC *SoC; + UINTN XhciDevCount; +} MV_BOARD_XHCI_DESC; + +// // PP2 NIC devices per-board description // typedef struct { diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 114a0ec..edf9491 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,27 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_AHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_SDMMC_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ); + +typedef +EFI_STATUS +(EFIAPI *MV_BOARD_DESC_XHCI_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_PP2_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -62,8 +83,11 @@ VOID ); =20 struct _MARVELL_BOARD_DESC_PROTOCOL { + MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; + MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; + MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; MV_BOARD_DESC_FREE BoardDescFree; }; =20 diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 7c0bc39..3439017 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,195 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescAhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_AHCI_DESC **AhciDesc + ) +{ + UINT8 *AhciDeviceEnabled; + UINTN AhciCount, AhciDeviceTableSize, AhciIndex, Index; + MV_BOARD_AHCI_DESC *BoardDesc; + MV_SOC_AHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available AHCI controllers */ + Status =3D ArmadaSoCDescAhciGet (&SoCDesc, &AhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled AHCI controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + AhciDeviceEnabled =3D PcdGetPtr (PcdPciEAhci); + if (AhciDeviceEnabled =3D=3D NULL) { + /* No AHCI on the platform */ + return EFI_SUCCESS; + } + + AhciDeviceTableSize =3D PcdGetSize (PcdPciEAhci); + + /* Check if PCD with AHCI controllers is correctly defined */ + if (AhciDeviceTableSize > AhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEAhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (AhciDeviceTableSize * sizeof (MV_BOARD_A= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + AhciIndex =3D 0; + for (Index =3D 0; Index < AhciDeviceTableSize; Index++) { + if (!AhciDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip Ahci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[AhciIndex].SoC =3D &SoCDesc[Index]; + AhciIndex++; + } + + BoardDesc->AhciDevCount =3D AhciIndex; + + *AhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescSdMmcGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc + ) +{ + UINT8 *SdMmcDeviceEnabled; + UINTN SdMmcCount, SdMmcDeviceTableSize, SdMmcIndex, Index; + MV_BOARD_SDMMC_DESC *BoardDesc; + MV_SOC_SDMMC_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available SDMMC controllers */ + Status =3D ArmadaSoCDescSdMmcGet (&SoCDesc, &SdMmcCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled SDMMC controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + SdMmcDeviceEnabled =3D PcdGetPtr (PcdPciESdhci); + if (SdMmcDeviceEnabled =3D=3D NULL) { + /* No SDMMC on platform */ + return EFI_SUCCESS; + } + + SdMmcDeviceTableSize =3D PcdGetSize (PcdPciESdhci); + + /* Check if PCD with SDMMC controllers is correctly defined */ + if (SdMmcDeviceTableSize > SdMmcCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciESdhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (SdMmcDeviceTableSize * sizeof (MV_BOARD_= SDMMC_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + SdMmcIndex =3D 0; + for (Index =3D 0; Index < SdMmcDeviceTableSize; Index++) { + if (!SdMmcDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip SdMmc controller %d\n", __FUNCTION__, = Index)); + continue; + } + + BoardDesc[SdMmcIndex].SoC =3D &SoCDesc[Index]; + SdMmcIndex++; + } + + BoardDesc->SdMmcDevCount =3D SdMmcIndex; + + *SdMmcDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MvBoardDescXhciGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_XHCI_DESC **XhciDesc + ) +{ + UINT8 *XhciDeviceEnabled; + UINTN XhciCount, XhciDeviceTableSize, XhciIndex, Index; + MV_BOARD_XHCI_DESC *BoardDesc; + MV_SOC_XHCI_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available XHCI controllers */ + Status =3D ArmadaSoCDescXhciGet (&SoCDesc, &XhciCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled XHCI controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + XhciDeviceEnabled =3D PcdGetPtr (PcdPciEXhci); + if (XhciDeviceEnabled =3D=3D NULL) { + /* No XHCI on platform */ + return EFI_SUCCESS; + } + + XhciDeviceTableSize =3D PcdGetSize (PcdPciEXhci); + + /* Check if PCD with XHCI controllers is correctly defined */ + if (XhciDeviceTableSize > XhciCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEXhci format\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (XhciDeviceTableSize * sizeof (MV_BOARD_X= HCI_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + XhciIndex =3D 0; + for (Index =3D 0; Index < XhciDeviceTableSize; Index++) { + if (!XhciDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip Xhci controller %d\n", __FUNCTION__, I= ndex)); + continue; + } + + BoardDesc[XhciIndex].SoC =3D &SoCDesc[Index]; + XhciIndex++; + } + + BoardDesc->XhciDevCount =3D XhciIndex; + + *XhciDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescPp2Get ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_PP2_DESC **Pp2Desc @@ -202,8 +391,11 @@ MvBoardDescInitProtocol ( IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol ) { + BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; + BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; + BoardDescProtocol->BoardDescXhciGet =3D MvBoardDescXhciGet; BoardDescProtocol->BoardDescFree =3D MvBoardDescFree; =20 return EFI_SUCCESS; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362789037875.2730498611236; Mon, 18 Jun 2018 15:59:49 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 15E432110A00B; Mon, 18 Jun 2018 15:59:20 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9D5D72110A007 for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:14 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mAFIKR77tuImppjWlErMCGbVG50og6G9coRlg4ZJyWw=; b=QpUQVGwIxBLmIevQkMDjxygn0n/jJcq74/t6LTe6Vtdq/7uGWOSGundTMznKfnRmyR I4VyI31MuN/V3Z7q0fG92oEgzolAx0vdfXpAYvYqd7LZ5azqwjg8EpfAv8ISc9SrpyMM qBJPJvYkMKH02D1WQvfE4KCYgf9f1pND5PYQjHkXuVt/mT8HLUyVmPrwgBR12hh/eakf 5SIp1AedKlgCsanFBd8+uxY7kXFOUBUWEazSlvDO44I/Fnv8mZwRfkx6CCujy/ixjGvO pqU+l7U5xE1QTnva1x546e4XDaS6FI37N50T/Fr0z6UjVLhHbf+8i7jqE39tYSwunvQt LtOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mAFIKR77tuImppjWlErMCGbVG50og6G9coRlg4ZJyWw=; b=VCTtF4MzQTxJmJvWFORMkSMoyPSBwC6qazAADkPliHzZTWJUE4LNeGAYfvKRcBnVbI PcSRmBDHrzQFZlu45T0r5vrWC8DxmbIboUVXC8925HdBnrUtYT0BH/eHot77iHi9VGOR ZWCCVnbIBRtEkZ/iLDuaXR5PoYTlb4JLQfi7xw5paVPRjvbd4Fv364AGzOixaFwt098+ rtuQ93yYqc2357ibiJaMA6rySpuEyyC1mZi+xFFQLK0RtwQjixs4h1RmeFqgqN/kAXhI fJJunBzIRSsT5ctiP6SQTF3CEnuIynjlVtan4Qlg1vymec5BT+PmROnca2zyrNJrqHsI ReRw== X-Gm-Message-State: APt69E1ODugquJOIBvwUXxpCmskW76L0qHxddmNqkhvPg9rYkKUlskRA wzwFpja4+nOl9zwKl1C6R7IPLZL5/u0= X-Google-Smtp-Source: ADUXVKIu5TcR6U0HDPlf9d7B4NBzV0VdCgyf2nqa8fYfyTRYqX0kqREyf2Hg2iUn08Mn61XzA+SCYQ== X-Received: by 2002:a2e:20e8:: with SMTP id g101-v6mr9333842lji.100.1529362755527; Mon, 18 Jun 2018 15:59:15 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:32 +0200 Message-Id: <1529362724-9244-14-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 13/25] Marvell/Drivers: NonDiscoverable: Switch to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" NonDiscoverableDevices driver used to get Armada7k8k AHCI/SDMMC/XHCI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver to get AHCI/SDMMC/XHCI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf | 6 +- Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c | 100 ++= ++++++++---------- 2 files changed, 52 insertions(+), 54 deletions(-) diff --git a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.= inf b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf index b62b3fb..98e5b0c 100644 --- a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf +++ b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.inf @@ -52,10 +52,8 @@ NonDiscoverableDeviceRegistrationLib UefiDriverEntryPoint =20 -[Pcd] - gMarvellTokenSpaceGuid.PcdPciEAhci - gMarvellTokenSpaceGuid.PcdPciESdhci - gMarvellTokenSpaceGuid.PcdPciEXhci +[Protocols] + gMarvellBoardDescProtocolGuid =20 [Depex] TRUE diff --git a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.= c b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c index 6ff90a5..c5cf904 100644 --- a/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c +++ b/Silicon/Marvell/Drivers/NonDiscoverableDxe/NonDiscoverableDxe.c @@ -35,50 +35,33 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include =20 #include -#include #include #include =20 +#include #include =20 -DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; - -// -// Tables with used devices -// -STATIC UINT8 * CONST XhciDeviceTable =3D FixedPcdGetPtr (PcdPciEXhci); -STATIC UINT8 * CONST AhciDeviceTable =3D FixedPcdGetPtr (PcdPciEAhci); -STATIC UINT8 * CONST SdhciDeviceTable =3D FixedPcdGetPtr (PcdPciESdhci); - // // NonDiscoverable devices registration // STATIC EFI_STATUS NonDiscoverableInitXhci ( + IN MV_BOARD_XHCI_DESC *Desc ) { - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_STATUS Status; UINT8 i; =20 - if (PcdGetSize (PcdPciEXhci) < Desc->XhciDevCount) { - DEBUG((DEBUG_ERROR, "NonDiscoverable: Wrong PcdPciEXhci format\n")); - return EFI_INVALID_PARAMETER; - } - for (i =3D 0; i < Desc->XhciDevCount; i++) { - if (!MVHW_DEV_ENABLED (Xhci, i)) { - continue; - } - Status =3D RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeXhci, - Desc->XhciDmaType[i], + Desc[i].SoC->XhciDmaType, NULL, NULL, 1, - Desc->XhciBaseAddresses[i], Desc->XhciMemSize[i] + Desc[i].SoC->XhciBaseAddress, + Desc[i].SoC->XhciMemSize ); =20 if (EFI_ERROR(Status)) { @@ -93,29 +76,21 @@ NonDiscoverableInitXhci ( STATIC EFI_STATUS NonDiscoverableInitAhci ( + IN MV_BOARD_AHCI_DESC *Desc ) { - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_STATUS Status; UINT8 i; =20 - if (PcdGetSize (PcdPciEAhci) < Desc->AhciDevCount) { - DEBUG((DEBUG_ERROR, "NonDiscoverable: Wrong PcdPciEAhci format\n")); - return EFI_INVALID_PARAMETER; - } - for (i =3D 0; i < Desc->AhciDevCount; i++) { - if (!MVHW_DEV_ENABLED (Ahci, i)) { - continue; - } - Status =3D RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeAhci, - Desc->AhciDmaType[i], + Desc[i].SoC->AhciDmaType, NULL, NULL, 1, - Desc->AhciBaseAddresses[i], Desc->AhciMemSize[i] + Desc[i].SoC->AhciBaseAddress, + Desc[i].SoC->AhciMemSize ); =20 if (EFI_ERROR(Status)) { @@ -130,29 +105,21 @@ NonDiscoverableInitAhci ( STATIC EFI_STATUS NonDiscoverableInitSdhci ( + IN MV_BOARD_SDMMC_DESC *Desc ) { - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_STATUS Status; UINT8 i; =20 - if (PcdGetSize (PcdPciESdhci) < Desc->SdhciDevCount) { - DEBUG((DEBUG_ERROR, "NonDiscoverable: Wrong PcdPciESdhci format\n")); - return EFI_INVALID_PARAMETER; - } - - for (i =3D 0; i < Desc->SdhciDevCount; i++) { - if (!MVHW_DEV_ENABLED (Sdhci, i)) { - continue; - } - + for (i =3D 0; i < Desc->SdMmcDevCount; i++) { Status =3D RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeSdhci, - Desc->SdhciDmaType[i], + Desc[i].SoC->SdMmcDmaType, NULL, NULL, 1, - Desc->SdhciBaseAddresses[i], Desc->SdhciMemSize[i] + Desc[i].SoC->SdMmcBaseAddress, + Desc[i].SoC->SdMmcMemSize ); =20 if (EFI_ERROR(Status)) { @@ -174,22 +141,55 @@ NonDiscoverableEntryPoint ( IN EFI_SYSTEM_TABLE *SystemTable ) { + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_SDMMC_DESC *SdMmcBoardDesc; + MV_BOARD_AHCI_DESC *AhciBoardDesc; + MV_BOARD_XHCI_DESC *XhciBoardDesc; EFI_STATUS Status; =20 - Status =3D NonDiscoverableInitXhci(); + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Xhci */ + Status =3D BoardDescProtocol->BoardDescXhciGet (BoardDescProtocol, + &XhciBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D NonDiscoverableInitXhci (XhciBoardDesc); if (EFI_ERROR(Status)) { return Status; } + BoardDescProtocol->BoardDescFree (XhciBoardDesc); =20 - Status =3D NonDiscoverableInitAhci(); + /* Ahci */ + Status =3D BoardDescProtocol->BoardDescAhciGet (BoardDescProtocol, + &AhciBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D NonDiscoverableInitAhci (AhciBoardDesc); if (EFI_ERROR(Status)) { return Status; } + BoardDescProtocol->BoardDescFree (AhciBoardDesc); =20 - Status =3D NonDiscoverableInitSdhci(); + /* SdMmc */ + Status =3D BoardDescProtocol->BoardDescSdMmcGet (BoardDescProtocol, + &SdMmcBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D NonDiscoverableInitSdhci (SdMmcBoardDesc); if (EFI_ERROR(Status)) { return Status; } + BoardDescProtocol->BoardDescFree (SdMmcBoardDesc); =20 return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362793114505.6067297524012; Mon, 18 Jun 2018 15:59:53 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 40B4E2110A01B; Mon, 18 Jun 2018 15:59:21 -0700 (PDT) Received: from mail-lf0-x230.google.com (mail-lf0-x230.google.com [IPv6:2a00:1450:4010:c07::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C8C512110A006 for ; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:16 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::230; helo=mail-lf0-x230.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9waDkAfncan5sNJiJQ5i1nRrLRPjrMpHUWpJrudq6WM=; b=TQy+hXC2eyCLGy8EyeFcBEfkGl6n8tHW98+Ep4W/yEGg9xKrp5E9YvXDPxkYzJlvPR EbK5bzd0PosZFz2hvNNbpnpMpUwPwuNiUVPU60r9RmHrLJb62r5tDPBNbsYkD0jTKDJZ dcTaa+ELeCCUrGFpURtExbE7vVohdI/93e37ALKNgefW6hw85lGiTeYp6CHzoZHtEK/V Qz89ZwT/YjNE/9mQLySEXKvlLLvBPYh2Gez8MJ6d1ySXtx2QAuKitPfoD8m1AN9VnzZo whjVEeIprljjvvuUEraHiOgBsU4GZlW0qubkK7FI7SA20yheJIx+rZGL9T0lKnGbdcaE FzyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9waDkAfncan5sNJiJQ5i1nRrLRPjrMpHUWpJrudq6WM=; b=LorsuIillIzsrgzOAuzuoBfEw9WCZkzfbjy7idtndqvSow1v5ftBX3kDdax6gCLvmk Rj1gMsO3Rxgo/9WsrypMeynP0oBTN6xGUdEppLwnNodXHFOfN24y/gGo8wr/z7dspcCP Tzbd8xGlvez74NLKXViMvzZviwP30XohpomZyhzbuxaL7Nox5cy8Tbza5oyAAs6ZP4+y qBF7qgJsbD1nG1Osy6a2ZrmdYBD6XUU5p24iBWVqUPlxUWcE1VbpP2JQbX1dehQ328F+ 1cuKS2pj4+Rx2jVKQuJ4d0dXHo8I06lhbGOT+2QmlpcBkmL+oldunVcLLrmD7q5uaQ0Q EoHw== X-Gm-Message-State: APt69E3/XHS8kp4vpXJd0qAYhm5ossWW3A6l4E39NnM5u2fHp15bu4m6 k+uRat3UZmoiG83QIhMzxU6Sv0Ub4I4= X-Google-Smtp-Source: ADUXVKKsfFsSfoZqbiZOP17AcjCm/G1aFOvv00cMmtUGGOHyIPwUUQsrUZ3DAfipIPGll3pDjnaUSA== X-Received: by 2002:a2e:e1a:: with SMTP id 26-v6mr8968931ljo.107.1529362756798; Mon, 18 Jun 2018 15:59:16 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:33 +0200 Message-Id: <1529362724-9244-15-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 14/25] Marvell/Library: ComPhyLib: Get AHCI data with MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" ComPhy Library used to get Armada7k8k AHCI/SDMMC/XHCI controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the driver to get AHCI controller description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 - Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 6 +- Silicon/Marvell/Include/Library/MvHwDescLib.h | 60 --= ------------------ Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 4 ++ Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 50 ++= ++++++-------- 5 files changed, 35 insertions(+), 86 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib= .inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf index f2c173c..e888566 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf @@ -47,7 +47,6 @@ =20 [LibraryClasses] ArmLib - ComPhyLib DebugLib MemoryAllocationLib MppLib diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyLib.inf index ce0af54..f36c701 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -52,12 +52,16 @@ PcdLib SampleAtResetLib IoLib + UefiBootServicesTableLib =20 [Sources.common] ComPhyLib.c ComPhyCp110.c ComPhyMux.c =20 +[Protocols] + gMarvellBoardDescProtocolGuid ## CONSUMES + [FixedPcd] gMarvellTokenSpaceGuid.PcdComPhyDevices =20 @@ -80,5 +84,3 @@ gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags - - gMarvellTokenSpaceGuid.PcdPciEAhci diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 5fd514c..9f383f4 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -36,7 +36,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define __MVHWDESCLIB_H__ =20 #include -#include =20 // // Helper macros @@ -80,31 +79,6 @@ typedef struct { } MVHW_MDIO_DESC; =20 // -// NonDiscoverable devices description template definition -// -#define MVHW_MAX_XHCI_DEVS 4 -#define MVHW_MAX_AHCI_DEVS 4 -#define MVHW_MAX_SDHCI_DEVS 4 - -typedef struct { - // XHCI - UINT8 XhciDevCount; - UINTN XhciBaseAddresses[MVHW_MAX_XHCI_DEVS]; - UINTN XhciMemSize[MVHW_MAX_XHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType[MVHW_MAX_XHCI_DEVS]; - // AHCI - UINT8 AhciDevCount; - UINTN AhciBaseAddresses[MVHW_MAX_AHCI_DEVS]; - UINTN AhciMemSize[MVHW_MAX_AHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType[MVHW_MAX_AHCI_DEVS]; - // SDHCI - UINT8 SdhciDevCount; - UINTN SdhciBaseAddresses[MVHW_MAX_SDHCI_DEVS]; - UINTN SdhciMemSize[MVHW_MAX_SDHCI_DEVS]; - NON_DISCOVERABLE_DEVICE_DMA_TYPE SdhciDmaType[MVHW_MAX_SDHCI_DEVS]; -} MVHW_NONDISCOVERABLE_DESC; - -// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -155,38 +129,4 @@ MVHW_MDIO_DESC mA7k8kMdioDescTemplate =3D {\ { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ } =20 -// -// Platform description of NonDiscoverable devices -// -#define MVHW_CP0_XHCI0_BASE 0xF2500000 -#define MVHW_CP0_XHCI1_BASE 0xF2510000 -#define MVHW_CP1_XHCI0_BASE 0xF4500000 -#define MVHW_CP1_XHCI1_BASE 0xF4510000 - -#define MVHW_CP0_AHCI0_BASE 0xF2540000 -#define MVHW_CP0_AHCI0_ID 0 -#define MVHW_CP1_AHCI0_BASE 0xF4540000 -#define MVHW_CP1_AHCI0_ID 1 - -#define MVHW_AP0_SDHCI0_BASE 0xF06E0000 -#define MVHW_CP0_SDHCI0_BASE 0xF2780000 - -#define DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE \ -STATIC \ -MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTemplate =3D {\ - 4, /* XHCI */\ - { MVHW_CP0_XHCI0_BASE, MVHW_CP0_XHCI1_BASE, MVHW_CP1_XHCI0_BASE, MVHW_CP= 1_XHCI1_BASE },\ - { SIZE_16KB, SIZE_16KB, SIZE_16KB, SIZE_16KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent,\ - NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent },\ - 2, /* AHCI */\ - { MVHW_CP0_AHCI0_BASE, MVHW_CP1_AHCI0_BASE },\ - { SIZE_8KB, SIZE_8KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent },\ - 2, /* SDHCI */\ - { MVHW_AP0_SDHCI0_BASE, MVHW_CP0_SDHCI0_BASE },\ - { SIZE_1KB, SIZE_1KB },\ - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCohe= rent }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.h index c675d74..090116d 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __COMPHY_H__ #define __COMPHY_H__ =20 +#include #include #include #include @@ -43,6 +44,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include + +#include =20 #define MAX_LANE_OPTIONS 10 =20 diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyCp110.c index 09994ca..5e0ebf6 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -33,7 +33,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. **************************************************************************= *****/ =20 #include "ComPhyLib.h" -#include #include =20 #define SD_LANE_ADDR_WIDTH 0x1000 @@ -46,8 +45,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CP110_PCIE_REF_CLK_TYPE0 0 #define CP110_PCIE_REF_CLK_TYPE12 1 =20 -DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; - /* * For CP-110 we have 2 Selector registers "PHY Selectors" * and " PIPE Selectors". @@ -1138,36 +1135,23 @@ ComPhySataCheckPll ( STATIC UINTN ComPhySataPowerUp ( + IN UINTN ChipId, IN UINT32 Lane, IN EFI_PHYSICAL_ADDRESS HpipeBase, IN EFI_PHYSICAL_ADDRESS ComPhyBase, - IN UINT8 SataHostId + IN MV_BOARD_AHCI_DESC *Desc ) { EFI_STATUS Status; - UINT8 *SataDeviceTable; - MVHW_NONDISCOVERABLE_DESC *Desc =3D &mA7k8kNonDiscoverableDescTemplate; EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS SdIpAddr =3D SD_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); =20 - SataDeviceTable =3D (UINT8 *) PcdGetPtr (PcdPciEAhci); - - if (SataDeviceTable =3D=3D NULL || SataHostId >=3D PcdGetSize (PcdPciEAh= ci)) { - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is undefined\n", SataHo= stId)); - return EFI_INVALID_PARAMETER; - } - - if (!MVHW_DEV_ENABLED (Sata, SataHostId)) { - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is disabled\n", SataHos= tId)); - return EFI_INVALID_PARAMETER; - } - DEBUG ((DEBUG_INFO, "ComPhySata: Initialize SATA PHYs\n")); =20 DEBUG((DEBUG_INFO, "ComPhySataPowerUp: stage: MAC configuration - power = down ComPhy\n")); =20 - ComPhySataMacPowerDown (Desc->AhciBaseAddresses[SataHostId]); + ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPh= y\n")); =20 @@ -1183,7 +1167,7 @@ ComPhySataPowerUp ( =20 DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); =20 - ComPhySataPhyPowerUp (Desc->AhciBaseAddresses[SataHostId]); + ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); =20 @@ -1884,6 +1868,8 @@ ComPhyCp110Init ( EFI_STATUS Status; COMPHY_MAP *PtrComPhyMap, *SerdesMap; EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_AHCI_DESC *AhciBoardDesc; UINT32 ComPhyMaxCount, Lane; UINT32 PcieWidth =3D 0; UINT8 ChipId; @@ -1927,11 +1913,29 @@ ComPhyCp110Init ( break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: - Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP0_AHCI0_ID); - break; case COMPHY_TYPE_SATA2: case COMPHY_TYPE_SATA3: - Status =3D ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, M= VHW_CP1_AHCI0_ID); + /* Obtain AHCI board description */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D BoardDescProtocol->BoardDescAhciGet (BoardDescProtocol, + &AhciBoardDesc); + if (EFI_ERROR (Status)) { + break; + } + + Status =3D ComPhySataPowerUp (ChipId, + Lane, + HpipeBaseAddr, + ComPhyBaseAddr, + AhciBoardDesc); + + BoardDescProtocol->BoardDescFree (AhciBoardDesc); break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:17 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::230; helo=mail-lf0-x230.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CUHg1ZKvqcRXDKIvyzCFSy4czpkBt65he9b+UKceg1U=; b=Ru0BZzTqZ4riZhOshlelku8klgQv3ckVoqqgSF5WT+9Oj4WJ14j7MKFezu/RDW6Ryw wYRgavLXkl0FSFEMzBdzt1kSWaZQV0FZOP4l+jsizMsw9wahfTT+Zq3Y9bYJy4FySggW TSdQCZskeZabTcsJhgrrKJyUz2AuEBbMczIY+15RWTSpSU/5D7q7wGdQCwhvvwLoEvTO GqCwwyLGpFyZZ1mhXWldUozpM6js/tGgV57qnJzPZJ1F9kOLU8ZZGVtsTRrZGyOehe+6 lLxmTaGGl57BlA9I6UZQH+BDnE1FukmSI7/U1G0HgniLLWqzalF6OOmFtX7TP9duqAD6 P1gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CUHg1ZKvqcRXDKIvyzCFSy4czpkBt65he9b+UKceg1U=; b=PbptUvtZdwts0dKGgSaE+vC5bovTGU3//bXtZbhdHFxkB6VD+0AfY9MT5nbJ55FYaK XxVvsQ7T9Lj9yr1Rp0U0xpliGMOZH1vphTaPAW96qRESB6NbtKEoGTPu+iczJPDB3fTv D1E1r58YU7mnyuUgHATAq6967sKSZcCErspjGQGQs4eNAsXEYgrRmLeXh0MPclH9eaCJ HQoKyQa3uc03njzbwI7L6yVLI22GaT74kaZUykLPSXxh+X3gofVoza1wawxcLFMuYjPN 5ercwOkKpbQLNwOnZPICU1XSILp+cGB/gRTnJhEUlY2Tjj4/Wdgn3k6HRQ0OiqWRTsgI BoDg== X-Gm-Message-State: APt69E3TnMOt3xgwUqgZTElyuq9lcJDojlYgsHS71l5zmy1mU4pLIEvS HQemJRSiigh0yOZUYT27wTmFftqofp8= X-Google-Smtp-Source: ADUXVKKeRJpGNmUM+8s8pmPjD9LhUduXXhdtpQG74f9RrbnFMuQxENTq7F7jE67Zke23EgHHmBgs9w== X-Received: by 2002:a2e:90c5:: with SMTP id o5-v6mr9084391ljg.15.1529362758156; Mon, 18 Jun 2018 15:59:18 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:34 +0200 Message-Id: <1529362724-9244-16-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 15/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with ComPhy information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescComPhyGet ()), which dynamically allocates and fills MV_SOC_COMPHY_DESC structure with the SoC description of ComPhy SerDes controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 8 +++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 20 ++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 33 ++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index d7557e8..f254b1c 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -30,6 +30,14 @@ #define MV_SOC_AHCI_ID(Cp) ((Cp) % 2) =20 // +// Platform description of ComPhy controllers +// +#define MV_SOC_COMPHY_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x441000) +#define MV_SOC_HPIPE3_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x120000) +#define MV_SOC_COMPHY_LANE_COUNT 6 +#define MV_SOC_COMPHY_MUX_BITS 4 + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 3b29d78..a133d1c 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -14,9 +14,29 @@ #ifndef __ARMADA_SOC_DESC_LIB_H__ #define __ARMADA_SOC_DESC_LIB_H__ =20 +#include #include =20 // +// ComPhy SoC description +// +typedef struct { + UINTN ComPhyId; + UINTN ComPhyBaseAddress; + UINTN ComPhyHpipe3BaseAddress; + UINTN ComPhyLaneCount; + UINTN ComPhyMuxBitCount; + MV_COMPHY_CHIP_TYPE ComPhyChipType; +} MV_SOC_COMPHY_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescComPhyGet ( + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, + IN OUT UINTN *DescCount + ); + +// // NonDiscoverable devices SoC description // // AHCI diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 97fe3f8..580c0f4 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -30,6 +30,39 @@ =20 EFI_STATUS EFIAPI +ArmadaSoCDescComPhyGet ( + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_COMPHY_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_COMPHY_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].ComPhyBaseAddress =3D MV_SOC_COMPHY_BASE (CpIndex); + Desc[CpIndex].ComPhyHpipe3BaseAddress =3D MV_SOC_HPIPE3_BASE (CpIndex); + Desc[CpIndex].ComPhyLaneCount =3D MV_SOC_COMPHY_LANE_COUNT; + Desc[CpIndex].ComPhyMuxBitCount =3D MV_SOC_COMPHY_MUX_BITS; + Desc[CpIndex].ComPhyChipType =3D MvComPhyTypeCp110; + Desc[CpIndex].ComPhyId =3D CpIndex; + } + + *ComPhyDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescAhciGet ( IN OUT MV_SOC_AHCI_DESC **AhciDesc, IN OUT UINTN *DescCount --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362803141400.43196436394544; Mon, 18 Jun 2018 16:00:03 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 91EAA2110A3C7; Mon, 18 Jun 2018 15:59:25 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1B01B2110A3C0 for ; Mon, 18 Jun 2018 15:59:22 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id d24-v6so27166968lfa.8 for ; Mon, 18 Jun 2018 15:59:22 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:19 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Sv8tYwysohMggX7vTazSD/YDTWrvfkVLLUu544tOQiY=; b=vqeFtf+GYlZAjeqPeYCIr2ycQkyJVy2jVIZzrDVOUc/VV3ewoBTuFxdNV/2mI1GO9r gQPnib82pjaUkNYHCeSvPfK4Dn+9ajfcMFQDOcLoHNf0aTEYmWYwCi9sTHWWm8jPDAUi jjkOfYuUw7qUmrzzdbwFORE9bfLx8xTh3NilxdvYrqMN7mCXH0A+cmZFgaX4u+hROGwq 3S6d9YcBEzUvJQAIPqUh2MkDfNcOXaEntCZGlLBW88QitCaXV0ZL1G9RJSX7K8Ag0Lq0 p9M3TNt3bEIA/3DlJgbNTFPcm93lJB8F8hspFgXZkIHKrC0fRobu0Q0iHGBUIqhyiqFB jT1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Sv8tYwysohMggX7vTazSD/YDTWrvfkVLLUu544tOQiY=; b=paLKApQliN4VyMksNOyFGS1G9X5V929wCN9DbA7mU4twa/YhDRv/Th0tKv53eCHSXQ AkhEYilR40wLXGeQ11Yf1ZtbAArUFg6ctwSbcro0CBFLu4kMSKKwMWX3f0sUkOaHMS2N ONktJoJ1OvVbPZOz1CrAHTTVYP0XwgAlR14/pHxs4MrRY8tFh+RxXL/1xHtpMvjGxJM7 qdx9q9J/5C2H/AY4k+PgcGiaRt6AMq22CLXhtr6UolUVW5SjObvZwxeHtwnfaPAnPBfp lAYJr1zDHQxBkVAcSB0idfrSj3Hrjs8qUE2cwc6Gs/M6oEZYEsNwGRQT0NWl8Q6M6xUv q5xQ== X-Gm-Message-State: APt69E3RDvMOQM45goHkx+LKsOGJHCcJsqNS30T4DlPrv12R65HYWk3j E+mosm9TnuD4LuV/hQmdkNQYzEPLeiE= X-Google-Smtp-Source: ADUXVKLEaNKtV34tP18hklaIiTSfiRzP9D8pKuxptaelyw8YcVqB65hHilQmghttXbWpiIlDtpEd5w== X-Received: by 2002:a2e:9e57:: with SMTP id g23-v6mr8923659ljk.14.1529362760126; Mon, 18 Jun 2018 15:59:20 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:35 +0200 Message-Id: <1529362724-9244-17-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 16/25] Marvell/Drivers: MvBoardDesc: Extend protocol with ComPhy support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about ComPhy controllers to the ComPhyLib. Extend ArmadaBoardDescLib with new structure MV_BOARD_COMPHY_DESC, for holding board specific data. In further steps it can be extended and replace PCD SerDes lanes' representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 8 +++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 64 ++++++++++++++++= ++++ 4 files changed, 81 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index cc0d9d4..dea99fd 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -57,6 +57,7 @@ gMarvellBoardDescProtocolGuid =20 [Pcd] + gMarvellTokenSpaceGuid.PcdComPhyDevices gMarvellTokenSpaceGuid.PcdPciEAhci gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdPciEXhci diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 7e4fa4d..32bd915 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -17,6 +17,14 @@ #include =20 // +// COMPHY controllers per-board description +// +typedef struct { + MV_SOC_COMPHY_DESC *SoC; + UINTN ComPhyDevCount; +} MV_BOARD_COMPHY_DESC; + +// // NonDiscoverableDevices per-board description // =20 diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index edf9491..b6dac75 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -43,6 +43,13 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOAR= D_DESC_PROTOCOL; =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_COMPHY_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_COMPHY_DESC **ComPhyDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_AHCI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -84,6 +91,7 @@ VOID =20 struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; + MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 3439017..6bbe40b 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -37,6 +37,69 @@ MV_BOARD_DESC *mBoardDescInstance; =20 STATIC EFI_STATUS +MvBoardDescComPhyGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_COMPHY_DESC **ComPhyDesc + ) +{ + UINT8 *ComPhyDeviceEnabled; + UINTN ComPhyCount, ComPhyDeviceTableSize, ComPhyIndex, Index; + MV_BOARD_COMPHY_DESC *BoardDesc; + MV_SOC_COMPHY_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available ComPhy controllers */ + Status =3D ArmadaSoCDescComPhyGet (&SoCDesc, &ComPhyCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled ComPhy controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + ComPhyDeviceEnabled =3D PcdGetPtr (PcdComPhyDevices); + if (ComPhyDeviceEnabled =3D=3D NULL) { + /* No ComPhy controllers declared */ + return EFI_NOT_FOUND; + } + + ComPhyDeviceTableSize =3D PcdGetSize (PcdComPhyDevices); + + /* Check if PCD with ComPhy is correctly defined */ + if (ComPhyDeviceTableSize > ComPhyCount) { + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdComPhyDevices format\n", __FUNCTION= __)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (ComPhyDeviceTableSize * sizeof (MV_BOARD= _COMPHY_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + ComPhyIndex =3D 0; + for (Index =3D 0; Index < ComPhyDeviceTableSize; Index++) { + if (!ComPhyDeviceEnabled[Index]) { + DEBUG ((DEBUG_ERROR, "%a: Skip ComPhy controller %d\n", __FUNCTION__= , Index)); + continue; + } + + BoardDesc[ComPhyIndex].SoC =3D &SoCDesc[Index]; + ComPhyIndex++; + } + + BoardDesc->ComPhyDevCount =3D ComPhyIndex; + + *ComPhyDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescAhciGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -392,6 +455,7 @@ MvBoardDescInitProtocol ( ) { BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; + BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362807393517.7427763615655; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:20 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=n2mrJ6+BGHXg5ji+0PN4NX0Hphgi1QLADbLYQa8TN7M=; b=LU9JFWxcKnY/EdeAgXQXyditdFjRjeNCSNUCaR7nFXihUt305jiy94T/xfHB82RBR5 mzZ6bpUmUJ3sZxI1cZSNDS9M487zNv3ODtsAwZwNw17bw/Shv5dmPE9CkPdqndPJCLFz pQVckmdJ/LZA8eC1zCMkrEIrVQ4vRYOm+989W4BJdFqn/fXW4Plq+fAoUTOQJ5dFrUSL tiYhNAvEXmJp6iruB+OcMYVXPGyJzikNn7eNjxNfcryq1LINlJp/pJMQ09/scqeYYhoN Vu5IjgqrlFKI5cWrtH6n1JXbeB0WXOLZtBPe7nT/kcHvlnimaMf5npXMrsGxbpu1UJY4 jAxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=n2mrJ6+BGHXg5ji+0PN4NX0Hphgi1QLADbLYQa8TN7M=; b=exNLbsRcZrvHimF8CdXvM7YO4oob7UaxQSdJJed07eFM/tb3f2WGhmB5FgMncAMnXA L8tzUhSWD6pvUM3FfUKxAu+Qdu+0pDFoJb8sKgRYZ6mOJ4ItDZgDkojXa24JRM7DQhnq h1K7eaFhveGJdLkEI4zJafQykDUl2BW0nlDjD2vjZJfaYt8w8hehnJwsyDkjy6JVruUL JKTndT3DESVK1Gs5OlXWOyGFYb179rd0N6CXREkl8lTvLVdURU0MuvGMQNEtlbj1sqXX zGBDcoufyTrJBLFCXe3ZKDCA+8ffRUoIkyLGm/prJqThOvRCkP6vhw/gNst/18XjpRgB gt8Q== X-Gm-Message-State: APt69E19tvouBaL3sWSgkuVanOTTQ4zvtwImzlhY7G6qnxAAC49mVF6/ H1BWtUnJfxgPNGQh0+U5Yqsa/Sr8dSQ= X-Google-Smtp-Source: ADUXVKKqRZUGUG5VxgFEH97rocZSMVD+8ui6Hm+veAf8+kxwsMFbfRqILXTuZ1wBlZeeJhE/QdEGhg== X-Received: by 2002:a2e:9ac4:: with SMTP id p4-v6mr9309975ljj.60.1529362761402; Mon, 18 Jun 2018 15:59:21 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:36 +0200 Message-Id: <1529362724-9244-18-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 17/25] Marvell/Library: ComPhyLib: Switch library to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" MvComPhyLib library used to get Armada7k8k SerDes multiplexing controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this library. This patch updates the library, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Include/Library/MvHwDescLib.h | 39 ----------- Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 74 ++++++++++++-------- 2 files changed, 45 insertions(+), 68 deletions(-) diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 9f383f4..423ca17 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -35,8 +35,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MVHWDESCLIB_H__ #define __MVHWDESCLIB_H__ =20 -#include - // // Helper macros // @@ -45,20 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) =20 // -// CommonPhy devices description template definition -// -#define MVHW_MAX_COMPHY_DEVS 4 - -typedef struct { - UINT8 ComPhyDevCount; - UINTN ComPhyBaseAddresses[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyHpipe3BaseAddresses[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyLaneCount[MVHW_MAX_COMPHY_DEVS]; - UINTN ComPhyMuxBitCount[MVHW_MAX_COMPHY_DEVS]; - MV_COMPHY_CHIP_TYPE ComPhyChipType[MVHW_MAX_COMPHY_DEVS]; -} MVHW_COMPHY_DESC; - -// // I2C devices description template definition // #define MVHW_MAX_I2C_DEVS 4 @@ -79,29 +63,6 @@ typedef struct { } MVHW_MDIO_DESC; =20 // -// Platform description of CommonPhy devices -// -#define MVHW_CP0_COMPHY_BASE 0xF2441000 -#define MVHW_CP0_HPIPE3_BASE 0xF2120000 -#define MVHW_CP0_COMPHY_LANES 6 -#define MVHW_CP0_COMPHY_MUX_BITS 4 -#define MVHW_CP1_COMPHY_BASE 0xF4441000 -#define MVHW_CP1_HPIPE3_BASE 0xF4120000 -#define MVHW_CP1_COMPHY_LANES 6 -#define MVHW_CP1_COMPHY_MUX_BITS 4 - -#define DECLARE_A7K8K_COMPHY_TEMPLATE \ -STATIC \ -MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate =3D {\ - 2,\ - { MVHW_CP0_COMPHY_BASE, MVHW_CP1_COMPHY_BASE },\ - { MVHW_CP0_HPIPE3_BASE, MVHW_CP1_HPIPE3_BASE },\ - { MVHW_CP0_COMPHY_LANES, MVHW_CP1_COMPHY_LANES },\ - { MVHW_CP0_COMPHY_MUX_BITS, MVHW_CP1_COMPHY_MUX_BITS },\ - { MvComPhyTypeCp110, MvComPhyTypeCp110 }\ -} - -// // Platform description of I2C devices // #define MVHW_CP0_I2C0_BASE 0xF2701000 diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.c index b03bc35..2ef9af4 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -34,9 +34,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "ComPhyLib.h" #include -#include - -DECLARE_A7K8K_COMPHY_TEMPLATE; =20 CHAR16 * TypeStringTable [] =3D {L"unconnected", L"PCIE0", L"PCIE1", L"PCI= E2", L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3= ", @@ -182,22 +179,20 @@ VOID InitComPhyConfig ( IN OUT CHIP_COMPHY_CONFIG *ChipConfig, IN OUT PCD_LANE_MAP *LaneData, - IN UINT8 Id + IN MV_BOARD_COMPHY_DESC *Desc ) { - MVHW_COMPHY_DESC *Desc =3D &mA7k8kComPhyDescTemplate; - - ChipConfig->ChipType =3D Desc->ComPhyChipType[Id]; - ChipConfig->ComPhyBaseAddr =3D Desc->ComPhyBaseAddresses[Id]; - ChipConfig->Hpipe3BaseAddr =3D Desc->ComPhyHpipe3BaseAddresses[Id]; - ChipConfig->LanesCount =3D Desc->ComPhyLaneCount[Id]; - ChipConfig->MuxBitCount =3D Desc->ComPhyMuxBitCount[Id]; - ChipConfig->ChipId =3D Id; + ChipConfig->ChipType =3D Desc->SoC->ComPhyChipType; + ChipConfig->ComPhyBaseAddr =3D Desc->SoC->ComPhyBaseAddress; + ChipConfig->Hpipe3BaseAddr =3D Desc->SoC->ComPhyHpipe3BaseAddress; + ChipConfig->LanesCount =3D Desc->SoC->ComPhyLaneCount; + ChipConfig->MuxBitCount =3D Desc->SoC->ComPhyMuxBitCount; + ChipConfig->ChipId =3D Desc->SoC->ComPhyId; =20 /* * Below macro contains variable name concatenation (used to form PCD's = name). */ - switch (Id) { + switch (ChipConfig->ChipId) { case 0: GetComPhyPcd (LaneData, 0); break; @@ -219,32 +214,49 @@ MvComPhyInit ( ) { EFI_STATUS Status; - CHIP_COMPHY_CONFIG ChipConfig[MVHW_MAX_COMPHY_DEVS], *PtrChipCfg; - PCD_LANE_MAP LaneData[MVHW_MAX_COMPHY_DEVS]; + CHIP_COMPHY_CONFIG *ChipConfig, *PtrChipCfg; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_COMPHY_DESC *ComPhyBoardDesc; + PCD_LANE_MAP *LaneData; UINT32 Lane, MaxComphyCount; - UINT8 *ComPhyDeviceTable, Index; + UINTN Index; =20 /* Obtain table with enabled ComPhy devices */ - ComPhyDeviceTable =3D (UINT8 *)PcdGetPtr (PcdComPhyDevices); - if (ComPhyDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdComPhyDevices\n")); - return EFI_INVALID_PARAMETER; + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D BoardDescProtocol->BoardDescComPhyGet (BoardDescProtocol, + &ComPhyBoardDesc); + if (EFI_ERROR (Status)) { + return Status; } =20 - if (PcdGetSize (PcdComPhyDevices) > MVHW_MAX_COMPHY_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdComPhyDevices format\n")); - return EFI_INVALID_PARAMETER; + ChipConfig =3D AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * + sizeof (CHIP_COMPHY_CONFIG)); + if (ChipConfig =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + return EFI_OUT_OF_RESOURCES; + } + + LaneData =3D AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * + sizeof (PCD_LANE_MAP)); + if (ChipConfig =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + FreePool (ChipConfig); + return EFI_OUT_OF_RESOURCES; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdComPhyDevices); Index++) { - if (!MVHW_DEV_ENABLED (ComPhy, Index)) { - DEBUG ((DEBUG_ERROR, "Skip ComPhy chip %d\n", Index)); - continue; - } + for (Index =3D 0; Index < ComPhyBoardDesc->ComPhyDevCount; Index++) { =20 PtrChipCfg =3D &ChipConfig[Index]; - InitComPhyConfig(PtrChipCfg, LaneData, Index); + InitComPhyConfig (PtrChipCfg, LaneData, &ComPhyBoardDesc[Index]); =20 /* Get the count of the SerDes of the specific chip */ MaxComphyCount =3D PtrChipCfg->LanesCount; @@ -275,5 +287,9 @@ MvComPhyInit ( PtrChipCfg->Init (PtrChipCfg); } =20 + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); + FreePool (ChipConfig); + FreePool (LaneData); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362811850703.4260037907326; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:21 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22a; helo=mail-lf0-x22a.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=34tHzhg5Zw5r/8Usds7ysjuFQPj59xU3nG245GwKZFY=; b=k8fM5Yhca+5AMejpguTWDL6fo2ND99VV7U1Q/9L/M4MKEwSW+RTp2OWUFf5hJnrrwF G+m5v3ZNQBlX5/Ca1c+AVbUnmbLDb0iDHZFvxZ7CXvbdYOm08dg+0uRLlEiSohBYjfzV wuabGAIeDDWZirqZbNB+FIhA7fTnh0KDvoXZt3ocRO3KAwOTjtAx8utf3TZ+6+mmP6wm 8O0AtvFxh/ndcqpRHc6GxY9DpPBIqnQPEYyrgRToMxt+8ejiCVWAYuTiCG1qO4Pcebuu K8Q7JJPJ5lFX98dmHe5M5OZ2JSVRxpKMlLJj+lOuhsrRsMaaTJZm6UPatEh9BsTxN1I3 ljxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=34tHzhg5Zw5r/8Usds7ysjuFQPj59xU3nG245GwKZFY=; b=b5edBMxmcwnHA5rBHGzJ612ksvjJeXmTc4xFVSWqYuSEAxgFQpCOmhVOK1UpZCWHob ifa7qpgQSgtc6RMgcYyXClyxinDFGa4YCLok7IQGJOwlms1pQSmRC87AZ5tNuPGJPWW7 ubzglCL7O3mOCOb9LSFmDzReHBgKDmt0eVXF7BdYl5HEKhY9qbkYdHlwzBPoybBXVwEW +3aD0HwCIrxKrsKA/PTsgxvvZkxzXm3ZAhH7cvWGYdg1kgVPw9RgGuXMhMwV3Og9kOgP 41Ymt0paSw9LXGtLXxiqg+UzN1IZUmpTGw2jEyKf18A5FNQdXm0wBa5hom2Go1G0zuPS JRng== X-Gm-Message-State: APt69E1fo3jJbYxmFGVLLsTgblcaNlNtuaF3Ow6SFPqs1Kb7bRdehokH YWutZnIQB/wJjzQFsXxo0M0nQFHWgHk= X-Google-Smtp-Source: ADUXVKJEVYB+n0B5xN4ZfDXURNciAApxO3V7yazlAkfuCnZsPMcR7n0wNAcWwSBMi2Vmorl6z9hS7A== X-Received: by 2002:a2e:5111:: with SMTP id f17-v6mr7539056ljb.16.1529362762569; Mon, 18 Jun 2018 15:59:22 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:37 +0200 Message-Id: <1529362724-9244-19-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 18/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with MDIO information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescMdioGet ()), which dynamically allocates and fills MV_SOC_MDIO_DESC structure with the SoC description of Mdio controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 6 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 15 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 29 ++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index f254b1c..87fc140 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -38,6 +38,12 @@ #define MV_SOC_COMPHY_MUX_BITS 4 =20 // +// Platform description of MDIO controllers +// +#define MV_SOC_MDIO_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x12A200) +#define MV_SOC_MDIO_ID(Cp) (Cp) + +// // Platform description of PP2 NIC // #define MV_SOC_PP2_BASE(Cp) MV_SOC_CP_BASE (Cp) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index a133d1c..304d068 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -37,6 +37,21 @@ ArmadaSoCDescComPhyGet ( ); =20 // +// MDIO +// +typedef struct { + UINTN MdioId; + UINTN MdioBaseAddress; +} MV_SOC_MDIO_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescMdioGet ( + IN OUT MV_SOC_MDIO_DESC **MdioDesc, + IN OUT UINTN *DescCount + ); + +// // NonDiscoverable devices SoC description // // AHCI diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 580c0f4..652677f 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -63,6 +63,35 @@ ArmadaSoCDescComPhyGet ( =20 EFI_STATUS EFIAPI +ArmadaSoCDescMdioGet ( + IN OUT MV_SOC_MDIO_DESC **MdioDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_MDIO_DESC *Desc; + UINTN CpCount, CpIndex; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + Desc =3D AllocateZeroPool (CpCount * sizeof (MV_SOC_MDIO_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + Desc[CpIndex].MdioId =3D MV_SOC_MDIO_ID (CpIndex); + Desc[CpIndex].MdioBaseAddress =3D MV_SOC_MDIO_BASE (CpIndex); + } + + *MdioDesc =3D Desc; + *DescCount =3D CpCount; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescAhciGet ( IN OUT MV_SOC_AHCI_DESC **AhciDesc, IN OUT UINTN *DescCount --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362816282937.7032127260112; Mon, 18 Jun 2018 16:00:16 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 17C512110A3D4; Mon, 18 Jun 2018 15:59:29 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AD44A2110A3C4 for ; Mon, 18 Jun 2018 15:59:25 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id v84-v6so4003954lfa.1 for ; Mon, 18 Jun 2018 15:59:25 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:23 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=e4oz/LVphMrgpG7kOr3kzkP1Z6zzpTSWmZepUbAKxeU=; b=xk9rpOhT5YJfa5v8yUTNGwNEC++egyA4le3ELr5rH0+VKFd1ruod9JljOdV4xuSpAD 03oPNm0yzQ85vfWvjhTweZFbK44Y5utZMBf6nnl9dDc2iOszq1S+W1luvlNOYqKRBZOF QsOTL4rRMqe0VyWc2L7HV0QHpQZNrHyz5oRXW1ZssT0P87okhI8RyakuGzh5phflaVwc RRInlgxGpB4J1jm2QbdHQDECCp1MtM/b4mx4+8668R49Q4EXJOzyjxYUfJHVH1NaYNfZ w3QIYnwkHICmroPakvVxsjq94J7g2A1Q/9fGXVtYtOlVNIQIEFYZag/POkD/nkRkywgu SwBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=e4oz/LVphMrgpG7kOr3kzkP1Z6zzpTSWmZepUbAKxeU=; b=fww1BD+H+KBzUq7vQ1QeXRsR6oBkyOCLw5cT3ZqI61vDqVkrZSqfXZqOslrFfiphVB p14E2+dnv9yEJNDtw2g4PA5EOdptqIYJLnlE8jdGEhUu6uxxMzqb8/ljGWodhZOmZcLo bKZcDupPThflFe+2J7TfN6M2DwnvW/++eAURfRRpFIYRKWzNMz+ItGEacfoejSxkbvd8 bTrOQJx4A8yHMyqiOWc2yJQHxsdjjIIGXYW643txntR4Qj5vjuqXvp8lPbKuB2zhVkqY 7iHQqkMo66OvmGX1lUUpTnP30xG57ggrRJ435RmD+d3ywXMd/jLZuj9iRNZkm+p1EbxA q2Ig== X-Gm-Message-State: APt69E1JyAkgXL3OVAgi53mfja20XtrzJZ308SB/x+u+Jk+WXYgi08Yv 5ba2Le99SluZMtkCr8V7F8f/IVlGQls= X-Google-Smtp-Source: ADUXVKJOOnhXPaxkQGxg2ar3ohdRk0XFDWiE0Cja2gw0ZNM5gwxWzSPO2Bfv61IU7pTrvE7zmKvRBw== X-Received: by 2002:a2e:420e:: with SMTP id p14-v6mr9978308lja.26.1529362763736; Mon, 18 Jun 2018 15:59:23 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:38 +0200 Message-Id: <1529362724-9244-20-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 19/25] Marvell/Drivers: MvBoardDesc: Extend protocol with MDIO support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about MDIO controllers to the Mdio driver. Extend ArmadaBoardDescLib with new structure MV_BOARD_MDIO_DESC, for holding board specific data. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 8 +++++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 36 ++++++++++++++++= ++++ 3 files changed, 52 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index 32bd915..b11fa9d 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -25,6 +25,14 @@ typedef struct { } MV_BOARD_COMPHY_DESC; =20 // +// MDIO devices per-board description +// +typedef struct { + MV_SOC_MDIO_DESC *SoC; + UINTN MdioDevCount; +} MV_BOARD_MDIO_DESC; + +// // NonDiscoverableDevices per-board description // =20 diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index b6dac75..55297f5 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -50,6 +50,13 @@ EFI_STATUS =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_MDIO_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_MDIO_DESC **MdioDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_AHCI_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -92,6 +99,7 @@ VOID struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; + MV_BOARD_DESC_MDIO_GET BoardDescMdioGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 6bbe40b..5dfc559 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -100,6 +100,41 @@ MvBoardDescComPhyGet ( =20 STATIC EFI_STATUS +MvBoardDescMdioGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_MDIO_DESC **MdioDesc + ) +{ + MV_BOARD_MDIO_DESC *BoardDesc; + MV_SOC_MDIO_DESC *SoCDesc; + UINTN MdioCount, Index; + EFI_STATUS Status; + + /* Get SoC data about all available MDIO controllers */ + Status =3D ArmadaSoCDescMdioGet (&SoCDesc, &MdioCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (MdioCount * sizeof (MV_BOARD_MDIO_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < MdioCount; Index++) { + BoardDesc[Index].SoC =3D &SoCDesc[Index]; + } + + BoardDesc->MdioDevCount =3D MdioCount; + *MdioDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescAhciGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_AHCI_DESC **AhciDesc @@ -456,6 +491,7 @@ MvBoardDescInitProtocol ( { BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; + BoardDescProtocol->BoardDescMdioGet =3D MvBoardDescMdioGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; BoardDescProtocol->BoardDescUtmiGet =3D MvBoardDescUtmiGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362821055737.7095621151421; Mon, 18 Jun 2018 16:00:21 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3F2062110A3D7; Mon, 18 Jun 2018 15:59:29 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EB7ED2110A3D0 for ; Mon, 18 Jun 2018 15:59:26 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id i15-v6so27174345lfc.2 for ; Mon, 18 Jun 2018 15:59:26 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:24 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8Gy3cHCMsm0ecmSBRI6IGHVj5v9VQ927WS3W+nixQpg=; b=qBfrbueZvHHHUA7J7IQMYBbxT211HJdYnPnECSAOuUfZPdvJuKSAyVnDRj09+7hfiC Y4VtN1Wn18Z7aWAxwLfx9+q4HCMcQGiUqP5pgn6w+/Fzj+Dm1p3ANgeCRfuI3URT8QEh PWSM5IDZvki+Ly5rbCEHSTxAIcNORBw0T8MO8IhIKD5glxMs5rLErz238o6YIUl/VV9P T0Zx9nsgfqsc0zxyvmW1dJG6cihsSnDVl/iXlNIVhXFVJwdqcOaXhNK0gRQWZZ+tdnWv UgAch7Xk6/i5u6PXhArmS3oqsJ4NQh9RNCpvxZDF/pOl/mNiWJ5vX4hoPrzSkMVDIJE+ TCAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8Gy3cHCMsm0ecmSBRI6IGHVj5v9VQ927WS3W+nixQpg=; b=kSt4+A/3qERuQBHXUKjupw2si9VhWOZ1CbqKNvdl8NphH3BrSJraNqncijNB8xwTLd E3HgmOzqjmAvDQyKTArsA9hHeMzdQvJ9xnjhXTvJyyOMOv0GXHfuDXh73mvg9I2hTQ5B +/RgUdGrAJHOL/hQWTdYwMXty0gefULxwzN3N2Rq5xx+mzhIIvO+RRa7YcnrUcpoY7AZ 9QGkpE49QMIo2T311y2tBSukfvMkjjwTHtzm3Nx9anaDgNrfBWlsHnbsjAXEFoeN1OjE EcsxXzgOXZ4SnwxfOdRkBkOni2FVWmV4L1G0ilEm31GISrN2Yhcn3yDCMloi07N1pY5I Oz3g== X-Gm-Message-State: APt69E1q4eqIXlNuFPrfz2uOseT2i/JiJInQmVdeKwjon7X1lwGZoD8X mLbgMtipLX9O2zuKkDgvbfNdmEAc1WY= X-Google-Smtp-Source: ADUXVKJ29SowFo8k7yxzFXOmgDCYij9uk0KlTNrT5l0cOrCGDvCqVgmb5QzigAjk2Yes/29uidOTvQ== X-Received: by 2002:a2e:635b:: with SMTP id x88-v6mr9916812ljb.103.1529362765041; Mon, 18 Jun 2018 15:59:25 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:39 +0200 Message-Id: <1529362724-9244-21-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 20/25] Marvell/Drivers: MvMdioDxe: Enable 64bit addressing X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In order to be prepared for operating on registers in 64-bit address space, this patch adjusts the MDIO controllers base address array. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c b/Silicon/Ma= rvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c index 12aabad..6c0a129 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c @@ -70,7 +70,7 @@ MdioCheckParam ( STATIC EFI_STATUS MdioWaitReady ( - UINT32 MdioBase + UINTN MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -92,7 +92,7 @@ MdioWaitReady ( STATIC EFI_STATUS MdioWaitValid ( - UINT32 MdioBase + UINTN MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -122,7 +122,7 @@ MdioOperation ( IN OUT UINT32 *Data ) { - UINT32 MdioBase =3D This->BaseAddresses[MdioIndex]; + UINTN MdioBase =3D This->BaseAddresses[MdioIndex]; UINT32 MdioReg; EFI_STATUS Status; =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362825553887.4432339388127; Mon, 18 Jun 2018 16:00:25 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 672A62110A3DB; Mon, 18 Jun 2018 15:59:29 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3D6A22110A3C6 for ; Mon, 18 Jun 2018 15:59:28 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id u5-v6so5932994lff.13 for ; Mon, 18 Jun 2018 15:59:28 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:25 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BAq84YYEkMg9IyqVTYYQYMT7uguTedJSNFEVqD4TwHE=; b=SCEFfqvajtoExE1sevQR+Z81S7+BW4quThhQoUBWgnaW4AgOMJWM54Vr+WPVkkuCH8 V+NJ/mUA5kQ360HyLFPC3Nzae/keIPPATVvZa2RmIAEHMAhHZ5fwDLVlEpPjsCaNu313 TA3TVrGTGgJ6at4co2SQcCkj72rXERcHpKbqEu1Tlbsc2/DEn99wavDMOQIssHGFaJ0d 1/SGCPiW9/Onar/u+OGD8by20S57Ec/cnVhb8IWncWLm2zy79uJxN/GdPch6PSuWnKIF AhxI4sadEXbQaeldl7sSxYrJR4ehDGkhxVOpPro2hux4PHk7l94HmNRo0NGYC87rVx02 ghHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BAq84YYEkMg9IyqVTYYQYMT7uguTedJSNFEVqD4TwHE=; b=md0OSvAfGxmKI49IqDBBKhpMv/BgNp+ZTDmsc3tLYybUS1OirZe9gv5Xj8acBBnOJZ 6OaO2gaYXNfuqAgBe6rknlizmreFvmGZWGV7Uw/vl2L5nyCzpnTcW0piqqrsOzWPPbJg 7IGK6oDT5a583Z+/tTV3qaW1ImUcwpTfpUIU9cxcXCywW2ilhJ955TbEzc6T2WA8OGCR tWyRuWQ5TnaRMoVvkEYhVRCqWxD/5N1XjbVSNCkRSFP/kavLxcm0wVYqXPuHZjCPSnD+ DRbJW0w+4en2NE8hZrNWJp+zKFCoZhdQjwJsdI8noCCIxtiZ+mEEvQ+o9M5YqjZLP4GW xdGA== X-Gm-Message-State: APt69E0V5NCSU+CrBIrCh6g4SkVgUrTaIhNpwqNoeN5z0RXvkEZz3R5c n3fn4jv7zbewOLliq96HHbHLQUWvVJ0= X-Google-Smtp-Source: ADUXVKLsU93lmM0Pq/Ph7b85eJ8ryzPuF3BtGqEoZ2a1eOv/6AUgPmy0pJF3nN5My5VH3tUajZONIQ== X-Received: by 2002:a2e:c52:: with SMTP id o18-v6mr9374106ljd.72.1529362766273; Mon, 18 Jun 2018 15:59:26 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:40 +0200 Message-Id: <1529362724-9244-22-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 21/25] Marvell/Drivers: MvMdioDxe: Switch driver to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" MvMdioDxe driver used to get Armada7k8k controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 1 + Silicon/Marvell/Include/Library/MvHwDescLib.h | 23 ------------- Silicon/Marvell/Include/Protocol/Mdio.h | 4 +-- Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c | 35 ++++++++++++++++-= --- 4 files changed, 31 insertions(+), 32 deletions(-) diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf b/Silicon/= Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf index c070785..739576f 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf @@ -60,6 +60,7 @@ UefiLib =20 [Protocols] + gMarvellBoardDescProtocolGuid gMarvellMdioProtocolGuid =20 [Depex] diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h index 423ca17..0de435d 100644 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h @@ -53,16 +53,6 @@ typedef struct { } MVHW_I2C_DESC; =20 // -// MDIO devices description template definition -// -#define MVHW_MAX_MDIO_DEVS 2 - -typedef struct { - UINT8 MdioDevCount; - UINTN MdioBaseAddresses[MVHW_MAX_MDIO_DEVS]; -} MVHW_MDIO_DESC; - -// // Platform description of I2C devices // #define MVHW_CP0_I2C0_BASE 0xF2701000 @@ -77,17 +67,4 @@ MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ { MVHW_CP0_I2C0_BASE, MVHW_CP0_I2C1_BASE, MVHW_CP1_I2C0_BASE, MVHW_CP1_I= 2C1_BASE }\ } =20 -// -// Platform description of MDIO devices -// -#define MVHW_CP0_MDIO_BASE 0xF212A200 -#define MVHW_CP1_MDIO_BASE 0xF412A200 - -#define DECLARE_A7K8K_MDIO_TEMPLATE \ -STATIC \ -MVHW_MDIO_DESC mA7k8kMdioDescTemplate =3D {\ - 2,\ - { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ -} - #endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Include/Protocol/Mdio.h b/Silicon/Marvell/Incl= ude/Protocol/Mdio.h index d077a8f..076ea26 100644 --- a/Silicon/Marvell/Include/Protocol/Mdio.h +++ b/Silicon/Marvell/Include/Protocol/Mdio.h @@ -35,8 +35,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MDIO_H__ #define __MDIO_H__ =20 -#include - #define MARVELL_MDIO_PROTOCOL_GUID { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0= x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} =20 typedef struct _MARVELL_MDIO_PROTOCOL MARVELL_MDIO_PROTOCOL; @@ -64,7 +62,7 @@ EFI_STATUS struct _MARVELL_MDIO_PROTOCOL { MARVELL_MDIO_READ Read; MARVELL_MDIO_WRITE Write; - UINTN BaseAddresses[MVHW_MAX_MDIO_DEVS]; + UINTN *BaseAddresses; UINTN ControllerCount; }; =20 diff --git a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c b/Silicon/Ma= rvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c index 6c0a129..72e88bd 100644 --- a/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c +++ b/Silicon/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include =20 @@ -46,8 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "MvMdioDxe.h" =20 -DECLARE_A7K8K_MDIO_TEMPLATE; - STATIC EFI_STATUS MdioCheckParam ( @@ -216,24 +215,46 @@ MvMdioDxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_MDIO_DESC *Desc =3D &mA7k8kMdioDescTemplate; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_MDIO_DESC *MdioBoardDesc; UINT8 Index; MARVELL_MDIO_PROTOCOL *Mdio; EFI_STATUS Status; EFI_HANDLE Handle =3D NULL; =20 + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D BoardDescProtocol->BoardDescMdioGet (BoardDescProtocol, + &MdioBoardDesc); + if (EFI_ERROR (Status)) { + return Status; + } + Mdio =3D AllocateZeroPool (sizeof (MARVELL_MDIO_PROTOCOL)); if (Mdio =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "MdioDxe: Protocol allocation failed\n")); return EFI_OUT_OF_RESOURCES; } =20 + Mdio->BaseAddresses =3D AllocateZeroPool (MdioBoardDesc->MdioDevCount * + sizeof (UINTN)); + if (Mdio->BaseAddresses =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "MdioDxe: Protocol allocation failed\n")); + return EFI_OUT_OF_RESOURCES; + } + /* Obtain base addresses of all possible controllers */ - for (Index =3D 0; Index < Desc->MdioDevCount; Index++) { - Mdio->BaseAddresses[Index] =3D Desc->MdioBaseAddresses[Index]; + for (Index =3D 0; Index < MdioBoardDesc->MdioDevCount; Index++) { + Mdio->BaseAddresses[Index] =3D MdioBoardDesc[Index].SoC->MdioBaseAddre= ss; } =20 - Mdio->ControllerCount =3D Desc->MdioDevCount; + Mdio->ControllerCount =3D MdioBoardDesc->MdioDevCount; Mdio->Read =3D MvMdioRead; Mdio->Write =3D MvMdioWrite; =20 @@ -248,5 +269,7 @@ MvMdioDxeInitialise ( return Status; } =20 + BoardDescProtocol->BoardDescFree (MdioBoardDesc); + return EFI_SUCCESS; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362829887436.10901698715713; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:26 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tBfLg+fYJ9Wla/ScJjgiPAvhxQ0/5XVYg8h0lggrEuQ=; b=j3YmiGcLUjxo781szOXesyNASXYSZs9NnM1mHmr/ii2u9Cd9DMIb0y6f1A7VrRHvIV 4LKJ/2kN0KEywiSGyWT9E1JEp29B/4cL2aMJKZW3Ylu57An6r6xz+HuzRllbzbUJ8zCv IIKWV720ckdNo2X7JZ9snZHsx2agjMSkExqjR2PD6XX/ha/Hc90KfZemPrrnXt7+OfUj QKzYxibVPAxwj39/+fQuWZcmzclXAsMkfd4Mk8Ao6gzizFMWvWgItnZuBDYZEhFRa6R2 I2/k1vTyt6vFA1lOTeIn1zvafFpZQ+oZTjmH7xgmuOFXlK1sJ+ZNgR2XCP19P4xQWGUU dKWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tBfLg+fYJ9Wla/ScJjgiPAvhxQ0/5XVYg8h0lggrEuQ=; b=ayrBuKGv3UjzjUiMK+X4zfY5+muedFe/6II4iBaE8IvrX2FLuvQgp95KINDOVOlb9F IulHPvVybr4YFbOyl2MXdSsFLye4/wGj75UZQfZC7ikIKRg7l1pRVMOGMG5sPKDoSWyH KoMNvWxvO5K8hySijF7pxVop+xQl2yCoHn7+zsU05dqjV3lkakJx8xlyuc+2Y3f8F+Eq SoFe3Lu6ccQi0HpibU/vAJDRT7dQ6mmLmpDeGyHpNBCFcRlw5KMCA8MC8XP0P0rTs0YS UxQc7CyvmiKvymDp1+wV1UoaAwNTwu5gD0LoXC0KZdoSr051HVM77PKlxT61tYCn0Zp3 EVLA== X-Gm-Message-State: APt69E2BIl/Z8qJN+nuLC8r1xIxwEPF9DwSxOHeSVyhmBCXjUpHg2sic 3GBxkcQDahplHtbbhziGxpPqEBLxa8o= X-Google-Smtp-Source: ADUXVKJ1ob5uwtiqsWKtaPzbHV8WQtiR6vzK8HuzlwOpx4eCr4gbsBUkYLJeIIAcFcqst62HgyZfKQ== X-Received: by 2002:a2e:2948:: with SMTP id u69-v6mr9230253lje.130.1529362767512; Mon, 18 Jun 2018 15:59:27 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:41 +0200 Message-Id: <1529362724-9244-23-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 22/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with I2C information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces new library callback (ArmadaSoCDescI2cGet ()), which dynamically allocates and fills MV_SOC_I2C_DESC structure with the SoC description of I2c controllers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.h | 6 ++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 15 ++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescL= ib.c | 31 ++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.h index 87fc140..3072883 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.h @@ -38,6 +38,12 @@ #define MV_SOC_COMPHY_MUX_BITS 4 =20 // +// Platform description of I2C controllers +// +#define MV_SOC_I2C_PER_CP_COUNT 2 +#define MV_SOC_I2C_BASE(I2c) (0x701000 + ((I2c) * 0x100)) + +// // Platform description of MDIO controllers // #define MV_SOC_MDIO_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x12A200) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/M= arvell/Include/Library/ArmadaSoCDescLib.h index 304d068..d2bcf2a 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -37,6 +37,21 @@ ArmadaSoCDescComPhyGet ( ); =20 // +// I2C +// +typedef struct { + UINTN I2cId; + UINTN I2cBaseAddress; +} MV_SOC_I2C_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescI2cGet ( + IN OUT MV_SOC_I2C_DESC **I2cDesc, + IN OUT UINTN *DescCount + ); + +// // MDIO // typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada= 7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/= Armada7k8kSoCDescLib.c index 652677f..6ce6bad 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoC= DescLib.c @@ -63,6 +63,37 @@ ArmadaSoCDescComPhyGet ( =20 EFI_STATUS EFIAPI +ArmadaSoCDescI2cGet ( + IN OUT MV_SOC_I2C_DESC **I2cDesc, + IN OUT UINTN *DescCount + ) +{ + MV_SOC_I2C_DESC *Desc; + UINTN CpCount, CpIndex, Index; + + CpCount =3D FixedPcdGet8 (PcdMaxCpCount); + + *DescCount =3D CpCount * MV_SOC_I2C_PER_CP_COUNT; + Desc =3D AllocateZeroPool (*DescCount * sizeof (MV_SOC_I2C_DESC)); + if (Desc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + *I2cDesc =3D Desc; + + for (CpIndex =3D 0; CpIndex < CpCount; CpIndex++) { + for (Index =3D 0; Index < MV_SOC_I2C_PER_CP_COUNT; Index++) { + Desc->I2cBaseAddress =3D MV_SOC_CP_BASE (CpIndex) + MV_SOC_I2C_BASE = (Index); + Desc++; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI ArmadaSoCDescMdioGet ( IN OUT MV_SOC_MDIO_DESC **MdioDesc, IN OUT UINTN *DescCount --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362834520280.7189256019576; Mon, 18 Jun 2018 16:00:34 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C34342110A3E4; Mon, 18 Jun 2018 15:59:32 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B857D21107824 for ; Mon, 18 Jun 2018 15:59:30 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id i15-v6so27174495lfc.2 for ; Mon, 18 Jun 2018 15:59:30 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4gZXvj4qSJ+6OCMfF8sIRWTHwWuOz/+vLS0nr4+dYDA=; b=oaFDMK+qDUtU8AeLccsaVUXCqYuqwdFjkgUMBG5gp++C0emzxHwCpMrhGA95C2hkeo UkpywR8xP/4w5Rib4Wu72BrhSbxSbBq9EtgPGxjPbgGOWTc5kSQJqW9j9t9GWs0IxvQm cljp4daOr94mMSzyoz4V1cLEHSpE0G9yu/dXrqLyOYxBSgGLPbFdwj4h4g857JCl0EfR B5locShCXDoJS14HNdMBL4iUvsWgYpkAEZZL1wbGzL3s6Xq8Dm3xQxvnyFSiO75/4kJo +McNXVB67a0qu2CgfYbMRkI8WEez4cv5pqdI568HkPVGxSBHWmJrPB4f3V/y91xo27Gk 6pAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4gZXvj4qSJ+6OCMfF8sIRWTHwWuOz/+vLS0nr4+dYDA=; b=MZBVxzgs3gEKx0j646U+/AJA2JEmydUYo7X+Rfy+t6YdivsqNG15Exf3w9wVlX61e0 ii9tgeVvMFFLHFXsBlXeZo4bmAhWEuWtMhwRD+lvyzxLjLL0thKpH5UaRNabktErY97M M9p/rnKDqy5E3GZBqzI3NH6mfZUeF5EkMnSPHE3oGKEGyrEy/jgP7G7kYT8K9OtgW0Px yCVi17qEIgzswPGTguKmPxWDIHqwrafs1sPH/WhoEJzwpADfE8120CCp0xMc+CjvB/5p 6/T5ljBPGVyGYOwP6H0UKfUHl2iuDvlXx4wBZVMx10oy08OM2UdV7qjd6LcntEA9Hpqx vY8g== X-Gm-Message-State: APt69E29gcKj7B4gF2byN3GHgtkUHioed85d+MAvqDaLDdvrgZmrE3+8 jNsy2+fJ3iDUTLFdfNglG8qYLmHcv2k= X-Google-Smtp-Source: ADUXVKJSOLUoRCcyPBe58LNU8QXYqCzgAEuMUFXGi+AKpwfoY9NnyfcdgesrfLhY7n5TP1kGiulUKw== X-Received: by 2002:a2e:1414:: with SMTP id u20-v6mr9652422ljd.134.1529362768709; Mon, 18 Jun 2018 15:59:28 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:42 +0200 Message-Id: <1529362724-9244-24-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 23/25] Marvell/Drivers: MvBoardDesc: Extend protocol with I2C support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce new callback that can provide information about I2C controllers to the I2c driver. Extend ArmadaBoardDescLib with new structure MV_BOARD_I2C_DESC, for holding board specific data. In further steps it should be extended and replace PCD I2C devices' representation with the appropriate structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 1 + Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 8 +++ Silicon/Marvell/Include/Protocol/BoardDesc.h | 8 +++ Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 66 ++++++++++++++++= ++++ 4 files changed, 83 insertions(+) diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon= /Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf index dea99fd..41f72d6 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf @@ -58,6 +58,7 @@ =20 [Pcd] gMarvellTokenSpaceGuid.PcdComPhyDevices + gMarvellTokenSpaceGuid.PcdI2cControllersEnabled gMarvellTokenSpaceGuid.PcdPciEAhci gMarvellTokenSpaceGuid.PcdPciESdhci gMarvellTokenSpaceGuid.PcdPciEXhci diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon= /Marvell/Include/Library/ArmadaBoardDescLib.h index b11fa9d..ee8e06e 100644 --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h @@ -25,6 +25,14 @@ typedef struct { } MV_BOARD_COMPHY_DESC; =20 // +// I2C devices per-board description +// +typedef struct { + MV_SOC_I2C_DESC *SoC; + UINTN I2cDevCount; +} MV_BOARD_I2C_DESC; + +// // MDIO devices per-board description // typedef struct { diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell= /Include/Protocol/BoardDesc.h index 55297f5..1d57a16 100644 --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h @@ -50,6 +50,13 @@ EFI_STATUS =20 typedef EFI_STATUS +(EFIAPI *MV_BOARD_DESC_I2C_GET) ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_I2C_DESC **I2cDesc + ); + +typedef +EFI_STATUS (EFIAPI *MV_BOARD_DESC_MDIO_GET) ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_MDIO_DESC **MdioDesc @@ -99,6 +106,7 @@ VOID struct _MARVELL_BOARD_DESC_PROTOCOL { MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; MV_BOARD_DESC_COMPHY_GET BoardDescComPhyGet; + MV_BOARD_DESC_I2C_GET BoardDescI2cGet; MV_BOARD_DESC_MDIO_GET BoardDescMdioGet; MV_BOARD_DESC_PP2_GET BoardDescPp2Get; MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/M= arvell/Drivers/BoardDesc/MvBoardDescDxe.c index 5dfc559..39dc06c 100644 --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c @@ -100,6 +100,71 @@ MvBoardDescComPhyGet ( =20 STATIC EFI_STATUS +MvBoardDescI2cGet ( + IN MARVELL_BOARD_DESC_PROTOCOL *This, + IN OUT MV_BOARD_I2C_DESC **I2cDesc + ) +{ + UINT8 *I2cDeviceEnabled; + UINTN I2cCount, I2cDeviceEnabledSize, I2cIndex, Index; + MV_BOARD_I2C_DESC *BoardDesc; + MV_SOC_I2C_DESC *SoCDesc; + EFI_STATUS Status; + + /* Get SoC data about all available I2C controllers */ + Status =3D ArmadaSoCDescI2cGet (&SoCDesc, &I2cCount); + if (EFI_ERROR (Status)) { + return Status; + } + + /* + * Obtain table with enabled I2C controllers + * which is represented as an array of UINT8 values + * (0x0 - disabled, 0x1 enabled). + */ + I2cDeviceEnabled =3D PcdGetPtr (PcdI2cControllersEnabled); + if (I2cDeviceEnabled =3D=3D NULL) { + /* No I2C on platform */ + return EFI_SUCCESS; + } + + I2cDeviceEnabledSize =3D PcdGetSize (PcdI2cControllersEnabled); + + /* Check if PCD with I2C controllers is correctly defined */ + if (I2cDeviceEnabledSize > I2cCount) { + DEBUG ((DEBUG_ERROR, + "%a: Wrong PcdI2cControllersEnabled format\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + /* Allocate and fill board description */ + BoardDesc =3D AllocateZeroPool (I2cDeviceEnabledSize * sizeof (MV_BOARD_= I2C_DESC)); + if (BoardDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + I2cIndex =3D 0; + for (Index =3D 0; Index < I2cDeviceEnabledSize; Index++) { + if (!I2cDeviceEnabled[Index]) { + DEBUG ((DEBUG_INFO, "%a: Skip I2c controller %d\n", __FUNCTION__, In= dex)); + continue; + } + + BoardDesc[I2cIndex].SoC =3D &SoCDesc[Index]; + I2cIndex++; + } + + BoardDesc->I2cDevCount =3D I2cIndex; + + *I2cDesc =3D BoardDesc; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS MvBoardDescMdioGet ( IN MARVELL_BOARD_DESC_PROTOCOL *This, IN OUT MV_BOARD_MDIO_DESC **MdioDesc @@ -491,6 +556,7 @@ MvBoardDescInitProtocol ( { BoardDescProtocol->BoardDescAhciGet =3D MvBoardDescAhciGet; BoardDescProtocol->BoardDescComPhyGet =3D MvBoardDescComPhyGet; + BoardDescProtocol->BoardDescI2cGet =3D MvBoardDescI2cGet; BoardDescProtocol->BoardDescMdioGet =3D MvBoardDescMdioGet; BoardDescProtocol->BoardDescPp2Get =3D MvBoardDescPp2Get; BoardDescProtocol->BoardDescSdMmcGet =3D MvBoardDescSdMmcGet; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362839452756.5688191080019; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:29 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=48Re+kklzRZO4J3+y1wRUlw4RXxrsc0ZdFtQT+ooXFw=; b=sscSWUVpV/wg7s6W0Mhd8xoolFBvsz7ViYJHD9Rx00Cc7o218wUvU0g3OFZatbDHY8 4G2gylIsyPphNpPrBUW9NOAiv1ptr6s031J18d+bJkBOsBspyjKz3TCIichiG8Do1E0R b+oTqywENSOYGchPucsBx4ASifP0r+6bmJn0D6okm4Mpj27qXT+axtEFyivyumu1GEXz AkOPzXPS5mzQfI0J7Wb/c7M88kTwuREExlNisC3rqbDkNYSsPu+2fueJ81FUf0+hp8ml em3fp4LEGZz8CCjKxHxB3L0F6/QkUSp19izQFQBWV89ErHIfg3OJvGoO8MwUQ2wRQiG/ Ma4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=48Re+kklzRZO4J3+y1wRUlw4RXxrsc0ZdFtQT+ooXFw=; b=LdQXAbHQtpozHDmcBEOTbeKqGWzZkOaZOBi9hzIZt2AbecEXDHKI1fTg1+CB/IACLc rpd581q/jy2GqeMCVs2KlYvEFfek7B13DUC15GSLMcabmITYOXRbRwgCAiGULZgcrgUI JOMPDKi2tnCMKC4+YFObobZNDL9pmR4CQ95R4LOg+vC7R64XrgLFpzJKT77k3gbhwazW /43NjuMT5U/2NDPsUQn0RahVF82PVOMmETgjG7FDgGVvC72ybIIxlXv9p9h0wvA+6smg 1FWxcpeFx3p0bNe13mDf6eRBUFDkeCioUpcNAvvIp17wGgP8xskW5IhIZQBJIhD0sR64 To6Q== X-Gm-Message-State: APt69E2LXPY0Qsvu/HZNEmbN9yr3qJ6VsLMlAbbygvJhQxbSxtk1rk7n VsaLvyTJ9UhiCzQ0rZfeWLGMl2Ko4Ng= X-Google-Smtp-Source: ADUXVKINZzXA9IthBTcsudX0GksLilCmV1eBoXbf/cyFXtK9qbg8u7e5fbaDmd39g+TIZjLFHEa1ng== X-Received: by 2002:a2e:8590:: with SMTP id b16-v6mr9009574lji.131.1529362769950; Mon, 18 Jun 2018 15:59:29 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:43 +0200 Message-Id: <1529362724-9244-25-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 24/25] Marvell/Drivers: MvI2cDxe: Switch driver to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" MvI2cDxe driver used to get Armada7k8k controller description from hardcoded values stored in the header file MvHwDescLib.h. As a result it is very hard to support other Armada SoC families with this driver. This patch updates the driver, so that it can obtain the description from newly introduced MARVELL_BOARD_DESC protocol, and removes the dependency on the hardcoded structures. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 1 + Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 37 +++++++++----------- 2 files changed, 18 insertions(+), 20 deletions(-) diff --git a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Silicon/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf index a7cf52e..0eef350 100755 --- a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf +++ b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf @@ -61,6 +61,7 @@ gEfiDevicePathProtocolGuid gEfiI2cEnumerateProtocolGuid gEfiI2cBusConfigurationManagementProtocolGuid + gMarvellBoardDescProtocolGuid =20 [Pcd] gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses diff --git a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Silicon/Marv= ell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index d6f590d..9ec4929 100755 --- a/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Silicon/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -32,6 +32,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 **************************************************************************= *****/ =20 +#include #include #include #include @@ -43,13 +44,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include #include #include -#include #include =20 #include "MvI2cDxe.h" =20 -DECLARE_A7K8K_I2C_TEMPLATE; - STATIC MV_I2C_BAUD_RATE baud_rate; =20 STATIC MV_I2C_DEVICE_PATH MvI2cDevicePathProtocol =3D { @@ -174,38 +172,37 @@ MvI2cInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { - MVHW_I2C_DESC *Desc =3D &mA7k8kI2cDescTemplate; - UINT8 *I2cDeviceTable, Index; + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; + MV_BOARD_I2C_DESC *Desc; EFI_STATUS Status; + UINTN Index; =20 - /* Obtain table with enabled I2c devices */ - I2cDeviceTable =3D (UINT8 *)PcdGetPtr (PcdI2cControllersEnabled); - if (I2cDeviceTable =3D=3D NULL) { - DEBUG ((DEBUG_ERROR, "Missing PcdI2cControllersEnabled\n")); - return EFI_INVALID_PARAMETER; + /* Obtain list of available controllers */ + Status =3D gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, + NULL, + (VOID **)&BoardDescProtocol); + if (EFI_ERROR (Status)) { + return Status; } =20 - if (PcdGetSize (PcdI2cControllersEnabled) > MVHW_MAX_I2C_DEVS) { - DEBUG ((DEBUG_ERROR, "Wrong PcdI2cControllersEnabled format\n")); - return EFI_INVALID_PARAMETER; + Status =3D BoardDescProtocol->BoardDescI2cGet (BoardDescProtocol, &Desc); + if (EFI_ERROR (Status)) { + return Status; } =20 /* Initialize enabled chips */ - for (Index =3D 0; Index < PcdGetSize (PcdI2cControllersEnabled); Index++= ) { - if (!MVHW_DEV_ENABLED (I2c, Index)) { - DEBUG ((DEBUG_ERROR, "Skip I2c chip %d\n", Index)); - continue; - } - + for (Index =3D 0; Index < Desc->I2cDevCount; Index++) { Status =3D MvI2cInitialiseController( ImageHandle, SystemTable, - Desc->I2cBaseAddresses[Index] + Desc[Index].SoC->I2cBaseAddress ); if (EFI_ERROR(Status)) return Status; } =20 + BoardDescProtocol->BoardDescFree (Desc); + return EFI_SUCCESS; } =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 08:19:34 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1529362844444378.5752234490303; Mon, 18 Jun 2018 16:00:44 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 339082110A3ED; Mon, 18 Jun 2018 15:59:35 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 494A621109FFE for ; Mon, 18 Jun 2018 15:59:33 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id i15-v6so27174618lfc.2 for ; Mon, 18 Jun 2018 15:59:33 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id h136-v6sm3020754lfe.23.2018.06.18.15.59.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Jun 2018 15:59:30 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8a8idFuSEi/1mQFoRZV7gkYZt3eZJQlJAfvzyckuHRc=; b=TnvXjepYwf9nBmqyRSuHtQ3GKdRWWPJYc5R4OOrW3m7ov5jicaQKblDrbsxbct/GdH qNLivWL+z2ZJ8e+D5H7Ql5ZXiRllOa2X/XVDnZBNxyzFRvoHe2i4yq3oMzthAS7x3hTQ sXjSTkUGROdzTRtvqSCNCR10hstxy9c+8KdVa0eQ+f1XihGw8mrYn2BreNbiyrk3nuu6 waS4JPJDb04U2MZsywIp5IMO2h7ag06G35sDSDSXlBwgI1xE55hN6mP1aslKaSg0E1ou o2LcqbnZis9NrBeFVewvl8n5H5ZGeXFZoTAggsfvEB9ptIEB0V1jw7PiAwAoRqi8MYMa B/Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8a8idFuSEi/1mQFoRZV7gkYZt3eZJQlJAfvzyckuHRc=; b=GWcJWgC1nvWVwuUtOP8E0/fr4Nzl/IRNv+7dRkjFBnVhteYubEPNBxgxapSX71wTsT jbbX4b+dEv51oxW5JLpI1vWSv+5jGiNEAY8PcdzcLQglMb86gdTtkMku2CmzufzHend5 zcWNzb2SJNHmC4dNMPLlZtX/cf87jdXV41vB70YafLl0/lrVxaw9fis0NMZl5b5AZ4LO qOT2nS1GWvEl+/5zyBJDibJCLthZTQ57F9Wtxg0OPT5p6JBCyoALU6S+AbVrW3xG7ezN gV/UdZ173/95TBHh6F845kXP89ZF+I6TXT2tiG3FxNu9OrU0kK5gSvPkP2cHKA17Vcha 4gxA== X-Gm-Message-State: APt69E0ccrE3fBo2G49TeoYMsw3kCFDOP0+nZz9NZ7WuIbZrFgvUxoLp FUC94Nuo58o4qp8W/TL26e4ASrhX39A= X-Google-Smtp-Source: ADUXVKIgCl7u7UVY6Erkubf82qWR7RmNu2zYBp/l9AqcFc9xNIsEBDeE4MhSLNCDPRE6puGi5uTRMA== X-Received: by 2002:a19:8f55:: with SMTP id r82-v6mr2614358lfd.67.1529362771218; Mon, 18 Jun 2018 15:59:31 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Tue, 19 Jun 2018 00:58:44 +0200 Message-Id: <1529362724-9244-26-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529362724-9244-1-git-send-email-mw@semihalf.com> References: <1529362724-9244-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v3 25/25] Marvell/Drivers: MvPhyDxe: Remove MvHwDescLib.h dependency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, nadavh@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Finally, after switching to new MV_BOARD_DESC solution in all drivers, stop using MvHwDescLib.h by its last user and safely remove this header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm Reviewed-by's and corrected double parentheses in one of the headers. --- Silicon/Marvell/Include/Library/MvHwDescLib.h | 70 -------------------- Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c | 4 +- 2 files changed, 2 insertions(+), 72 deletions(-) delete mode 100644 Silicon/Marvell/Include/Library/MvHwDescLib.h diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvel= l/Include/Library/MvHwDescLib.h deleted file mode 100644 index 0de435d..0000000 --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************= ******* -Copyright (C) 2017 Marvell International Ltd. - -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute a= nd/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modific= ation, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -* Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -**************************************************************************= *****/ - -#ifndef __MVHWDESCLIB_H__ -#define __MVHWDESCLIB_H__ - -// -// Helper macros -// - -// Check if device is enabled - it expects PCD to be read to 'Device= Table' array -#define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) - -// -// I2C devices description template definition -// -#define MVHW_MAX_I2C_DEVS 4 - -typedef struct { - UINT8 I2cDevCount; - UINTN I2cBaseAddresses[MVHW_MAX_I2C_DEVS]; -} MVHW_I2C_DESC; - -// -// Platform description of I2C devices -// -#define MVHW_CP0_I2C0_BASE 0xF2701000 -#define MVHW_CP0_I2C1_BASE 0xF2701100 -#define MVHW_CP1_I2C0_BASE 0xF4701000 -#define MVHW_CP1_I2C1_BASE 0xF4701100 - -#define DECLARE_A7K8K_I2C_TEMPLATE \ -STATIC \ -MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ - 4,\ - { MVHW_CP0_I2C0_BASE, MVHW_CP0_I2C1_BASE, MVHW_CP1_I2C0_BASE, MVHW_CP1_I= 2C1_BASE }\ -} - -#endif /* __MVHWDESCLIB_H__ */ diff --git a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c b/Silicon/Marv= ell/Drivers/Net/MvPhyDxe/MvPhyDxe.c index dd2edae..9be0489 100644 --- a/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c +++ b/Silicon/Marvell/Drivers/Net/MvPhyDxe/MvPhyDxe.c @@ -41,7 +41,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include #include #include #include @@ -380,7 +379,8 @@ MvPhyInit ( MdioIndex =3D Phy2MdioController[PhyIndex]; =20 /* Verify correctness of PHY <-> MDIO assignment */ - if (!MVHW_DEV_ENABLED (Mdio, MdioIndex) || MdioIndex >=3D Mdio->Controll= erCount) { + if ((MdioDeviceTable[MdioIndex] =3D=3D 0) || + (MdioIndex >=3D Mdio->ControllerCount)) { DEBUG ((DEBUG_ERROR, "MvPhyDxe: Incorrect Mdio controller assignment f= or PHY#%d", PhyIndex)); return EFI_INVALID_PARAMETER; } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel