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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id r11-v6sm1612908ljg.37.2018.05.09.06.51.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 May 2018 06:51:35 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HiDJAWV+dzizs17DLoq2OZA+YJgKDctdwHCMxP6F4+w=; b=1yp6f+sGZhmuHwG/syxGeAMGKabPj4BtdemBE6qxPBMlOGCA48IUdhJGjEbc5nUQYz MXBL6t1j4Mvl3pcZnkP8JKzr2ub9/fESs6jWwFytpsj7YBtUP2NbLLHzFNQW+QDWGuf/ tAUEhu1PSQ8s4oCXz4aN5yfrlm/n6f4T0N0lxys7pqLCsFttzIxHLXvIC9nCNBuDREwj PVaG0D932QGomHibKACIED19nIIVcnwAZ1FJHJp8Wn9ipj23CZ3Jpdh9mUbgx+okrJiN SPcwjulJskLfo5fYrk+LPBqG7C3gLtBIgSxe8VDVBXownDURRJHiWnhm5iSaAwYaSV6h o8xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HiDJAWV+dzizs17DLoq2OZA+YJgKDctdwHCMxP6F4+w=; b=XKAmt/jDs7bqSNdCpaiAjl/mYc68dl5v02s4SCjlLPNW9AjZGcmnYAGaOK44QtdUse gPtX+WhAzL1NntKn4+TbNm4hj+WbV0+sMVvi1i/MohhWlqhouo3qg1nxLatfHk2LBfxd ZdsfzH/Msx8Bx+EUzWmifbuD0867TWbVUD08KO3DPx84OxLV5DoFoaxEI81ECdxQnrT5 2t7Ch3HQY3dD9IjE0K08VDMZ7Y2IzC94mNnN2FdLLIXtaJS6FH+CIzmtuka2EI0FDlvG vQR1W68YKVefEzCGJ1hEeh4F3pNSlVCo8YcJX8z/3D4jFdrbkjeAVfOKw1CrVQf69CXd wSYQ== X-Gm-Message-State: ALQs6tDYef2GRtkNQIBxsk1YHA6cmcCjKtKgBOrXkmGLsF9cwJ2CYXW0 N1d0H62lJImvrWcNSbIm3LQSx0dBgM0= X-Google-Smtp-Source: AB8JxZrgRTmUeQOzTgsOzi1sFu5M4FRXacemBzpOrIAAXRxxRkDdzgGW5SsxSSi67af/K9pe1ZCoBg== X-Received: by 2002:a2e:7c02:: with SMTP id x2-v6mr32248605ljc.96.1525873896148; Wed, 09 May 2018 06:51:36 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 9 May 2018 15:51:08 +0200 Message-Id: <1525873871-799-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1525873871-799-1-git-send-email-mw@semihalf.com> References: <1525873871-799-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH v2 1/4] Marvell/Armada7k8k: Remove Intel BDS dependency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile is no longer needed due to usage of generic BDS and its presence results in build error. Remove it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index cd58107..a147b6e 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -236,7 +236,6 @@ =20 # Required for Intel BDS gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x0= 4, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, = 0xD1 } =20 # ARM Generic Interrupt Controller gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1525873903618858.8121906398289; Wed, 9 May 2018 06:51:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C2D7B2096AEEB; Wed, 9 May 2018 06:51:40 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 67E8D2096AEE0 for ; Wed, 9 May 2018 06:51:39 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id m18-v6so51082924lfb.0 for ; Wed, 09 May 2018 06:51:39 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r11-v6sm1612908ljg.37.2018.05.09.06.51.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 May 2018 06:51:36 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QUTraSXSI8nRqakejt/176DUpwUTGlyMiHYqnZYFXNY=; b=OvagEmUxUJK1tzPWJ6QLl9Jl2eEbHR80qqvfNHl90Ly9fb3rj8K1/2hvQcIXfFy0qZ wmMO207gSB5rlttLhCXY5JH37JZjHTqzP9+nPvVAK+0p8tz9/Om1M24ENAlUKrt3RkXl uU/EUoUkwm8JwXVriLl/U4ulcF8RC1n/M0otkvNSYtf80wOfr3v63Df29qodeGeF+yX2 n3AsthMWj1TtNfG2FAqX/IAo3pB84MdLKPTFG8KfnCz5nRMtAXgFFxvGD6OF0qA+O8Qp bDUHPPXyPApKq8SDE113O4WJpFedMszfLawQPoy6Wo9p3h3n6XB6v0muy2GaeTFECE7Z jh5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QUTraSXSI8nRqakejt/176DUpwUTGlyMiHYqnZYFXNY=; b=pM1MlLZ1jLpBeaBqwbH7EnlmKE+4BWibS/SysTzReKZvCqCqGkI6H8rivZVdGCZVD0 NqXUnNYZjl/f6pdgP0vjssDwkn4+3KqTGz0eR62fqEWk2cXfGnQ45yoF8e1ev8lxvpfl ZTOwaIfsM2SOmIv2m7N+pwrtj7BKva85XaPlQfOaTenZ2r2AA7xbrH854+F2WqxZw5oy h50egjiffbB3DpkODvc198VM41un+xDMDmMmjnnQ0dmdbvhupMfG8Hn7TbSmHmjVtlmr 1uegCgS4NecTPu0EWsYZ6usNoAsfsyBa+PsVWwKx0GNPwWA5ryDaQHXtzp+Jcq2RcPqc GgTA== X-Gm-Message-State: ALQs6tDNEbhGj79FwExrnpzhqpbfPSE/4TshOIu5iPqlO1we8VLUFE7m UqcA+CUWMVfsyiPwYqnHclB35QhU3t4= X-Google-Smtp-Source: AB8JxZrzsYY6+9e2tNiLD90JZ652n6b5phhOdrcdMuTmcoHkxMyViDwhdSvxnHCEcLQYSqv8yypv9w== X-Received: by 2002:a2e:c41:: with SMTP id o1-v6mr30335738ljd.87.1525873897279; Wed, 09 May 2018 06:51:37 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 9 May 2018 15:51:09 +0200 Message-Id: <1525873871-799-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1525873871-799-1-git-send-email-mw@semihalf.com> References: <1525873871-799-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH v2 2/4] Marvell/Armada70x0Db: Use more generic output fd file name X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Unification of output file name will ease handling build scripts (e.g. for CI purpose) when multiple board support will be added. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Platform/Marv= ell/Armada70x0Db/Armada70x0Db.fdf index befb107..e165d90 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf @@ -24,7 +24,7 @@ # ##########################################################################= ###### =20 -[FD.Armada70x0Db_EFI] +[FD.Armada_EFI] BaseAddress =3D 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The ba= se address of the Firmware in NOR Flash. Size =3D 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The si= ze in bytes of the FLASH Device ErasePolarity =3D 1 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1525873906901201.761199740464; Wed, 9 May 2018 06:51:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EAD642096AEEE; Wed, 9 May 2018 06:51:42 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DC05C2096AEEE for ; Wed, 9 May 2018 06:51:40 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id o123-v6so51059886lfe.8 for ; Wed, 09 May 2018 06:51:40 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r11-v6sm1612908ljg.37.2018.05.09.06.51.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 May 2018 06:51:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4OMW3jk8gGERHMP0oomRmu8dlbffx+ZHqbrZlp5ULr8=; b=a1YQ2xBHHuKq8hHKGFCOm80JTbZMB4kV3ftg7Osrt6Bx3S0ogUfQeaDDVAuKWDhH0O uUxPY8DvC1kPblYCunwqBBPIDJN0Xk2ZUG/7dEsfAdQ8fLdp+mMaVfu7+lrZ+7m27aV7 azEtWyWGpyqF9U70i0AAxaCpQ3P9eDnRYdORHqTSwAhVbsN+FGWUprYYRkG/5WHprJ81 YoM9Coj1J6PlE5IbV8m6l82IJijkip7M3Jt4kRzta0R+Q7tWuSq1sp8vJHXbYi56iKIo YTUQZE87N4ykOGZ1XvIPJwEfNYsqMCgMqIuKWueNBOK/tSaxBSEojERym4DJuHGB4ogI wxSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4OMW3jk8gGERHMP0oomRmu8dlbffx+ZHqbrZlp5ULr8=; b=jkgpQx3G+F9zW8DH4rvF558f89//yTOHlf1ysCLVPQ/5xX6gmjCDtZ+jsOhkF8wmbo 6s06Ux0NNQA31kV3ZtJg4vwOIgL5TPMpXD5r8b3fRTxr8O0QsVasxyDSEwPffki2Ln2Z SFzqApdNBC+R/6WhdajeEhb21dyAirDHsnMvkc6BHkb9IeGgHJCmnWZAl9UtdQ0ZfUsf bjyoyxhMWuXqS6dl00CK1rBJwT4uFu5KGIOA5NLYWYAXq3jITeHm8+QTIah8tp640DE0 4+Fwcj4Liciz0hoxaMqeUS5FskB8y0uG0zU94zR6gVFIDu6gTYH7DokA6eRi5qRC9I01 iDMg== X-Gm-Message-State: ALQs6tAGWY7H2rr0c2m++CLnzBNrUHrxzCkv1oksEhgOWRFT0eRh7wuB LZDLqts+dchDY46QksVHgNa/n/WZu44= X-Google-Smtp-Source: AB8JxZrx0o+Ns8vN/Z3LCvHZqyNSiTuWCnlsU9ZnBvmQn11Cujs+zVVL7bHhejqeQdAWbQygpwAMuQ== X-Received: by 2002:a2e:804c:: with SMTP id p12-v6mr32111446ljg.129.1525873898566; Wed, 09 May 2018 06:51:38 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 9 May 2018 15:51:10 +0200 Message-Id: <1525873871-799-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1525873871-799-1-git-send-email-mw@semihalf.com> References: <1525873871-799-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH v2 3/4] Marvell/Armada7k8k: Add basic sample at reset library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, Igal Liberman MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Igal Liberman The sample at reset library adds the following functionalities: - MvSARGetCpuFreq - Get the CPU frequency - MvSARGetDramFreq - Get the DRAM frequency - MvSARGetPcieClkDirection - Determine the PCIe clock direction for two types specified in CP110 HW block. It will be needed for proper configuration during the PCIE SerDes training. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Igal Liberman Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSa= mpleAtResetLib.c | 111 ++++++++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSa= mpleAtResetLib.h | 109 +++++++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7k8kSa= mpleAtResetLib.inf | 54 ++++++++++ Silicon/Marvell/Include/Library/SampleAtResetLib.h = | 57 ++++++++++ Silicon/Marvell/Marvell.dec = | 3 + 5 files changed, 334 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/= Armada7k8kSampleAtResetLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8= kSampleAtResetLib/Armada7k8kSampleAtResetLib.c new file mode 100644 index 0000000..3ebff56 --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7= k8kSampleAtResetLib.c @@ -0,0 +1,111 @@ +/*************************************************************************= ******* +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +Glossary - abbreviations used in Marvell SampleAtReset library implementat= ion: +AP - Application Processor hardware block (Armada 7k8k incorporates AP806) +CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +SAR - Sample At Reset + +**************************************************************************= *****/ + +#include + +#include +#include +#include + +#include "Armada7k8kSampleAtResetLib.h" + +UINT32 +EFIAPI +SampleAtResetGetCpuFrequency ( + VOID + ) +{ + CONST PLL_FREQUENCY_DESCRIPTION *PllFrequencies; + UINT32 ClockValue; + UINT32 Index; + + ClockValue =3D MmioAnd32 (AP806_SAR_BASE, SAR_CLOCK_FREQUENCY_MODE_MASK); + + PllFrequencies =3D PllFrequencyTable; + + for (Index =3D 0; Index < SAR_MAX_OPTIONS; Index++, PllFrequencies++) { + if (PllFrequencies->ClockingOption =3D=3D ClockValue) { + break; + } + } + + return PllFrequencies->CpuFrequency; +} + +UINT32 +EFIAPI +SampleAtResetGetDramFrequency ( + VOID + ) +{ + CONST PLL_FREQUENCY_DESCRIPTION *PllFrequencies; + UINT32 ClockValue; + UINT32 Index; + + ClockValue =3D MmioAnd32 (AP806_SAR_BASE, SAR_CLOCK_FREQUENCY_MODE_MASK); + + PllFrequencies =3D PllFrequencyTable; + + for (Index =3D 0; Index < SAR_MAX_OPTIONS; Index++, PllFrequencies++) { + if (PllFrequencies->ClockingOption =3D=3D ClockValue) { + break; + } + } + + return PllFrequencies->DdrFrequency; +} + +UINT32 +EFIAPI +SampleAtResetGetPcieClockDirection ( + IN UINT32 CpIndex, + IN UINT32 PcieIndex + ) +{ + UINT32 ClockDirection; + + ASSERT (CpIndex < MAX_CP_COUNT); + ASSERT (PcieIndex < MAX_PCIE_CLK_TYPE_COUNT); + + ClockDirection =3D MmioAnd32 (CP110_SAR_BASE (CpIndex), + PcieClockMask[CpIndex][PcieIndex] >> + PcieClockOffset[CpIndex][PcieIndex]); + + return ClockDirection; +} diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/= Armada7k8kSampleAtResetLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8= kSampleAtResetLib/Armada7k8kSampleAtResetLib.h new file mode 100644 index 0000000..323399f --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7= k8kSampleAtResetLib.h @@ -0,0 +1,109 @@ +/*************************************************************************= ******* +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +Glossary - abbreviations used in Marvell SampleAtReset library implementat= ion: +AP - Application Processor hardware block (Armada 7k8k incorporates AP806) +CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +SAR - Sample At Reset + +**************************************************************************= *****/ + +#define SAR_MAX_OPTIONS 16 + +#define AP806_SAR_BASE 0xf06f8200 +#define SAR_CLOCK_FREQUENCY_MODE_MASK 0x1f + +#define CP110_SAR_BASE(_CpIndex) (0xf2000000 + (0x2000000 * (_CpIndex)) += 0x400200) + +#define MAX_CP_COUNT 2 +#define MAX_PCIE_CLK_TYPE_COUNT 2 + +#define CP0_PCIE0_CLK_OFFSET 2 +#define CP0_PCIE1_CLK_OFFSET 3 +#define CP1_PCIE0_CLK_OFFSET 0 +#define CP1_PCIE1_CLK_OFFSET 1 +#define CP0_PCIE0_CLK_MASK (1 << CP0_PCIE0_CLK_OFFSET) +#define CP0_PCIE1_CLK_MASK (1 << CP0_PCIE1_CLK_OFFSET) +#define CP1_PCIE0_CLK_MASK (1 << CP1_PCIE0_CLK_OFFSET) +#define CP1_PCIE1_CLK_MASK (1 << CP1_PCIE1_CLK_OFFSET) + +typedef enum { + CPU_2000_DDR_1200_RCLK_1200 =3D 0x0, + CPU_2000_DDR_1050_RCLK_1050 =3D 0x1, + CPU_1600_DDR_800_RCLK_800 =3D 0x4, + CPU_1800_DDR_1200_RCLK_1200 =3D 0x6, + CPU_1800_DDR_1050_RCLK_1050 =3D 0x7, + CPU_1600_DDR_1050_RCLK_1050 =3D 0x0d, + CPU_1000_DDR_650_RCLK_650 =3D 0x13, + CPU_1300_DDR_800_RCLK_800 =3D 0x14, + CPU_1300_DDR_650_RCLK_650 =3D 0x17, + CPU_1200_DDR_800_RCLK_800 =3D 0x19, + CPU_1400_DDR_800_RCLK_800 =3D 0x1a, + CPU_600_DDR_800_RCLK_800 =3D 0x1b, + CPU_800_DDR_800_RCLK_800 =3D 0x1c, + CPU_1000_DDR_800_RCLK_800 =3D 0x1d, +} CLOCKING_OPTIONS; + +typedef struct { + UINT32 CpuFrequency; + UINT32 DdrFrequency; + UINT32 RingFrequency; + CLOCKING_OPTIONS ClockingOption; +} PLL_FREQUENCY_DESCRIPTION; + +STATIC CONST PLL_FREQUENCY_DESCRIPTION PllFrequencyTable[SAR_MAX_OPTIONS] = =3D { + /* CPU DDR Ring [MHz] */ + {2000, 1200, 1200, CPU_2000_DDR_1200_RCLK_1200}, + {2000, 1050, 1050, CPU_2000_DDR_1050_RCLK_1050}, + {1800, 1200, 1200, CPU_1800_DDR_1200_RCLK_1200}, + {1800, 1050, 1050, CPU_1800_DDR_1050_RCLK_1050}, + {1600, 1050, 1050, CPU_1600_DDR_1050_RCLK_1050}, + {1300, 800 , 800 , CPU_1300_DDR_800_RCLK_800}, + {1300, 650 , 650 , CPU_1300_DDR_650_RCLK_650}, + {1600, 800 , 800 , CPU_1600_DDR_800_RCLK_800}, + {1000, 650 , 650 , CPU_1000_DDR_650_RCLK_650}, + {1200, 800 , 800 , CPU_1200_DDR_800_RCLK_800}, + {1400, 800 , 800 , CPU_1400_DDR_800_RCLK_800}, + {600 , 800 , 800 , CPU_600_DDR_800_RCLK_800}, + {800 , 800 , 800 , CPU_800_DDR_800_RCLK_800}, + {1000, 800 , 800 , CPU_1000_DDR_800_RCLK_800} +}; + +STATIC CONST UINT32 PcieClockMask[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT] = =3D { + {CP0_PCIE0_CLK_MASK, CP0_PCIE1_CLK_MASK}, + {CP1_PCIE0_CLK_MASK, CP1_PCIE1_CLK_MASK} +}; + +STATIC CONST UINT32 PcieClockOffset[MAX_CP_COUNT][MAX_PCIE_CLK_TYPE_COUNT]= =3D { + {CP0_PCIE0_CLK_OFFSET, CP0_PCIE1_CLK_OFFSET}, + {CP1_PCIE0_CLK_OFFSET, CP1_PCIE1_CLK_OFFSET} +}; diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/= Armada7k8kSampleAtResetLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7= k8kSampleAtResetLib/Armada7k8kSampleAtResetLib.inf new file mode 100644 index 0000000..5a21cde --- /dev/null +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtResetLib/Armada7= k8kSampleAtResetLib.inf @@ -0,0 +1,54 @@ +# Copyright (C) 2018 Marvell International Ltd. +# +# Marvell BSD License Option +# +# If you received this File from Marvell, you may opt to use, redistribute= and/or +# modify this File under the following licensing terms. +# Redistribution and use in source and binary forms, with or without modif= ication, +# are permitted provided that the following conditions are met: +# +# * Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# * Neither the name of Marvell nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IM= PLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL D= AMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVI= CES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF= THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D Armada7k8kSampleAtResetLib + FILE_GUID =3D 03e022c7-9bd7-4608-aa21-379deaac2430 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SampleAtResetLib + +[Sources] + Armada7k8kSampleAtResetLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + DebugLib + IoLib + +[Depex] + TRUE diff --git a/Silicon/Marvell/Include/Library/SampleAtResetLib.h b/Silicon/M= arvell/Include/Library/SampleAtResetLib.h new file mode 100644 index 0000000..1be3a6a --- /dev/null +++ b/Silicon/Marvell/Include/Library/SampleAtResetLib.h @@ -0,0 +1,57 @@ +/*************************************************************************= ******* +Copyright (C) 2018 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must Retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ + +#ifndef __SAMPLE_AT_RESET_LIB_H__ +#define __SAMPLE_AT_RESET_LIB_H__ + +UINT32 +EFIAPI +SampleAtResetGetCpuFrequency ( + VOID + ); + +UINT32 +EFIAPI +SampleAtResetGetDramFrequency ( + VOID + ); + +UINT32 +EFIAPI +SampleAtResetGetPcieClockDirection ( + IN UINT32 CpIndex, + IN UINT32 PcieIndex + ); + +#endif /* __SAMPLE_AT_RESET_LIB_H__ */ diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 2eb6238..be74b4e 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -59,6 +59,9 @@ gMarvellFvbDxeGuid =3D { 0x42903750, 0x7e61, 0x4aaf, { 0x83, 0x29, 0xbf,= 0x42, 0x36, 0x4e, 0x24, 0x85 } } gMarvellSpiFlashDxeGuid =3D { 0x49d7fb74, 0x306d, 0x42bd, { 0x94, 0xc8, = 0xc0, 0xc5, 0x4b, 0x18, 0x1d, 0xd7 } } =20 +[LibraryClasses] + SampleAtResetLib|Include/Library/SampleAtResetLib.h + [Protocols] # installed as a protocol by PlatInitDxe to force ordering between DXE d= rivers # that depend on the lowlevel platform initialization having been comple= ted --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Thu May 2 00:16:58 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1525873910510751.7668525075053; Wed, 9 May 2018 06:51:50 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 212D22096AEF8; Wed, 9 May 2018 06:51:44 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 173722096AEE1 for ; Wed, 9 May 2018 06:51:42 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id y72-v6so37309332lfd.2 for ; Wed, 09 May 2018 06:51:42 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id r11-v6sm1612908ljg.37.2018.05.09.06.51.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 09 May 2018 06:51:39 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=njZe5aH6uTYG3Rni+5qQ56SAREFAGXoIjviLCJDq1So=; b=BgLrZw1zyL7cLITro6k7fHg37PzB5MYcrAhGhrReA1bywaolml2xBIItKwnp/KHfz8 DGTvIq73gXjTbNZp/tn+AWamKNoaXm7NWIM7fDyFUfOPcPTIuntdb3PHkL1urCi7Vcvq 2QXXHwbDGPHZUenUzZRBDeBH18frCFZkXUlbYleCwe1nIA3H6sd4efVpuzZ1Rl4Gmlvb QE0VHH10nPXJt9Zt4CV4vfm88xNyTbUbO+1R4k6DQPMtj6jxG22i7hLQrwUwLJg8XeD0 D6Y2X4Gi7vYQwdD9C94DkhCCxVvbD5nC0fhkEQOCQOhjoqmbptWDHt8JIrx4q+fAuEC8 CrMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=njZe5aH6uTYG3Rni+5qQ56SAREFAGXoIjviLCJDq1So=; b=IqGm89oydMDeTiSVfFsRI9ZDWhZVrF76J9fqEqTTORVHWBN3orPwdeXdwfTFydE/bo l4q0OH7U47083imSzpWun0fUQ71LaZyoO2tUGc0XrkFaIXNY5zs3Ila0IY3o8iqMQCqa K4omr0Ys4YiXCoOdsLDtjEcwEXR19/JKQ58Xaq845GIl5m2grdIvDjmc75Hiagc8o/8g byV0iLaHZ7TvzWkwpQzN/mOg9h8ERa5NLT8SwT+AIQsBjVBeX7ePPJROgaB/TE2Khh2y 8C6RmrlkcpGZbkus/ovYHnudWsk7vdgddWeu5IgmwTP8EoNInd40upYAd7eX5Y/iy3E5 qSCQ== X-Gm-Message-State: ALQs6tBWrnXLmeXr7JPMQgcRrunUHVe2n0g1AVHlTEgf3LUezSIbci8R VX3I4Ou9pX8E0iCFTud6en7mM4NaFB0= X-Google-Smtp-Source: AB8JxZplMj+MelYL57dLJ1Z97bCe574LLH+Sxo4e3pFndMhN4DH0zW+d5xN9pjV0CB+3CV6IQEJXkQ== X-Received: by 2002:a2e:760a:: with SMTP id r10-v6mr30310165ljc.144.1525873899882; Wed, 09 May 2018 06:51:39 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 9 May 2018 15:51:11 +0200 Message-Id: <1525873871-799-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1525873871-799-1-git-send-email-mw@semihalf.com> References: <1525873871-799-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms PATCH v2 4/4] Marvell/Library: ComPhyLib: Fix configuration for PCIE x4 and x2 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, jaz@semihalf.com, leif.lindholm@linaro.org, Evan Wang MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Evan Wang PCIE clock direction (input/output) has implications on comphy settings. There are 2 PCIe clocks in CP110: - Ref clock 0 for lanes 1,2 and 3 - Ref clock 1 for lanes 4 and 5 A proper handling of above had to be added, using newly introduced sample at reset library class for Marvell SoCs. Other than that, update HPIPE settings and the reset sequence, which differ from one used in x1 link. This patch fixes PCIE x4 and x2 configuration, which helps to overcome link establishing issue for multi-lane end points. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Evan Wang Signed-off-by: Marcin Wojtas --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 + Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 216 +++++++++++++++----- Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 1 + Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 36 ++++ Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 + 5 files changed, 203 insertions(+), 52 deletions(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index a147b6e..4129742 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -36,6 +36,7 @@ ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf MppLib|Silicon/Marvell/Library/MppLib/MppLib.inf NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf + SampleAtResetLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSampleAtRe= setLib/Armada7k8kSampleAtResetLib.inf UtmiPhyLib|Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf =20 DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyCp110.c index 40a7b99..5c7e769 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -34,6 +34,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "ComPhyLib.h" #include +#include =20 #define SD_LANE_ADDR_WIDTH 0x1000 #define HPIPE_ADDR_OFFSET 0x800 @@ -42,6 +43,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define HPIPE_ADDR(base, Lane) (SD_ADDR(base, Lane) + HPIPE_ADDR_OFFS= ET) #define COMPHY_ADDR(base, Lane) (base + COMPHY_ADDR_LANE_WIDTH * Lane) =20 +#define CP110_PCIE_REF_CLK_TYPE0 0 +#define CP110_PCIE_REF_CLK_TYPE12 1 + DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; =20 /* @@ -99,11 +103,26 @@ COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] =3D { STATIC VOID ComPhyPcieRFUConfiguration ( + IN UINT32 Lane, + IN UINT32 PcieWidth, IN EFI_PHYSICAL_ADDRESS ComPhyAddr ) { UINT32 Mask, Data; =20 + /* Enable PCIe by4 and by2 */ + if (Lane =3D=3D 0) { + if (PcieWidth =3D=3D 4) { + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1, + COMMON_PHY_SD_CTRL1_PCIE_X4_EN, + COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK); + } else if (PcieWidth =3D=3D 2) { + RegSet (ComPhyAddr + COMMON_PHY_SD_CTRL1, + COMMON_PHY_SD_CTRL1_PCIE_X2_EN, + COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK); + } + } + /* RFU configurations - hard reset ComPhy */ Mask =3D COMMON_PHY_CFG1_PWR_UP_MASK; Data =3D 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; @@ -132,11 +151,14 @@ ComPhyPcieRFUConfiguration ( STATIC VOID ComPhyPciePhyConfiguration ( + IN UINT32 Lane, + IN UINT32 PcieWidth, + IN UINT32 PcieClk, IN EFI_PHYSICAL_ADDRESS ComPhyAddr, IN EFI_PHYSICAL_ADDRESS HpipeAddr ) { - UINT32 Mask, Data, PcieClk =3D 0; + UINT32 Mask, Data; =20 /* Set PIPE soft reset */ Mask =3D HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; @@ -156,13 +178,31 @@ ComPhyPciePhyConfiguration ( RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, Data, Mask); =20 /* Set PLL ready delay for 0x2 */ - RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, - 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET, - HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK); + Data =3D HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT; + Mask =3D HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; + if (PcieWidth !=3D 1) { + Data |=3D HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT | + HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT; + Mask |=3D HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK | + HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; + } + RegSet (HpipeAddr + HPIPE_CLK_SRC_LO_REG, Data, Mask); =20 /* Set PIPE mode interface to PCIe3 - 0x1 */ - RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, - 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET, HPIPE_CLK_SRC_HI_MODE_PIPE_M= ASK); + Data =3D HPIPE_CLK_SRC_HI_MODE_PIPE_EN; + Mask =3D HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; + if (PcieWidth !=3D 1) { + Mask |=3D HPIPE_CLK_SRC_HI_LANE_STRT_MASK | + HPIPE_CLK_SRC_HI_LANE_MASTER_MASK | + HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; + if (Lane =3D=3D 0) { + Data |=3D HPIPE_CLK_SRC_HI_LANE_STRT_EN | + HPIPE_CLK_SRC_HI_LANE_MASTER_EN; + } else if (Lane =3D=3D (PcieWidth - 1)) { + Data |=3D HPIPE_CLK_SRC_HI_LANE_BREAK_EN; + } + } + RegSet (HpipeAddr + HPIPE_CLK_SRC_HI_REG, Data, Mask); =20 /* Config update polarity equalization */ RegSet (HpipeAddr + HPIPE_LANE_EQ_CFG1_REG, @@ -172,19 +212,21 @@ ComPhyPciePhyConfiguration ( RegSet (HpipeAddr + HPIPE_DFE_CTRL_28_REG, 0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET, HPIPE_DFE_CTRL_28_PIPE4_MASK); =20 - /* Enable PIN clock 100M_125M */ - Mask =3D HPIPE_MISC_CLK100M_125M_MASK; - Data =3D 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; - /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock = */ - Mask |=3D HPIPE_MISC_TXDCLK_2X_MASK; - Data |=3D 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; + Mask =3D HPIPE_MISC_TXDCLK_2X_MASK; + Data =3D HPIPE_MISC_TXDCLK_2X_500MHZ; =20 /* Enable 500MHz Clock */ Mask |=3D HPIPE_MISC_CLK500_EN_MASK; Data |=3D 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; =20 if (PcieClk) { + /* + * Enable PIN clock 100M_125M + * Only if clock is output, configure the clock-source mux + */ + Mask |=3D HPIPE_MISC_CLK100M_125M_MASK; + Data |=3D HPIPE_MISC_CLK100M_125M_EN; /* Set reference clock comes from group 1 */ Mask |=3D HPIPE_MISC_REFCLK_SEL_MASK; Data |=3D 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; @@ -214,6 +256,13 @@ ComPhyPciePhyConfiguration ( Data |=3D 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; RegSet (HpipeAddr + HPIPE_PWR_PLL_REG, Data, Mask); =20 + /* Ref clock alignment */ + if (PcieWidth !=3D 1) { + RegSet (HpipeAddr + HPIPE_LANE_ALIGN_REG, + HPIPE_LANE_ALIGN_OFF, + HPIPE_LANE_ALIGN_OFF_MASK); + } + /* * Set the amount of time spent in the LoZ state - set * for 0x7 only if the PCIe clock is output @@ -396,7 +445,7 @@ ComPhyPcieSetAnalogParameters ( HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; Data =3D (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) | (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) | - (0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET); + (HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT); MmioAndThenOr32 (HpipeAddr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, ~Mask, Da= ta); =20 /* Set phy in root complex mode */ @@ -404,37 +453,82 @@ ComPhyPcieSetAnalogParameters ( } =20 STATIC -VOID -ComPhyPciePhyPowerUp ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr -) -{ - /* Release from PIPE soft reset */ - RegSet (HpipeAddr + HPIPE_RST_CLK_CTRL_REG, - 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET, - HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); - - /* Wait 15ms - for ComPhy calibration done */ - MicroSecondDelay (15000); - MemoryFence (); -} - -STATIC EFI_STATUS -ComPhyPcieCheckPll ( - IN EFI_PHYSICAL_ADDRESS HpipeAddr +ComPhyPciePhyPowerUp ( + IN UINT32 Lane, + IN UINT32 PcieWidth, + IN EFI_PHYSICAL_ADDRESS ComPhyBase, + IN EFI_PHYSICAL_ADDRESS HpipeBase ) { EFI_STATUS Status =3D EFI_SUCCESS; + UINT8 StartLane, EndLane, Loop; UINT32 Data; =20 - /* Read Lane status */ - Data =3D MmioRead32 (HpipeAddr + HPIPE_LANE_STATUS0_REG); - if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) =3D=3D 0) { - DEBUG((DEBUG_INFO, "ComPhy: Read from reg =3D %p - value =3D 0x%x\n", - HpipeAddr + HPIPE_LANE_STATUS0_REG, Data)); - DEBUG((DEBUG_INFO, "ComPhy: HPIPE_LANE_STATUS0_PCLK_EN_MASK is 0\n")); - Status =3D EFI_D_ERROR; + /* + * For PCIe by4 or by2 - release from reset only after finish to + * configure all lanes + */ + if ((PcieWidth =3D=3D 1) || (Lane =3D=3D (PcieWidth - 1))) { + if (PcieWidth !=3D 1) { + /* Allows writing to all lanes in one write */ + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1, + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE, + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); + StartLane =3D 0; + EndLane =3D PcieWidth; + + /* + * Release from PIPE soft reset + * for PCIe by4 or by2 - release from soft reset + * all lanes - can't use read modify write + */ + RegSet (HPIPE_ADDR (HpipeBase, 0) + HPIPE_RST_CLK_CTRL_REG, + HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 | HPIPE_RST_CLK_CTRL_MODE_RE= FDIV_4, + HPIPE_RST_CLK_CTRL_CLR_ALL_MASK); + } else { + StartLane =3D Lane; + EndLane =3D Lane + 1; + + /* + * Release from PIPE soft reset + * for PCIe by4 or by2 - release from soft reset + * all lanes + */ + RegSet (HPIPE_ADDR (HpipeBase, Lane) + HPIPE_RST_CLK_CTRL_REG, + HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE, + HPIPE_RST_CLK_CTRL_PIPE_RST_MASK); + } + + if (PcieWidth !=3D 1) { + /* Disable writing to all lanes with one write */ + RegSet (ComPhyBase + COMMON_PHY_SD_CTRL1, + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE, + COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK); + } + MemoryFence (); + + /* Wait 20ms until status of all lanes stabilize */ + MicroSecondDelay (20000); + + /* Make sure all lanes are UP */ + for (Loop =3D StartLane; Loop < EndLane; Loop++) { + Data =3D MmioRead32 (HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATU= S0_REG); + + if ((Data & HPIPE_LANE_STATUS0_PCLK_EN_MASK) =3D=3D 0) { + DEBUG ((DEBUG_ERROR, + "%a: Read from lane%d, reg =3D %p - value =3D 0x%x\n", + __FUNCTION__, + Loop, + HPIPE_ADDR (HpipeBase, Loop) + HPIPE_LANE_STATUS0_REG, + Data)); + DEBUG ((DEBUG_ERROR, + "%a: HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n", + __FUNCTION__)); + Status =3D EFI_D_ERROR; + break; + } + } } =20 return Status; @@ -443,8 +537,9 @@ ComPhyPcieCheckPll ( STATIC EFI_STATUS ComPhyPciePowerUp ( + IN UINT8 ChipId, IN UINT32 Lane, - IN UINT32 PcieBy4, + IN UINT32 PcieWidth, IN EFI_PHYSICAL_ADDRESS HpipeBase, IN EFI_PHYSICAL_ADDRESS ComPhyBase ) @@ -452,26 +547,36 @@ ComPhyPciePowerUp ( EFI_STATUS Status =3D EFI_SUCCESS; EFI_PHYSICAL_ADDRESS HpipeAddr =3D HPIPE_ADDR(HpipeBase, Lane); EFI_PHYSICAL_ADDRESS ComPhyAddr =3D COMPHY_ADDR(ComPhyBase, Lane); + UINT32 PcieClk; + + /* + * Obtain clock direction from sample-at-reset configuration. + * 4th and 5th SerDes lanes can belong only to PCIE Port1 and + * Port2, which use different clock type specifier than Port0. + */ + if (Lane =3D=3D 4 || Lane =3D=3D 5) { + PcieClk =3D SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF= _CLK_TYPE12); + } else { + PcieClk =3D SampleAtResetGetPcieClockDirection (ChipId, CP110_PCIE_REF= _CLK_TYPE0); + } + + DEBUG ((DEBUG_INFO, "%a: ChipId: %d PcieClk:%d\n", __FUNCTION__, ChipId,= PcieClk)); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPh= y\n")); =20 - ComPhyPcieRFUConfiguration (ComPhyAddr); + ComPhyPcieRFUConfiguration (Lane, PcieWidth, ComPhyAddr); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy configuration\n")); =20 - ComPhyPciePhyConfiguration (ComPhyAddr, HpipeAddr); + ComPhyPciePhyConfiguration (Lane, PcieWidth, PcieClk, ComPhyAddr, HpipeA= ddr); =20 DEBUG((DEBUG_INFO, "ComPhy: stage: Set analog paramters\n")); =20 ComPhyPcieSetAnalogParameters (HpipeAddr); =20 - DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); + DEBUG ((DEBUG_INFO, "%a: stage: ComPhy power up and check PLL\n", __FUNC= TION__)); =20 - ComPhyPciePhyPowerUp (HpipeAddr); - - DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); - - Status =3D ComPhyPcieCheckPll (HpipeAddr); + Status =3D ComPhyPciePhyPowerUp (Lane, PcieWidth, ComPhyBase, HpipeBase); =20 return Status; } @@ -1780,28 +1885,35 @@ ComPhyCp110Init ( COMPHY_MAP *PtrComPhyMap, *SerdesMap; EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr; UINT32 ComPhyMaxCount, Lane; - UINT32 PcieBy4 =3D 1; // Indicating if first 4 lanes set to PCIE + UINT32 PcieWidth =3D 0; + UINT8 ChipId; =20 ComPhyMaxCount =3D PtrChipCfg->LanesCount; ComPhyBaseAddr =3D PtrChipCfg->ComPhyBaseAddr; HpipeBaseAddr =3D PtrChipCfg->Hpipe3BaseAddr; SerdesMap =3D PtrChipCfg->MapData; + ChipId =3D PtrChipCfg->ChipId; =20 /* Config Comphy mux configuration */ ComPhyMuxCp110(PtrChipCfg, SerdesMap); =20 /* Check if the first 4 Lanes configured as By-4 */ for (Lane =3D 0, PtrComPhyMap =3D SerdesMap; Lane < 4; Lane++, PtrComPhy= Map++) { - if (PtrComPhyMap->Type !=3D COMPHY_TYPE_PCIE0) { - PcieBy4 =3D 0; + if (PtrComPhyMap->Type !=3D COMPHY_TYPE_PCIE0) break; - } + PcieWidth++; } =20 for (Lane =3D 0, PtrComPhyMap =3D SerdesMap; Lane < ComPhyMaxCount; Lane++, PtrComPhyMap++) { DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane)); DEBUG((DEBUG_INFO, "ComPhy: Serdes Type =3D 0x%x\n", PtrComPhyMap->Typ= e)); + + if (Lane >=3D 4) { + /* PCIe lanes above the first 4 lanes, can be only by1 */ + PcieWidth =3D 1; + } + switch (PtrComPhyMap->Type) { case COMPHY_TYPE_UNCONNECTED: continue; @@ -1810,7 +1922,7 @@ ComPhyCp110Init ( case COMPHY_TYPE_PCIE1: case COMPHY_TYPE_PCIE2: case COMPHY_TYPE_PCIE3: - Status =3D ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBas= eAddr); + Status =3D ComPhyPciePowerUp (ChipId, Lane, PcieWidth, HpipeBaseAddr= , ComPhyBaseAddr); break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.c index bf21dca..b03bc35 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -192,6 +192,7 @@ InitComPhyConfig ( ChipConfig->Hpipe3BaseAddr =3D Desc->ComPhyHpipe3BaseAddresses[Id]; ChipConfig->LanesCount =3D Desc->ComPhyLaneCount[Id]; ChipConfig->MuxBitCount =3D Desc->ComPhyMuxBitCount[Id]; + ChipConfig->ChipId =3D Id; =20 /* * Below macro contains variable name concatenation (used to form PCD's = name). diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvel= l/Library/ComPhyLib/ComPhyLib.h index 5899a4a..c675d74 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -252,14 +252,17 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. =20 #define HPIPE_LANE_ALIGN_REG 0x124 #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 +#define HPIPE_LANE_ALIGN_OFF (0x0 << HPIPE_LANE_ALIGN= _OFF_OFFSET) #define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN= _OFF_OFFSET) =20 #define HPIPE_MISC_REG 0x13C #define HPIPE_MISC_CLK100M_125M_OFFSET 4 +#define HPIPE_MISC_CLK100M_125M_EN (0x1 << HPIPE_MISC_CLK10= 0M_125M_OFFSET) #define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK10= 0M_125M_OFFSET) #define HPIPE_MISC_ICP_FORCE_OFFSET 5 #define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_F= ORCE_OFFSET) #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 +#define HPIPE_MISC_TXDCLK_2X_500MHZ (0x0 << HPIPE_MISC_TXDCL= K_2X_OFFSET) #define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCL= K_2X_OFFSET) #define HPIPE_MISC_CLK500_EN_OFFSET 7 #define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK50= 0_EN_OFFSET) @@ -476,30 +479,52 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 #define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_F= OM_ONLY_MODE_OFFFSET) #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_DEFAULT (0x1 << HPIPE_LANE_CFG_F= OM_PRESET_VECTOR_OFFSET) #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_F= OM_PRESET_VECTOR_OFFSET) =20 #define HPIPE_RST_CLK_CTRL_REG 0x704 +#define HPIPE_RST_CLK_CTRL_CLR_ALL_MASK MAX_UINT32 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 +#define HPIPE_RST_CLK_CTRL_PIPE_RST_DISABLE (0x0 << HPIPE_RST_CLK_CT= RL_PIPE_RST_OFFSET) #define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CT= RL_PIPE_RST_OFFSET) #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CT= RL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_8 (0x1 << HPIPE_RST_CLK_CT= RL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_WIDTH_16 (0x0 << HPIPE_RST_CLK_CT= RL_FIXED_PCLK_OFFSET) #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CT= RL_PIPE_WIDTH_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_OFFSET 4 +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_MASK (0x3 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_1 (0x0 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_2 (0x1 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_4 (0x2 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) +#define HPIPE_RST_CLK_CTRL_MODE_REFDIV_8 (0x3 << HPIPE_RST_CLK_CT= RL_MODE_REFDIV_OFFSET) #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CT= RL_CORE_FREQ_SEL_OFFSET) =20 #define HPIPE_CLK_SRC_LO_REG 0x70c +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_DEFAULT (0x1 << HPIPE_CLK_SRC_L= O_BUNDLE_PERIOD_SEL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO= _BUNDLE_PERIOD_SEL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_DEFAULT (0x1 << HPIPE_CLK_SRC= _LO_BUNDLE_PERIOD_SCALE_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO= _BUNDLE_PERIOD_SCALE_OFFSET) #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_DEFAULT (0x2 << HPIPE_CLK_SRC_LO= _PLL_RDY_DL_OFFSET) #define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO= _PLL_RDY_DL_OFFSET) =20 #define HPIPE_CLK_SRC_HI_REG 0x710 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 +#define HPIPE_CLK_SRC_HI_LANE_STRT_EN (0x1 << HPIPE_CLK_SRC_HI= _LANE_STRT_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI= _LANE_STRT_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 +#define HPIPE_CLK_SRC_HI_LANE_BREAK_EN (0x1 << HPIPE_CLK_SRC_HI= _LANE_BREAK_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI= _LANE_BREAK_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 +#define HPIPE_CLK_SRC_HI_LANE_MASTER_EN (0x1 << HPIPE_CLK_SRC_HI= _LANE_MASTER_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI= _LANE_MASTER_OFFSET) #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 +#define HPIPE_CLK_SRC_HI_MODE_PIPE_EN (0x1 << HPIPE_CLK_SRC_HI_M= ODE_PIPE_OFFSET) #define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI= _MODE_PIPE_OFFSET) =20 #define HPIPE_GLOBAL_MISC_CTRL 0x718 @@ -528,6 +553,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define COMMON_SELECTOR_PIPE_OFFSET 0x144 =20 #define COMMON_PHY_SD_CTRL1 0x148 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_ENABLE 0x0 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_WR_DISABLE 0x3210 +#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN (0x1 << COMMON_PHY_SD_CT= RL1_PCIE_X4_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CT= RL1_PCIE_X4_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN (0x1 << COMMON_PHY_SD_CT= RL1_PCIE_X2_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CT= RL1_PCIE_X2_EN_OFFSET) #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CT= RL1_RXAUI1_OFFSET) #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 @@ -594,6 +629,7 @@ struct _CHIP_COMPHY_CONFIG { COMPHY_CHIP_INIT Init; UINT32 LanesCount; UINT32 MuxBitCount; + UINT8 ChipId; }; =20 VOID diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marv= ell/Library/ComPhyLib/ComPhyLib.inf index a1584b4..ce0af54 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -50,6 +50,7 @@ DebugLib MemoryAllocationLib PcdLib + SampleAtResetLib IoLib =20 [Sources.common] --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel