From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1517991804225207.89243790943613; Wed, 7 Feb 2018 00:23:24 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BD1B221F833A8; Wed, 7 Feb 2018 00:17:38 -0800 (PST) Received: from mail-pf0-x241.google.com (mail-pf0-x241.google.com [IPv6:2607:f8b0:400e:c00::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B144121F0DA6F for ; Wed, 7 Feb 2018 00:17:37 -0800 (PST) Received: by mail-pf0-x241.google.com with SMTP id 17so22623pfw.11 for ; Wed, 07 Feb 2018 00:23:21 -0800 (PST) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id k127sm1984999pga.92.2018.02.07.00.23.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Feb 2018 00:23:19 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::241; helo=mail-pf0-x241.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bKYWOo0tckjmF2xq+B0jjREcXmK9GaQmqQ3Ats0fdMU=; b=c9JeZt88TbcAi7F28GRqMrubynGHQ1X56AnJJiP2XbBMJdy2DvDQqDI6eUFzz3EEFD 2XC5ChmhkRRMAMMVEaCtzlPwRq8Wfz0DIxM6u6AJLKWpFIInEYiroORVXXb5Vza1iWzx 7s6aWpP36B3fc3ez7+lccy+bWx3FUVFnInYgk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bKYWOo0tckjmF2xq+B0jjREcXmK9GaQmqQ3Ats0fdMU=; b=RbWtNZj3jFX14qU8C/gT+j/qiJy9DIAU6uSv2c4Q73JVgEMaWNrPpYYi09ygwLo9ph i52Q0kwy5wN+mmRFEjzRG8uZxXI6QIeDziqvMdNMdLz2pwzG8QGwosj8L5c2LI+fJDha Y7PpCowJB9dyMBoN7sKpbKGEIxIthVUHrh5bo44S0benKIOwclODatoZwqC2ohk10SMe sdofgPDmL1ft1ZHO766930YajQEfPX8jWSjx0wIdYhu7sOLdZ1KIeeGiVfLV5C4jw26N xjM2LtIB0o1wB2qb7gU2yLYaN5Qrq2dwYH2rnUvYIG05bJpF6Yzj3Z7t+lnTh1xrfsM+ GLNw== X-Gm-Message-State: APf1xPCHBqzItLW/soGZ5REn3PC6hxHw2HfSMxi5kjqj6ak8M4ApBY0D G6X4ySv7ojvnvclzu7Ursb0+tg== X-Google-Smtp-Source: AH8x225oMCDC4MBTQr95d6GqarRcHKSSssUdSeYwMRhdAriTqV6rRBLRQZ1Bn3ozbo8M9lb7+QJUzQ== X-Received: by 10.98.60.5 with SMTP id j5mr5218173pfa.217.1517991799703; Wed, 07 Feb 2018 00:23:19 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:35 +0800 Message-Id: <1517991769-5485-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 01/15] Hisilicon/D05: Move Madt definition to head file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Move definition of Madt struct to head file, so PPTT driver can include it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Ard Biesheuvel Reviewed-by: Graeme Gregory Reveiwed-by: Jeremy Linton --- Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h | 30 +++++++++++++= ++++++- Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc | 23 +------------= -- 2 files changed, 30 insertions(+), 23 deletions(-) diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Sili= con/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h index 808219a..ad73aa2 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h @@ -1,7 +1,7 @@ /** @file * * Copyright (c) 2011-2015, ARM Limited. All rights reserved. -* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015-2018, Hisilicon Limited. All rights reserved. * Copyright (c) 2015-2016, Linaro Limited. All rights reserved. * * This program and the accompanying materials @@ -20,6 +20,8 @@ #ifndef _HI1610_PLATFORM_H_ #define _HI1610_PLATFORM_H_ =20 +#include + // // ACPI table information used to initialize tables. // @@ -44,5 +46,31 @@ } =20 #define HI1616_WATCHDOG_COUNT 2 +#define HI1616_GIC_STRUCTURE_COUNT 64 + +#define HI1616_MPID_TA_BASE 0x10000 +#define HI1616_MPID_TB_BASE 0x30000 +#define HI1616_MPID_TA_2_BASE 0x50000 +#define HI1616_MPID_TB_2_BASE 0x70000 + +// Differs from Juno, we have another affinity level beyond cluster and co= re +#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (HI1616_MPID_TA_BASE | (= (ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (HI1616_MPID_TB_BASE | (= (ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (HI1616_MPID_TA_2_BASE= | ((ClusterId) << 8) | (CoreId)) +#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (HI1616_MPID_TB_2_BASE= | ((ClusterId) << 8) | (CoreId)) + +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[HI16= 16_GIC_STRUCTURE_COUNT]; + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[8]; +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () =20 #endif diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Silic= on/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc index 169ee72..54605a6 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc @@ -2,7 +2,7 @@ * Multiple APIC Description Table (MADT) * * Copyright (c) 2012 - 2014, ARM Limited. All rights reserved. -* Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved. * Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. * * This program and the accompanying materials @@ -27,27 +27,6 @@ #include #include "Hi1616Platform.h" =20 -// Differs from Juno, we have another affinity level beyond cluster and co= re -// 0x20000 is only for socket 0 -#define PLATFORM_GET_MPID_TA(ClusterId, CoreId) (0x10000 | ((ClusterId) = << 8) | (CoreId)) -#define PLATFORM_GET_MPID_TB(ClusterId, CoreId) (0x30000 | ((ClusterId) = << 8) | (CoreId)) -#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId) (0x50000 | ((ClusterId= ) << 8) | (CoreId)) -#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId) (0x70000 | ((ClusterId= ) << 8) | (CoreId)) - -// -// Multiple APIC Description Table -// -#pragma pack (1) - -typedef struct { - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; - EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[64]; - EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; - EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[8]; -} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE; - -#pragma pack () - EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D { { ARM_ACPI_HEADER ( --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 07 Feb 2018 00:23:32 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::242; helo=mail-pg0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4tvAtahBRQM/PPWrcKKAaxoubmDTacpz4tyj5A7o5Mk=; b=N9zXyvVAwAExxzfDE5fYfP2h+ksg9TOp75A1MWZEXoqsbUKK+nuiiaxfDlvvRgHQ0l zIuBcxePJb+D/sAf3n9Dpy+4sXhVmvFi03XfOhcU5SBVu122hdTwRlRr2D4XZIpoxyar WYKzbO71029rrhO3xxhvV/ic6Lu+Etb2kuKEQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; 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charset="utf-8" Add Processor Properties Topology Table, PPTT include Processor hierarchy node, Cache Type Structure and ID structure. PPTT is needed for lscpu command to show socket information correctly. https://bugs.linaro.org/show_bug.cgi?id=3D3206 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel Reviewed-by: Graeme Gregory Reveiwed-by: Jeremy Linton --- Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Silicon/Hisilicon/Hi1616/Pptt/Pptt.c | 529 ++++++++++++++++++++ Silicon/Hisilicon/Hi1616/Pptt/Pptt.h | 67 +++ Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf | 48 ++ 5 files changed, 646 insertions(+) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 77a89fd..710339c 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -506,6 +506,7 @@ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf =20 Silicon/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf + Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf =20 # diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 78ab0c8..97de4d2 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -241,6 +241,7 @@ READ_LOCK_STATUS =3D TRUE INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf =20 INF RuleOverride=3DACPITABLE Silicon/Hisilicon/Hi1616/D05AcpiTables/Acpi= TablesHi1616.inf + INF Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf =20 # diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c b/Silicon/Hisilicon/Hi161= 6/Pptt/Pptt.c new file mode 100644 index 0000000..4cdbb4f --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.c @@ -0,0 +1,529 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/ +* +**/ + +#include "Pptt.h" + +EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol =3D NULL; +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol =3D NULL; + +EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =3D + ARM_ACPI_HEADER ( + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_DESCRIPTION_HEADER, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ); + +EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] = =3D +{ + {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, PPTT_VENDOR_ID, 0, = 0, 0, 0, 0} +}; + +EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO]; + + +STATIC +VOID +InitCacheInfo ( + VOID + ) +{ + UINT8 Index; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes; + CSSELR_DATA CsselrData; + CCSIDR_DATA CcsidrData; + + for (Index =3D 0; Index < PPTT_CACHE_NO; Index++) { + CsselrData.Data =3D 0; + CcsidrData.Data =3D 0; + SetMem ( + &Type1Attributes, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES), + 0 + ); + + if (Index =3D=3D 0) { //L1I + CsselrData.Bits.InD =3D 1; + CsselrData.Bits.Level =3D 0; + Type1Attributes.CacheType =3D 1; + } else if (Index =3D=3D 1) { + Type1Attributes.CacheType =3D 0; + CsselrData.Bits.Level =3D Index - 1; + } else { + Type1Attributes.CacheType =3D 2; + CsselrData.Bits.Level =3D Index - 1; + } + + CcsidrData.Data =3D ReadCCSIDR (CsselrData.Data); + + if (CcsidrData.Bits.Wa =3D=3D 1) { + Type1Attributes.AllocationType =3D EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALL= OCATION_WRITE; + if (CcsidrData.Bits.Ra =3D=3D 1) { + Type1Attributes.AllocationType =3D EFI_ACPI_6_2_CACHE_ATTRIBUTES_A= LLOCATION_READ_WRITE; + } + } + + if (CcsidrData.Bits.Wt =3D=3D 1) { + Type1Attributes.WritePolicy =3D 1; + } + DEBUG ((DEBUG_INFO, + "[Acpi PPTT] Level =3D %x!CcsidrData =3D %x!\n", + CsselrData.Bits.Level, + CcsidrData.Data)); + + mPpttCacheType1[Index].Type =3D EFI_ACPI_6_2_PPTT_TYPE_CACHE; + mPpttCacheType1[Index].Length =3D sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_= CACHE); + mPpttCacheType1[Index].Reserved[0] =3D 0; + mPpttCacheType1[Index].Reserved[1] =3D 0; + mPpttCacheType1[Index].Flags.SizePropertyValid =3D 1; + mPpttCacheType1[Index].Flags.NumberOfSetsValid =3D 1; + mPpttCacheType1[Index].Flags.AssociativityValid =3D 1; + mPpttCacheType1[Index].Flags.AllocationTypeValid =3D 1; + mPpttCacheType1[Index].Flags.CacheTypeValid =3D 1; + mPpttCacheType1[Index].Flags.WritePolicyValid =3D 1; + mPpttCacheType1[Index].Flags.LineSizeValid =3D 1; + mPpttCacheType1[Index].Flags.Reserved =3D 0; + mPpttCacheType1[Index].NextLevelOfCache =3D 0; + + if (Index !=3D PPTT_CACHE_NO - 1) { + mPpttCacheType1[Index].NumberOfSets =3D (UINT16)CcsidrData.Bits.NumS= ets + 1; + mPpttCacheType1[Index].Associativity =3D (UINT16)CcsidrData.Bits.Ass= ociativity + 1; + mPpttCacheType1[Index].LineSize =3D (UINT16)( 1 << (CcsidrData.Bits.= LineSize + 4)); + mPpttCacheType1[Index].Size =3D mPpttCacheType1[Index].LineSize * = \ + mPpttCacheType1[Index].Associativity *= \ + mPpttCacheType1[Index].NumberOfSets; + CopyMem ( + &mPpttCacheType1[Index].Attributes, + &Type1Attributes, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES) + ); + } else { + // L3 cache + mPpttCacheType1[Index].Size =3D 0x1000000; // 16m + mPpttCacheType1[Index].NumberOfSets =3D 0x2000; + mPpttCacheType1[Index].Associativity =3D 0x10; // CacheAssociativi= ty16Way + SetMem ( + &mPpttCacheType1[Index].Attributes, + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES), + 0x0A + ); + mPpttCacheType1[Index].LineSize =3D 0x80; // 128byte + } + } +} + +STATIC +EFI_STATUS +AddCoreTable ( + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, + IN OUT UINT32 *PpttTableLengthRemain, + IN UINT32 Parent, + IN UINT32 ResourceNo, + IN UINT32 ProcessorId + ) +{ + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1; + UINT32 *PrivateResource; + UINT8 Index; + + if (*PpttTableLengthRemain < + (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) { + return EFI_OUT_OF_RESOURCES; + } + PpttType0 =3D (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTab= le + + PpttTable->Length); + PpttType0->Type =3D 0; + SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); + PpttType0->Flags.AcpiProcessorIdValid =3D EFI_ACPI_6_2_PPTT_PROCESSOR_ID= _VALID; + PpttType0->Parent=3D Parent; + PpttType0->AcpiProcessorId =3D ProcessorId; + PpttType0->NumberOfPrivateResources =3D ResourceNo; + PpttType0->Length =3D sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + + ResourceNo * 4; + + *PpttTableLengthRemain -=3D (UINTN)PpttType0->Length; + PpttTable->Length +=3D PpttType0->Length; + PrivateResource =3D (UINT32 *)((UINT8 *)PpttType0 + + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESS= OR)); + + // Add cache type structure + for (Index =3D 0; Index < ResourceNo; Index++, PrivateResource++) { + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE= )) { + return EFI_OUT_OF_RESOURCES; + } + *PrivateResource =3D PpttTable->Length; + PpttType1 =3D (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable= + + PpttTable->Length); + gBS->CopyMem ( + PpttType1, + &mPpttCacheType1[Index], + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE) + ); + *PpttTableLengthRemain -=3D PpttType1->Length; + PpttTable->Length +=3D PpttType1->Length; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +AddClusterTable ( + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, + IN OUT UINT32 *PpttTableLengthRemain, + IN UINT32 Parent, + IN UINT32 ResourceNo + ) +{ + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1; + UINT32 *PrivateResource; + + if ((*PpttTableLengthRemain) < + (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) { + return EFI_OUT_OF_RESOURCES; + } + PpttType0 =3D (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTab= le + + PpttTable->Length); + PpttType0->Type =3D 0; + SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); + PpttType0->Parent=3D Parent; + PpttType0->NumberOfPrivateResources =3D ResourceNo; + PpttType0->Length =3D sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + + ResourceNo * 4; + + *PpttTableLengthRemain -=3D PpttType0->Length; + PpttTable->Length +=3D PpttType0->Length; + PrivateResource =3D (UINT32 *)((UINT8 *)PpttType0 + + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESS= OR)); + + // Add cache type structure + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE))= { + return EFI_OUT_OF_RESOURCES; + } + *PrivateResource =3D PpttTable->Length; + PpttType1 =3D (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable + + PpttTable->Length); + gBS->CopyMem ( + PpttType1, + &mPpttCacheType1[2], + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE) + ); + *PpttTableLengthRemain -=3D PpttType1->Length; + PpttTable->Length +=3D PpttType1->Length; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +AddScclTable ( + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, + IN OUT UINT32 *PpttTableLengthRemain, + IN UINT32 Parent, + IN UINT32 ResourceNo + ) +{ + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1; + UINT32 *PrivateResource; + + if (*PpttTableLengthRemain < + (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) { + return EFI_OUT_OF_RESOURCES; + } + PpttType0 =3D (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTab= le + + PpttTable->Length); + PpttType0->Type =3D 0; + SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); + PpttType0->Parent=3D Parent; + PpttType0->NumberOfPrivateResources =3D ResourceNo; + PpttType0->Length =3D sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + + ResourceNo * 4; + + *PpttTableLengthRemain -=3D PpttType0->Length; + PpttTable->Length +=3D PpttType0->Length; + PrivateResource =3D (UINT32 *)((UINT8 *)PpttType0 + + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESS= OR)); + + // Add cache type structure + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE))= { + return EFI_OUT_OF_RESOURCES; + } + *PrivateResource =3D PpttTable->Length; + PpttType1 =3D (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable + + PpttTable->Length); + gBS->CopyMem ( + PpttType1, + &mPpttCacheType1[3], + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE) + ); + *PpttTableLengthRemain -=3D PpttType1->Length; + PpttTable->Length +=3D PpttType1->Length; + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +AddSocketTable ( + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable, + IN OUT UINT32 *PpttTableLengthRemain, + IN UINT32 Parent, + IN UINT32 ResourceNo + ) +{ + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0; + EFI_ACPI_6_2_PPTT_STRUCTURE_ID *PpttType2; + UINT32 *PrivateResource; + UINT8 Index; + + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESS= OR)) { + return EFI_OUT_OF_RESOURCES; + } + PpttType0 =3D (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTab= le + + PpttTable->Length); + PpttType0->Type =3D 0; + SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0); + PpttType0->Flags.PhysicalPackage =3D EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALI= D; + PpttType0->Parent=3D Parent; + PpttType0->NumberOfPrivateResources =3D ResourceNo; + PpttType0->Length =3D sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + + ResourceNo * 4; + PpttTable->Length +=3D PpttType0->Length; + + *PpttTableLengthRemain -=3D PpttType0->Length; + if (*PpttTableLengthRemain < ResourceNo * 4) { + return EFI_OUT_OF_RESOURCES; + } + PrivateResource =3D (UINT32 *)((UINT8 *)PpttType0 + + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESS= OR)); + DEBUG ((DEBUG_INFO, + "[Acpi PPTT] sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID) =3D %x!\n", + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID))); + + for (Index =3D 0; Index < ResourceNo; Index++, PrivateResource++) { + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)) { + return EFI_OUT_OF_RESOURCES; + } + *PrivateResource =3D PpttTable->Length; + PpttType2 =3D (EFI_ACPI_6_2_PPTT_STRUCTURE_ID *)((UINT8 *)PpttTable + + PpttTable->Length); + gBS->CopyMem ( + PpttType2, + &mPpttSocketType2[Index], + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID) + ); + *PpttTableLengthRemain -=3D PpttType2->Length; + PpttTable->Length +=3D PpttType2->Length; + } + + return EFI_SUCCESS; +} + +STATIC +VOID +GetApic ( + IN EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable, + IN OUT EFI_ACPI_DESCRIPTION_HEADER *PpttTable, + IN UINT32 PpttTableLengthRemai= n, + IN UINT32 Index1 +) +{ + UINT32 IndexSocket, IndexSccl, IndexCluster, IndexCore; + UINT32 SocketOffset, ScclOffset, ClusterOffset; + UINT32 Parent =3D 0; + UINT32 ResourceNo =3D 0; + + // Get APIC data + for (IndexSocket =3D 0; IndexSocket < PPTT_SOCKET_NO; IndexSocket++) { + SocketOffset =3D 0; + for (IndexSccl =3D 0; IndexSccl < PPTT_SCCL_NO; IndexSccl++) { + ScclOffset =3D 0; + for (IndexCluster =3D 0; IndexCluster < PPTT_CLUSTER_NO; IndexCluste= r++) { + ClusterOffset =3D 0; + for (IndexCore =3D 0; IndexCore < PPTT_CORE_NO; IndexCore++) { + if (ApicTable->GicInterfaces[Index1].AcpiProcessorUid !=3D Index= 1) { + // This processor is unusable + DEBUG ((DEBUG_ERROR, "[Acpi PPTT] Please check MADT table for = UID!\n")); + return; + } + if ((ApicTable->GicInterfaces[Index1].Flags & BIT0) =3D=3D 0) { + // This processor is unusable + Index1++; + continue; + } + + if (SocketOffset =3D=3D 0) { + // Add socket0 for type0 table + ResourceNo =3D PPTT_SOCKET_COMPONENT_NO; + SocketOffset =3D PpttTable->Length; + Parent =3D 0; + AddSocketTable ( + PpttTable, + &PpttTableLengthRemain, + Parent, + ResourceNo + ); + } + if (ScclOffset =3D=3D 0) { + // Add socket0sccl0 for type0 table + ResourceNo =3D 1; + ScclOffset =3D PpttTable->Length; + Parent =3D SocketOffset; + AddScclTable ( + PpttTable, + &PpttTableLengthRemain, + Parent, + ResourceNo + ); + } + if (ClusterOffset =3D=3D 0) { + // Add socket0sccl0ClusterId for type0 table + ResourceNo =3D 1; + ClusterOffset =3D PpttTable->Length ; + Parent =3D ScclOffset; + AddClusterTable ( + PpttTable, + &PpttTableLengthRemain, + Parent, + ResourceNo + ); + } + + // Add socket0sccl0ClusterIdCoreId for type0 table + ResourceNo =3D 2; + Parent =3D ClusterOffset; + AddCoreTable ( + PpttTable, + &PpttTableLengthRemain, + Parent, + ResourceNo, + Index1 + ); + + Index1++; + } + } + } + } + return ; +} + +STATIC +VOID +PpttSetAcpiTable ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINTN AcpiTableHandle; + EFI_STATUS Status; + UINT8 Checksum; + EFI_ACPI_SDT_HEADER *Table; + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *ApicTable; + EFI_ACPI_TABLE_VERSION TableVersion; + EFI_ACPI_DESCRIPTION_HEADER *PpttTable; + UINTN TableKey; + UINT32 Index0, Index1; + UINT32 PpttTableLengthRemain =3D = 0; + + gBS->CloseEvent (Event); + + InitCacheInfo (); + + PpttTable =3D (EFI_ACPI_DESCRIPTION_HEADER *)AllocateZeroPool (PPTT_TABL= E_MAX_LEN); + gBS->CopyMem ( + (VOID *)PpttTable, + &mPpttHeader, + sizeof (EFI_ACPI_DESCRIPTION_HEADER) + ); + PpttTableLengthRemain =3D PPTT_TABLE_MAX_LEN - sizeof (EFI_ACPI_DESCRIPT= ION_HEADER); + + for (Index0 =3D 0; Index0 < EFI_ACPI_MAX_NUM_TABLES; Index0++) { + Status =3D mAcpiSdtProtocol->GetAcpiTable ( + Index0, + &Table, + &TableVersion, + &TableKey + ); + if (EFI_ERROR (Status)) { + break; + } + + // Find APIC table + if (Table->Signature =3D=3D EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TAB= LE_SIGNATURE) { + break; + } + + } + + if (!EFI_ERROR (Status) && (Index0 !=3D EFI_ACPI_MAX_NUM_TABLES)) { + ApicTable =3D (EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE *)Table; + Index1 =3D 0; + + GetApic (ApicTable, PpttTable, PpttTableLengthRemain, Index1); + + Checksum =3D CalculateCheckSum8 ((UINT8 *)(PpttTable), PpttTable->Leng= th); + PpttTable->Checksum =3D Checksum; + + AcpiTableHandle =3D 0; + Status =3D mAcpiTableProtocol->InstallAcpiTable ( + mAcpiTableProtocol, + PpttTable, + PpttTable->Length, + &AcpiTableHandle); + } + + FreePool (PpttTable); + return ; +} + +EFI_STATUS +EFIAPI +PpttEntryPoint( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT ReadyToBootEvent; + + Status =3D gBS->LocateProtocol ( + &gEfiAcpiTableProtocolGuid, + NULL, + (VOID **)&mAcpiTableProtocol); + ASSERT_EFI_ERROR (Status); + + Status =3D gBS->LocateProtocol ( + &gEfiAcpiSdtProtocolGuid, + NULL, + (VOID **)&mAcpiSdtProtocol); + ASSERT_EFI_ERROR (Status); + + Status =3D EfiCreateEventReadyToBootEx ( + TPL_NOTIFY, + PpttSetAcpiTable, + NULL, + &ReadyToBootEvent + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Acpi Pptt init done.\n")); + + return Status; +} diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h b/Silicon/Hisilicon/Hi161= 6/Pptt/Pptt.h new file mode 100644 index 0000000..01926e1 --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.h @@ -0,0 +1,67 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/ +* +**/ + +#ifndef _PPTT_H_ +#define _PPTT_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../D05AcpiTables/Hi1616Platform.h" + +#define PPTT_VENDOR_ID SIGNATURE_32('H', 'I', 'S', 'I') + +#define EFI_ACPI_MAX_NUM_TABLES 20 + +#define PPTT_TABLE_MAX_LEN 0x6000 +#define PPTT_SOCKET_NO 0x2 +#define PPTT_SCCL_NO 0x2 +#define PPTT_CLUSTER_NO 0x4 +#define PPTT_CORE_NO 0x4 +#define PPTT_SOCKET_COMPONENT_NO 0x1 +#define PPTT_CACHE_NO 0x4 + +typedef union { + struct { + UINT32 InD :1; + UINT32 Level :3; + UINT32 Reserved :28; + } Bits; + UINT32 Data; +} CSSELR_DATA; + +typedef union { + struct { + UINT32 LineSize :3; + UINT32 Associativity :10; + UINT32 NumSets :15; + UINT32 Wa :1; + UINT32 Ra :1; + UINT32 Wb :1; + UINT32 Wt :1; + } Bits; + UINT32 Data; +} CCSIDR_DATA; + +#endif // _PPTT_H_ + diff --git a/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf b/Silicon/Hisilicon/Hi1= 616/Pptt/Pptt.inf new file mode 100644 index 0000000..ff6f772 --- /dev/null +++ b/Silicon/Hisilicon/Hi1616/Pptt/Pptt.inf @@ -0,0 +1,48 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/ +* +**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D AcpiPptt + FILE_GUID =3D AAB14F90-DC2E-4f33-A594-C7894A5B412D + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PpttEntryPoint + +[Sources.common] + Pptt.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + ArmLib + BaseMemoryLib + DebugLib + HobLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + +[Protocols] + gEfiAcpiSdtProtocolGuid ## PROTOCOL ALWAYS_CONSUMED + gEfiAcpiTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED + +[Depex] + gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid + --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=6Gzb0p4AIXNmRFJs8RsakCinjw6m5LkJrWeF8pUvsAA=; b=Qj/c/Hn5ytROj0h5yO2MZ0sXXc1nE+GyNhr0Hnc1d4oskYNptsthgilK85UY08EhO5 EtV4yNs0t009QqnqeDBrf5JlhsMoCTA822CKgV0AwN8ZzaO5H92GyibkqLcE9PwR0P89 S+az/iEXemobPmcZSMBSStGeZkuVOr5MTkgS65PzlF1bC1KKXEhVsQWyOWZYXi/PfuVE 7z5tMABb5N+Ji6pprbf7PlMmLTs2bCReT2ZtA+0EVsS6UW7KM14HscRBPbS5GO93ySQ4 8uVJh0uJ3EF9y0x72dSeA1RhBVjIlxE1fAvMMLs2NCDGY7ZPC6ljyRsUGsmu4qJcFiK7 9DKA== X-Gm-Message-State: APf1xPBJjp3YBp6Fo0mHXFcILn5Jz1I21RvIMtcV+AIGeBt6EBTPirtR d4VKNpeQNY5ywarPcKNQEoX49A== X-Google-Smtp-Source: AH8x224b7joOKF0BekZIloFbL1p+hnaWdWSdlEqhTyOAG3/ZI+7zG3JNTs1kDOjSA/EzKllgU5ud+Q== X-Received: by 2002:a17:902:40a:: with SMTP id 10-v6mr5161483ple.88.1517991830565; Wed, 07 Feb 2018 00:23:50 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:37 +0800 Message-Id: <1517991769-5485-4-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 03/15] Hisilicon/D0x/BDS: Switch to Generic BDS driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hisilicon-specific PlatformBootManagerLib added. It is convenient to add specific feature, like BMC control boot option. Remove Intel BDS from dsc file because it is out of use. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Signed-off-by: Jason Zhang Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Hisilicon/D03/D03.dsc = | 17 +- Platform/Hisilicon/D03/D03.fdf = | 3 +- Platform/Hisilicon/D05/D05.dsc = | 17 +- Platform/Hisilicon/D05/D05.fdf = | 3 +- Silicon/Hisilicon/HisiPkg.dec = | 2 + Silicon/Hisilicon/Hisilicon.dsc.inc = | 1 + Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c = | 636 ++++++++++++++++++++ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h = | 31 + Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.in= f | 73 +++ 9 files changed, 777 insertions(+), 6 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index b434f68..5fbe1f9 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -68,6 +68,13 @@ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLi= b.inf PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformInt= elBdsLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/= PlatformBootManagerLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf =20 # USB Requirements @@ -187,7 +194,7 @@ =20 =20 gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x0= 4, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, = 0xD1 } + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 }|VOID*|0x0001006b =20 gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000 gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 @@ -405,6 +412,12 @@ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf =20 + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } MdeModulePkg/Application/HelloWorld/HelloWorld.inf # # Bds @@ -457,7 +470,7 @@ =20 MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf =20 # # UEFI application (Shell Embedded Boot Loader) diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 0b38eb4..474f37f 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -283,6 +283,7 @@ READ_LOCK_STATUS =3D TRUE INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf !endif #$(INCLUDE_TFTP_COMMAND) =20 + INF MdeModulePkg/Application/UiApp/UiApp.inf # # Bds # @@ -291,7 +292,7 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDx= e.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf =20 [FV.FVMAIN_COMPACT] FvAlignment =3D 16 diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 710339c..4d630da 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -84,6 +84,12 @@ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLi= b.inf PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformInt= elBdsLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/= PlatformBootManagerLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf =20 # USB Requirements @@ -119,6 +125,7 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE =20 [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|8 @@ -202,8 +209,8 @@ =20 =20 gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE - gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x0= 4, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, = 0xD1 } =20 + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 }|VOID*|0x0001006b gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000 gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8 =20 @@ -560,6 +567,12 @@ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf =20 + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } # # Bds # @@ -610,7 +623,7 @@ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf # # UEFI application (Shell Embedded Boot Loader) # diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 97de4d2..9f8dc2a 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -305,6 +305,7 @@ READ_LOCK_STATUS =3D TRUE INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf !endif #$(INCLUDE_TFTP_COMMAND) =20 + INF MdeModulePkg/Application/UiApp/UiApp.inf # # Bds # @@ -313,7 +314,7 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDx= e.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf =20 [FV.FVMAIN_COMPACT] FvAlignment =3D 16 diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec index 81ba3be..398d0a7 100644 --- a/Silicon/Hisilicon/HisiPkg.dec +++ b/Silicon/Hisilicon/HisiPkg.dec @@ -94,6 +94,8 @@ =20 gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x0|UINT32|0x40000004 =20 + gHisiTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0= x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }|VOID*|0x30006554 + #FDT File Address gHisiTokenSpaceGuid.FdtFileAddress|0x0|UINT64|0x40000005 =20 diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisili= con.dsc.inc index cc23673..308064b 100644 --- a/Silicon/Hisilicon/Hisilicon.dsc.inc +++ b/Silicon/Hisilicon/Hisilicon.dsc.inc @@ -263,6 +263,7 @@ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 =20 # DEBUG_ASSERT_ENABLED 0x01 # DEBUG_PRINT_ENABLED 0x02 diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c = b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c new file mode 100644 index 0000000..15df3ba --- /dev/null +++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c @@ -0,0 +1,636 @@ +/** @file + Implementation for PlatformBootManagerLib library class interfaces. + + Copyright (c) 2018, ARM Ltd. All rights reserved.
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved. + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PlatformBm.h" + +#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >>= 8) } + + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH SerialDxe; + UART_DEVICE_PATH Uart; + VENDOR_DEFINED_DEVICE_PATH TermType; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_SERIAL_CONSOLE; +#pragma pack () + +#define SERIAL_DXE_FILE_GUID { \ + 0xD3987D4B, 0x971A, 0x435F, \ + { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } \ + } + +EFI_GUID EblAppGuid2 =3D {0x3CEF354A,0x3B7A,0x4519,{0xAD,0x70,0x72,0xA1,= 0x34,0x69,0x83,0x11}}; + +STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole =3D { + // + // VENDOR_DEVICE_PATH SerialDxe + // + { + { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH)= }, + SERIAL_DXE_FILE_GUID + }, + + // + // UART_DEVICE_PATH Uart + // + { + { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) }, + 0, // Reserved + FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate + FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits + FixedPcdGet8 (PcdUartDefaultParity), // Parity + FixedPcdGet8 (PcdUartDefaultStopBits) // StopBits + }, + + // + // VENDOR_DEFINED_DEVICE_PATH TermType + // + { + { + MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, + DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH) + } + // + // Guid to be filled in dynamically + // + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + + +#pragma pack (1) +typedef struct { + USB_CLASS_DEVICE_PATH Keyboard; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_USB_KEYBOARD; +#pragma pack () + +STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard =3D { + // + // USB_CLASS_DEVICE_PATH Keyboard + // + { + { + MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP, + DP_NODE_LEN (USB_CLASS_DEVICE_PATH) + }, + 0xFFFF, // VendorId: any + 0xFFFF, // ProductId: any + 3, // DeviceClass: HID + 1, // DeviceSubClass: boot + 1 // DeviceProtocol: keyboard + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + + +/** + Check if the handle satisfies a particular condition. + + @param[in] Handle The handle to check. + @param[in] ReportText A caller-allocated string passed in for reporting + purposes. It must never be NULL. + + @retval TRUE The condition is satisfied. + @retval FALSE Otherwise. This includes the case when the condition coul= d not + be fully evaluated due to an error. +**/ +typedef +BOOLEAN +(EFIAPI *FILTER_FUNCTION) ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ); + + +/** + Process a handle. + + @param[in] Handle The handle to process. + @param[in] ReportText A caller-allocated string passed in for reporting + purposes. It must never be NULL. +**/ +typedef +VOID +(EFIAPI *CALLBACK_FUNCTION) ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ); + +/** + Locate all handles that carry the specified protocol, filter them with a + callback function, and pass each handle that passes the filter to another + callback. + + @param[in] ProtocolGuid The protocol to look for. + + @param[in] Filter The filter function to pass each handle to. If = this + parameter is NULL, then all handles are process= ed. + + @param[in] Process The callback function to pass each handle to th= at + clears the filter. +**/ +STATIC +VOID +FilterAndProcess ( + IN EFI_GUID *ProtocolGuid, + IN FILTER_FUNCTION Filter OPTIONAL, + IN CALLBACK_FUNCTION Process + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN NoHandles; + UINTN Idx; + + Status =3D gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid, + NULL /* SearchKey */, &NoHandles, &Handles); + if (EFI_ERROR (Status)) { + // + // This is not an error, just an informative condition. + // + DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid, + Status)); + return; + } + + ASSERT (NoHandles > 0); + for (Idx =3D 0; Idx < NoHandles; ++Idx) { + CHAR16 *DevicePathText; + STATIC CHAR16 Fallback[] =3D L""; + + // + // The ConvertDevicePathToText() function handles NULL input transpare= ntly. + // + DevicePathText =3D ConvertDevicePathToText ( + DevicePathFromHandle (Handles[Idx]), + FALSE, // DisplayOnly + FALSE // AllowShortcuts + ); + if (DevicePathText =3D=3D NULL) { + DevicePathText =3D Fallback; + } + + if (Filter =3D=3D NULL || Filter (Handles[Idx], DevicePathText)) { + Process (Handles[Idx], DevicePathText); + } + + if (DevicePathText !=3D Fallback) { + FreePool (DevicePathText); + } + } + gBS->FreePool (Handles); +} + + +/** + This FILTER_FUNCTION checks if a handle corresponds to a PCI display dev= ice. +**/ +STATIC +BOOLEAN +EFIAPI +IsPciDisplay ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 Pci; + + Status =3D gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid, + (VOID**)&PciIo); + if (EFI_ERROR (Status)) { + // + // This is not an error worth reporting. + // + return FALSE; + } + + Status =3D PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */, + sizeof Pci / sizeof (UINT32), &Pci); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status)= ); + return FALSE; + } + + return IS_PCI_DISPLAY (&Pci); +} + + +/** + This CALLBACK_FUNCTION attempts to connect a handle non-recursively, ask= ing + the matching driver to produce all first-level child handles. +**/ +STATIC +VOID +EFIAPI +Connect ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + + Status =3D gBS->ConnectController ( + Handle, // ControllerHandle + NULL, // DriverImageHandle + NULL, // RemainingDevicePath -- produce all children + FALSE // Recursive + ); + DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, "%a: %s: %r\n", + __FUNCTION__, ReportText, Status)); +} + + +/** + This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the + handle, and adds it to ConOut and ErrOut. +**/ +STATIC +VOID +EFIAPI +AddOutput ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + DevicePath =3D DevicePathFromHandle (Handle); + if (DevicePath =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: %s: handle %p: device path not found\n", + __FUNCTION__, ReportText, Handle)); + return; + } + + Status =3D EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL= ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__, + ReportText, Status)); + return; + } + + Status =3D EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL= ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__, + ReportText, Status)); + return; + } + + DEBUG ((DEBUG_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTIO= N__, + ReportText)); +} + +STATIC +VOID +PlatformRegisterFvBootOption ( + EFI_GUID *FileGuid, + CHAR16 *Description, + UINT32 Attributes + ) +{ + EFI_STATUS Status; + INTN OptionIndex; + EFI_BOOT_MANAGER_LOAD_OPTION NewOption; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + Status =3D gBS->HandleProtocol ( + gImageHandle, + &gEfiLoadedImageProtocolGuid, + (VOID **) &LoadedImage + ); + ASSERT_EFI_ERROR (Status); + + EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); + DevicePath =3D DevicePathFromHandle (LoadedImage->DeviceHandle); + ASSERT (DevicePath !=3D NULL); + DevicePath =3D AppendDevicePathNode ( + DevicePath, + (EFI_DEVICE_PATH_PROTOCOL *) &FileNode + ); + ASSERT (DevicePath !=3D NULL); + + Status =3D EfiBootManagerInitializeLoadOption ( + &NewOption, + LoadOptionNumberUnassigned, + LoadOptionTypeBoot, + Attributes, + Description, + DevicePath, + NULL, + 0 + ); + ASSERT_EFI_ERROR (Status); + FreePool (DevicePath); + + BootOptions =3D EfiBootManagerGetLoadOptions ( + &BootOptionCount, LoadOptionTypeBoot + ); + + OptionIndex =3D EfiBootManagerFindLoadOption ( + &NewOption, BootOptions, BootOptionCount + ); + + if (OptionIndex =3D=3D -1) { + Status =3D EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN); + ASSERT_EFI_ERROR (Status); + } + EfiBootManagerFreeLoadOption (&NewOption); + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); +} + + +STATIC +VOID +PlatformRegisterOptionsAndKeys ( + VOID + ) +{ + EFI_STATUS Status; + EFI_INPUT_KEY Enter; + EFI_INPUT_KEY F2; + EFI_INPUT_KEY Esc; + EFI_BOOT_MANAGER_LOAD_OPTION BootOption; + + // + // Register ENTER as CONTINUE key + // + Enter.ScanCode =3D SCAN_NULL; + Enter.UnicodeChar =3D CHAR_CARRIAGE_RETURN; + Status =3D EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL); + ASSERT_EFI_ERROR (Status); + + // + // Map F2 and ESC to Boot Manager Menu + // + F2.ScanCode =3D SCAN_F2; + F2.UnicodeChar =3D CHAR_NULL; + Esc.ScanCode =3D SCAN_ESC; + Esc.UnicodeChar =3D CHAR_NULL; + + Status =3D EfiBootManagerGetBootManagerMenu (&BootOption); + ASSERT_EFI_ERROR (Status); + Status =3D EfiBootManagerAddKeyOptionVariable ( + NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL + ); + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_ALREADY_STARTED); + Status =3D EfiBootManagerAddKeyOptionVariable ( + NULL, (UINT16) BootOption.OptionNumber, 0, &Esc, NULL + ); + ASSERT (Status =3D=3D EFI_SUCCESS || Status =3D=3D EFI_ALREADY_STARTED); +} + +STATIC +VOID +UpdateMemory ( + ) +{ + EFI_STATUS Status; + EFI_GENERIC_MEMORY_TEST_PROTOCOL* MemoryTest; + BOOLEAN RequireSoftECCInit; + + RequireSoftECCInit =3D FALSE; + + // Add MemoryTest for memmap add above 4G memory. + Status =3D gBS->LocateProtocol ( + &gEfiGenericMemTestProtocolGuid, + NULL, + (VOID **)&MemoryTest); + if (!EFI_ERROR (Status)) { + Status =3D MemoryTest->MemoryTestInit ( + MemoryTest, + IGNORE, + &RequireSoftECCInit); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "MemoryTestInit fail(%r)\n", Status)); + } + } else { + DEBUG ((DEBUG_ERROR, "Get GenericMemTestProtocol fail(%r)\n", Status)); + } + + return; +} + +// +// BDS Platform Functions +// +/** + Do the platform init, can be customized by OEM/IBV + Possible things that can be done in PlatformBootManagerBeforeConsole: + Update console variable: 1. include hot-plug devices; + 2. Clear ConIn and add SOL for AMT + Register new Driver#### or Boot#### + Register new Key####: e.g.: F12 + Signal ReadyToLock event + Authentication action: 1. connect Auth devices; + 2. Identify auto logon user. +**/ +VOID +EFIAPI +PlatformBootManagerBeforeConsole ( + VOID + ) +{ + EFI_STATUS Status; + ESRT_MANAGEMENT_PROTOCOL *EsrtManagement; + + // + // Signal EndOfDxe PI Event + // + EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid); + + // + //Sync Esrt Table + // + EsrtManagement =3D NULL; + Status =3D gBS->LocateProtocol ( + &gEsrtManagementProtocolGuid, + NULL, + (VOID **)&EsrtManagement); + if (!EFI_ERROR (Status)) { + Status =3D EsrtManagement->SyncEsrtFmp (); + } + + UpdateMemory (); + + // + // Locate the PCI root bridges and make the PCI bus driver connect each, + // non-recursively. This will produce a number of child handles with Pci= Io on + // them. + // + FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect); + + // + // Find all display class PCI devices (using the handles from the previo= us + // step), and connect them non-recursively. This should produce a number= of + // child handles with GOPs on them. + // + FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect); + + // + // Now add the device path of all handles with GOP on them to ConOut and + // ErrOut. + // + FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput); + + // + // Add the hardcoded short-form USB keyboard device path to ConIn. + // + EfiBootManagerUpdateConsoleVariable (ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL); + + // + // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut. + // + ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) =3D=3D 4); + CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid); + + EfiBootManagerUpdateConsoleVariable (ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); + EfiBootManagerUpdateConsoleVariable (ConOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); + EfiBootManagerUpdateConsoleVariable (ErrOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL); + + // + // Register platform-specific boot options and keyboard shortcuts. + // + PlatformRegisterOptionsAndKeys (); +} + +/** + Do the platform specific action after the console is ready + Possible things that can be done in PlatformBootManagerAfterConsole: + Console post action: + Dynamically switch output mode from 100x31 to 80x25 for certain sena= rino + Signal console ready platform customized event + Run diagnostics like memory testing + Connect certain devices + Dispatch aditional option roms + Special boot: e.g.: USB boot, enter UI +**/ +VOID +EFIAPI +PlatformBootManagerAfterConsole ( + VOID + ) +{ + EFI_STATUS Status; + ESRT_MANAGEMENT_PROTOCOL *EsrtManagement =3D NULL; + + // + // Show the splash screen. + // + BootLogoEnableLogo (); + + // + // Connect the rest of the devices. + // + EfiBootManagerConnectAll (); + + // + // Enumerate all possible boot options. + // + EfiBootManagerRefreshAllBootOption (); + + // + // Sync Esrt Table + // + Status =3D gBS->LocateProtocol ( + &gEsrtManagementProtocolGuid, + NULL, + (VOID **)&EsrtManagement); + if (!EFI_ERROR (Status)) { + Status =3D EsrtManagement->SyncEsrtFmp (); + } + + // + // Register UEFI Shell + // + PlatformRegisterFvBootOption ( + PcdGetPtr (PcdShellFile), L"UEFI Shell", LOAD_OPTION_ACTIVE + ); +} + +/** + This function is called each second during the boot manager waits the + timeout. + + @param TimeoutRemain The remaining timeout. +**/ +VOID +EFIAPI +PlatformBootManagerWaitCallback ( + UINT16 TimeoutRemain + ) +{ + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White; + UINT16 Timeout; + + Print(L"\r%-2d seconds left, Press Esc or F2 to enter Setup.", TimeoutRe= main); + Timeout =3D PcdGet16 (PcdPlatformBootTimeOut); + + Black.Raw =3D 0x00000000; + White.Raw =3D 0x00FFFFFF; + + BootLogoUpdateProgress ( + White.Pixel, + Black.Pixel, + L"Start boot option", + White.Pixel, + (Timeout - TimeoutRemain) * 100 / Timeout, + 0 + ); +} diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h = b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h new file mode 100644 index 0000000..4067e93 --- /dev/null +++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.h @@ -0,0 +1,31 @@ +/** @file + Head file for BDS Platform specific code + + Copyright (c) 2018, ARM Ltd. All rights reserved.
+ Copyright (c) 2018, Hisilicon Limited. All rights reserved. + Copyright (c) 2018, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PLATFORM_BM_H_ +#define _PLATFORM_BM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#endif // _PLATFORM_BM_H_ diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootM= anagerLib.inf b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBo= otManagerLib.inf new file mode 100644 index 0000000..27ef64b --- /dev/null +++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerL= ib.inf @@ -0,0 +1,73 @@ +## @file +# Implementation for PlatformBootManagerLib library class interfaces. +# +# Copyright (c) 2018, ARM Ltd. All rights reserved.
+# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformBootManagerLib + FILE_GUID =3D f2a6b1de-479e-4212-859e-f014ddd27b66 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformBootManagerLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D ARM AARCH64 +# + +[Sources] + PlatformBm.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + BootLogoLib + DebugLib + DevicePathLib + DxeServicesLib + MemoryAllocationLib + PcdLib + PrintLib + UefiBootManagerLib + UefiBootServicesTableLib + UefiLib + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType + gHisiTokenSpaceGuid.PcdShellFile + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut + +[Guids] + gEfiEndOfDxeEventGroupGuid + gEfiTtyTermGuid + +[Protocols] + gEfiGenericMemTestProtocolGuid + gEfiLoadedImageProtocolGuid + gEsrtManagementProtocolGuid --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 07 Feb 2018 00:24:07 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::243; helo=mail-pf0-x243.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bl69YEg+JOs/KlPvUu5vcTL6vcifXi30aCgxtZ6U/1s=; b=cbgn7pJRwK4cxfN5FE/23o9HM3crH86UKtMkp4tTjCnwLGsZAbN9YBl38yBu68snls Li5JafmR5877bolUrLV+rfEQDUawSMCRP3RE9OkZGYWjgarwSMppfJIBLu7l/TDku2+p J5HtEU1iqOaq7HCc6bt5ApMp4ZaGumrkXmU18= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Bl69YEg+JOs/KlPvUu5vcTL6vcifXi30aCgxtZ6U/1s=; b=gpg8h8t11BTbyu0XLXaCIiHvesVNTmMvv868ifeT3SJtOE7qIwqXVqTiI1EXR3FOUT t0UqHBxl6GwANNryIIjsMiQ6XLtgrqcUDCl5zvLtoQpqwwKcWKgFvJ3WPNhQgoANJsy5 PsNrwt0lkdTPN7OU3D3fOMyZD7BrrDFlmwu4eDJ8e8xhukb+7Kt0O+98GZetZ9TiVdnv Ls0BcMHt6rNKWt9UQa6KQfo01boR0TYQguh2OJgV5EPhVKwlPmDFzrO55VTU8SB3feU/ ecX87F+L99j2CXOoGSkN/gN4QKM1JDWsxfUMUWCQ3SxsEp0XTeTzbVXs2af3LceSpE52 +WGw== X-Gm-Message-State: APf1xPC7Xm5IMDFJDd42NEKej9viDMegvDqshtcUCUHK07jwbaSnV6rP C7A2dxnEEtfW+1+6DHSuEOGqFg== X-Google-Smtp-Source: AH8x2259dgoVokpq1RD/PdSHzR5stevEUTxJ0E6pzvl8d8nCv3nmEI23mxQ3bUJQcjlPCQV23mdk+g== X-Received: by 10.101.86.73 with SMTP id m9mr4262984pgs.70.1517991847768; Wed, 07 Feb 2018 00:24:07 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:38 +0800 Message-Id: <1517991769-5485-5-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 04/15] Hisilicon/D0x: Break BMC SetBoot option out into separate library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Modify the feature of BMC set boot option as switching generic BDS. Break BMC SetBoot option out into BmcConfigBootLib. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Hisilicon/D03/D03.dsc = | 1 + Platform/Hisilicon/D05/D05.dsc = | 1 + Silicon/Hisilicon/HisiPkg.dec = | 1 + Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h = | 31 ++ Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c = | 466 ++++++++++++++++++++ Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf = | 51 +++ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c = | 7 + Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.in= f | 1 + 8 files changed, 559 insertions(+) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 5fbe1f9..e1e3b14 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -68,6 +68,7 @@ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLi= b.inf PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformInt= elBdsLib.inf + BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBoo= tLib.inf UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 4d630da..ac7da04 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -84,6 +84,7 @@ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLi= b.inf PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformInt= elBdsLib.inf + BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBoo= tLib.inf UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec index 398d0a7..889a181 100644 --- a/Silicon/Hisilicon/HisiPkg.dec +++ b/Silicon/Hisilicon/HisiPkg.dec @@ -43,6 +43,7 @@ =20 gHisiEfiMemoryMapGuid =3D {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xb= d, 0x56, 0xda, 0x91, 0xc0, 0x7f}} gVersionInfoHobGuid =3D {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0= xe, 0xe1, 0x42, 0x12, 0xbf}} + gOemBootVariableGuid =3D {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4,= 0xa4, 0x2f, 0x45, 0x06, 0xf8}} =20 [LibraryClasses] PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h diff --git a/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h b/Silicon= /Hisilicon/Include/Library/BmcConfigBootLib.h new file mode 100644 index 0000000..d937234 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/BmcConfigBootLib.h @@ -0,0 +1,31 @@ +/** @file +* +* Copyright (c) 2017, Hisilicon Limited. All rights reserved. +* Copyright (c) 2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef _BMC_CONFIG_BOOT_LIB_H_ +#define _BMC_CONFIG_BOOT_LIB_H_ + +VOID +EFIAPI +RestoreBootOrder ( + VOID + ); + +VOID +EFIAPI +HandleBmcBootType ( + VOID + ); + +#endif diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c = b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c new file mode 100644 index 0000000..08a9c9c --- /dev/null +++ b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.c @@ -0,0 +1,466 @@ +/** @file +* +* Copyright (c) 2017, Hisilicon Limited. All rights reserved. +* Copyright (c) 2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +STATIC +UINT16 +EFIAPI +GetBBSTypeFromFileSysPath ( + IN CHAR16 *UsbPathTxt, + IN CHAR16 *FileSysPathTxt, + IN EFI_DEVICE_PATH_PROTOCOL *FileSysPath + ) +{ + EFI_DEVICE_PATH_PROTOCOL *Node; + + if (StrnCmp (UsbPathTxt, FileSysPathTxt, StrLen (UsbPathTxt)) =3D=3D 0) { + Node =3D FileSysPath; + while (!IsDevicePathEnd (Node)) { + if ((DevicePathType (Node) =3D=3D MEDIA_DEVICE_PATH) && + (DevicePathSubType (Node) =3D=3D MEDIA_CDROM_DP)) { + return BBS_TYPE_CDROM; + } + Node =3D NextDevicePathNode (Node); + } + } + + return BBS_TYPE_UNKNOWN; +} + +STATIC +UINT16 +EFIAPI +GetBBSTypeFromUsbPath ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *UsbPath + ) +{ + EFI_STATUS Status; + EFI_HANDLE *FileSystemHandles; + UINTN NumberFileSystemHandles; + UINTN Index; + EFI_DEVICE_PATH_PROTOCOL *FileSysPath; + EFI_DEVICE_PATH_TO_TEXT_PROTOCOL *DevPathToText; + CHAR16 *UsbPathTxt; + CHAR16 *FileSysPathTxt; + UINT16 Result; + + Status =3D gBS->LocateProtocol ( + &gEfiDevicePathToTextProtocolGuid, + NULL, + (VOID **) &DevPathToText); + ASSERT_EFI_ERROR(Status); + + Result =3D BBS_TYPE_UNKNOWN; + UsbPathTxt =3D DevPathToText->ConvertDevicePathToText (UsbPath, TRUE, TR= UE); + if (UsbPathTxt =3D=3D NULL) { + return Result; + } + + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiSimpleFileSystemProtocolGuid, + NULL, + &NumberFileSystemHandles, + &FileSystemHandles + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Locate SimpleFileSystemProtocol error(%r)\n", St= atus)); + FreePool (UsbPathTxt); + return BBS_TYPE_UNKNOWN; + } + + for (Index =3D 0; Index < NumberFileSystemHandles; Index++) { + FileSysPath =3D DevicePathFromHandle (FileSystemHandles[Index]); + FileSysPathTxt =3D DevPathToText->ConvertDevicePathToText (FileSysPath= , TRUE, TRUE); + + if (FileSysPathTxt =3D=3D NULL) { + continue; + } + + Result =3D GetBBSTypeFromFileSysPath (UsbPathTxt, FileSysPathTxt, File= SysPath); + FreePool (FileSysPathTxt); + + if (Result !=3D BBS_TYPE_UNKNOWN) { + break; + } + } + + if (NumberFileSystemHandles !=3D 0) { + FreePool (FileSystemHandles); + } + + FreePool (UsbPathTxt); + + return Result; +} + +STATIC +UINT16 +EFIAPI +GetBBSTypeFromMessagingDevicePath ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + IN EFI_DEVICE_PATH_PROTOCOL *Node + ) +{ + VENDOR_DEVICE_PATH *Vendor; + UINT16 Result; + + Result =3D BBS_TYPE_UNKNOWN; + + switch (DevicePathSubType (Node)) { + case MSG_MAC_ADDR_DP: + Result =3D BBS_TYPE_EMBEDDED_NETWORK; + break; + + case MSG_USB_DP: + Result =3D GetBBSTypeFromUsbPath (DevicePath); + if (Result =3D=3D BBS_TYPE_UNKNOWN) { + Result =3D BBS_TYPE_USB; + } + break; + + case MSG_SATA_DP: + Result =3D BBS_TYPE_HARDDRIVE; + break; + + case MSG_VENDOR_DP: + Vendor =3D (VENDOR_DEVICE_PATH *) (Node); + if (&Vendor->Guid !=3D NULL) { + if (CompareGuid (&Vendor->Guid, &((EFI_GUID) DEVICE_PATH_MESSAGING_S= AS))) { + Result =3D BBS_TYPE_HARDDRIVE; + } + } + break; + + default: + Result =3D BBS_TYPE_UNKNOWN; + break; + } + + return Result; +} + +STATIC +UINT16 +EFIAPI +GetBBSTypeByDevicePath ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + EFI_DEVICE_PATH_PROTOCOL *Node; + UINT16 Result; + + Result =3D BBS_TYPE_UNKNOWN; + if (DevicePath =3D=3D NULL) { + return Result; + } + + Node =3D DevicePath; + while (!IsDevicePathEnd (Node)) { + switch (DevicePathType (Node)) { + case MEDIA_DEVICE_PATH: + if (DevicePathSubType (Node) =3D=3D MEDIA_CDROM_DP) { + Result =3D BBS_TYPE_CDROM; + } + break; + + case MESSAGING_DEVICE_PATH: + Result =3D GetBBSTypeFromMessagingDevicePath (DevicePath, Node); + break; + + default: + Result =3D BBS_TYPE_UNKNOWN; + break; + } + + if (Result !=3D BBS_TYPE_UNKNOWN) { + break; + } + + Node =3D NextDevicePathNode (Node); + } + + return Result; +} + +STATIC +EFI_STATUS +EFIAPI +GetBmcBootOptionsSetting ( + OUT IPMI_GET_BOOT_OPTION *BmcBootOpt + ) +{ + EFI_STATUS Status; + + Status =3D IpmiCmdGetSysBootOptions (BmcBootOpt); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Get iBMC BootOpts %r!\n", Status)); + return Status; + } + + if (BmcBootOpt->BootFlagsValid !=3D BOOT_OPTION_BOOT_FLAG_VALID) { + return EFI_NOT_FOUND; + } + + if (BmcBootOpt->Persistent) { + BmcBootOpt->BootFlagsValid =3D BOOT_OPTION_BOOT_FLAG_VALID; + } else { + BmcBootOpt->BootFlagsValid =3D BOOT_OPTION_BOOT_FLAG_INVALID; + } + + Status =3D IpmiCmdSetSysBootOptions (BmcBootOpt); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Set iBMC BootOpts %r!\n", Status)); + } + + return Status; +} + +VOID +EFIAPI +RestoreBootOrder ( + VOID + ) +{ + EFI_STATUS Status; + UINT16 *BootOrder; + UINTN BootOrderSize; + + GetVariable2 ( + L"BootOrderBackup", + &gOemBootVariableGuid, + (VOID **) &BootOrder, + &BootOrderSize + ); + if (BootOrder =3D=3D NULL) { + return ; + } + + Print (L"\nRestore BootOrder(%d).\n", BootOrderSize / sizeof (UINT16)); + + Status =3D gRT->SetVariable ( + L"BootOrder", + &gEfiGlobalVariableGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_A= CCESS + | EFI_VARIABLE_NON_VOLATILE, + BootOrderSize, + BootOrder + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SetVariable BootOrder %r!\n", Status)); + } + + Status =3D gRT->SetVariable ( + L"BootOrderBackup", + &gOemBootVariableGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLAT= ILE, + 0, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SetVariable BootOrderBackup %r!\n", Status)); + } + + FreePool (BootOrder); +} + + +STATIC +VOID +EFIAPI +RestoreBootOrderOnReadyToBoot ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // restore BootOrder variable in normal condition. + RestoreBootOrder (); +} + +STATIC +VOID +EFIAPI +UpdateBootOrder ( + IN UINT16 *NewOrder, + IN UINT16 *BootOrder, + IN UINTN BootOrderSize + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + Status =3D gRT->SetVariable ( + L"BootOrderBackup", + &gOemBootVariableGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLAT= ILE, + BootOrderSize, + BootOrder + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Set BootOrderBackup Variable:%r!\n", Status)); + return; + } + + Status =3D gRT->SetVariable ( + L"BootOrder", + &gEfiGlobalVariableGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_A= CCESS + | EFI_VARIABLE_NON_VOLATILE, + BootOrderSize, + NewOrder + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Set BootOrder Variable:%r!\n", Status)); + return; + } + + // Register notify function to restore BootOrder variable on ReadyToBoot= Event. + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + RestoreBootOrderOnReadyToBoot, + NULL, + &gEfiEventReadyToBootGuid, + &Event + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Create ready to boot event %r!\n", Status)); + } +} + +STATIC +VOID +EFIAPI +SetBootOrder ( + IN UINT16 BootType + ) +{ + EFI_STATUS Status; + UINT16 *NewOrder; + UINT16 *RemainBoots; + UINT16 *BootOrder; + UINTN BootOrderSize; + EFI_BOOT_MANAGER_LOAD_OPTION Option; + CHAR16 OptionName[sizeof ("Boot####")]; + UINTN Index; + UINTN SelectCnt; + UINTN RemainCnt; + + GetEfiGlobalVariable2 (L"BootOrder", (VOID **) &BootOrder, &BootOrderSiz= e); + if (BootOrder =3D=3D NULL) { + return ; + } + + NewOrder =3D AllocatePool (BootOrderSize); + RemainBoots =3D AllocatePool (BootOrderSize); + if ((NewOrder =3D=3D NULL) || (RemainBoots =3D=3D NULL)) { + DEBUG ((DEBUG_ERROR, "Out of resources.")); + goto Exit; + } + + SelectCnt =3D 0; + RemainCnt =3D 0; + + for (Index =3D 0; Index < BootOrderSize / sizeof (UINT16); Index++) { + UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", BootOrder= [Index]); + Status =3D EfiBootManagerVariableToLoadOption (OptionName, &Option); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Boot%04x is invalid option!\n", BootOrder[Inde= x])); + continue; + } + + if (GetBBSTypeByDevicePath (Option.FilePath) =3D=3D BootType) { + NewOrder[SelectCnt++] =3D BootOrder[Index]; + } else { + RemainBoots[RemainCnt++] =3D BootOrder[Index]; + } + } + + if (SelectCnt !=3D 0) { + // append RemainBoots to NewOrder + for (Index =3D 0; Index < RemainCnt; Index++) { + NewOrder[SelectCnt + Index] =3D RemainBoots[Index]; + } + + if (CompareMem (NewOrder, BootOrder, BootOrderSize) !=3D 0) { + UpdateBootOrder (NewOrder, BootOrder, BootOrderSize); + } + } + +Exit: + FreePool (BootOrder); + if (NewOrder !=3D NULL) { + FreePool (NewOrder); + } + if (RemainBoots !=3D NULL) { + FreePool (RemainBoots); + } +} + +VOID +EFIAPI +HandleBmcBootType ( + VOID + ) +{ + EFI_STATUS Status; + IPMI_GET_BOOT_OPTION BmcBootOpt; + UINT16 BootType; + + Status =3D GetBmcBootOptionsSetting (&BmcBootOpt); + if (EFI_ERROR (Status)) { + return; + } + + Print (L"Boot Type from BMC is %x\n", BmcBootOpt.BootDeviceSelector); + + switch (BmcBootOpt.BootDeviceSelector) { + case ForcePxe: + BootType =3D BBS_TYPE_EMBEDDED_NETWORK; + break; + + case ForcePrimaryRemovableMedia: + BootType =3D BBS_TYPE_USB; + break; + + case ForceDefaultHardDisk: + BootType =3D BBS_TYPE_HARDDRIVE; + break; + + case ForceDefaultCD: + BootType =3D BBS_TYPE_CDROM; + break; + + default: + return; + } + + SetBootOrder (BootType); +} + diff --git a/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.in= f b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf new file mode 100644 index 0000000..b603523 --- /dev/null +++ b/Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf @@ -0,0 +1,51 @@ +#/** @file +# +# Copyright (c) 2015, Hisilicon Limited. All rights reserved. +# Copyright (c) 2015, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the= BSD License +# which accompanies this distribution. The full text of the license may= be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D BmcConfigBootLib + FILE_GUID =3D f174d192-7208-46c1-b9d1-65b2db06ad3b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BmcConfigBootLib + +[Sources.common] + BmcConfigBootLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + IpmiCmdLib + PcdLib + PrintLib + UefiBootManagerLib + +[Guids] + gEfiEventReadyToBootGuid + gOemBootVariableGuid + +[Protocols] + gEfiDevicePathToTextProtocolGuid ## CONSUMES + gEfiSimpleFileSystemProtocolGuid ## CONSUMES + +[Depex] + gEfiDevicePathToTextProtocolGuid diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c = b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c index 15df3ba..7dd5ba6 100644 --- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c +++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c @@ -17,6 +17,7 @@ =20 #include #include +#include #include #include #include @@ -502,6 +503,10 @@ PlatformBootManagerBeforeConsole ( Status =3D EsrtManagement->SyncEsrtFmp (); } =20 + // restore BootOrder variable if previous BMC boot override attempt + // left it in a modified state + RestoreBootOrder (); + UpdateMemory (); =20 // @@ -601,6 +606,8 @@ PlatformBootManagerAfterConsole ( PlatformRegisterFvBootOption ( PcdGetPtr (PcdShellFile), L"UEFI Shell", LOAD_OPTION_ACTIVE ); + + HandleBmcBootType (); } =20 /** diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootM= anagerLib.inf b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBo= otManagerLib.inf index 27ef64b..7a53bef 100644 --- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerL= ib.inf +++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerL= ib.inf @@ -42,6 +42,7 @@ BaseLib BaseMemoryLib BootLogoLib + BmcConfigBootLib DebugLib DevicePathLib DxeServicesLib --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 07 Feb 2018 00:24:26 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::242; helo=mail-pg0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MvmvB7CG7gEIMeVZ95r6DMiF8DhjMQe66mY42wnUmlo=; b=dXLcTbRIz+RRO3etWZB1Jj6dr+u+KyJ6fA8AqfUzhMr7+Ul4gaNLHpbJg+LPydYNBD LdV774sPsIsNUljL8UzcwQo4cKd/d30YvADeWdWVN18ZMy6fMQqAaHyNAjC/f9HugKJM it3C2iDu5EsExr0IH+rW4+hOgEXeA1Kq561Wg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MvmvB7CG7gEIMeVZ95r6DMiF8DhjMQe66mY42wnUmlo=; b=QlRYfez9IZfZguPZjuzcBsc7GDDokJpXfhpp19G7mx6yFa3wkSaAC0/zcOxPHGeqWD sVSJs96ZCc7WMwnoH+/fmquggWkMQ+eu53nUg2S2coN0kg2xARgoE3kn2dCyz4H25gxD MZhzEGrCJ9zySzR4vx4fLX/33VBX83RpSn4f0jIrveVRKYtu5p320dbrdqJEmJHi/qy7 0eTY/YKlAt8D+zT78758wm4Ry8vOfttNMRApfQPvSmH20ttCCPqZt0uFluRFNbO+PFSW 5N9NIl1lDSBz0znW+p1+KbiCP6BUQnramjtQ3iiBX/mNWcLdN8JnjhOW0BcH/b7S5uOo WXzQ== X-Gm-Message-State: APf1xPBbaLfzyZTag1HZviGmwZP5NxFIioHrTxUlcs4SnW4peX1SBJXv 0V9V81AnqVmHSon5uNR/DgzzDw== X-Google-Smtp-Source: AH8x226bhCAyqBRPs6ovYsuWc9uMtEyQ5E//wQia5XG9nJhz6ZfvyYbgx0oPWKHgED3Tu9BoFH6+ZQ== X-Received: by 10.99.64.196 with SMTP id n187mr4212411pga.147.1517991866899; Wed, 07 Feb 2018 00:24:26 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:39 +0800 Message-Id: <1517991769-5485-6-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 05/15] Hisilicon D03/D05: Add capsule upgrade support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This module support updating the boot CPU firmware only. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason Zhang Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUp= dateConfig.ini | 45 +++++++ Platform/Hisilicon/D03/D03.dsc = | 17 ++- Platform/Hisilicon/D03/D03.fdf = | 70 +++++++++++ Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDesc= riptor.aslc | 81 +++++++++++++ Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDesc= riptor.inf | 50 ++++++++ Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDesc= riptorPei.c | 70 +++++++++++ Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUp= dateConfig.ini | 45 +++++++ Platform/Hisilicon/D05/D05.dsc = | 19 ++- Platform/Hisilicon/D05/D05.fdf = | 70 +++++++++++ Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDesc= riptor.aslc | 81 +++++++++++++ Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDesc= riptor.inf | 50 ++++++++ Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDesc= riptorPei.c | 70 +++++++++++ Silicon/Hisilicon/Hisilicon.dsc.inc = | 11 +- Silicon/Hisilicon/Hisilicon.fdf.inc = | 9 ++ Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe= .c | 123 ++++++++++++++++++++ Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe= .inf | 51 ++++++++ 16 files changed, 859 insertions(+), 3 deletions(-) diff --git a/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/Syst= emFirmwareUpdateConfig.ini b/Platform/Hisilicon/D03/Capsule/SystemFirmwareU= pdateConfig/SystemFirmwareUpdateConfig.ini new file mode 100644 index 0000000..fc834d9 --- /dev/null +++ b/Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmw= areUpdateConfig.ini @@ -0,0 +1,45 @@ +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Head] +NumOfUpdate =3D 3 +NumOfRecovery =3D 0 +Update0 =3D SysFvMain +Update1 =3D SysCustom +Update2 =3D SysNvRam + +[SysFvMain] +FirmwareType =3D 0 # 0 - SystemFirmware, 1 - NvRam +AddressType =3D 0 # 0 - relative address, 1 - absolute addre= ss. +BaseAddress =3D 0x00000000 # Base address offset on flash +Length =3D 0x002D0000 # Length +ImageOffset =3D 0x00000000 # Image offset of this SystemFirmware image +FileGuid =3D 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFi= rmwareFileGuid + +[SysCustom] +FirmwareType =3D 0 # 0 - SystemFirmware, 1 - NvRam +AddressType =3D 0 # 0 - relative address, 1 - absolute addre= ss. +BaseAddress =3D 0x002F0000 # Base address offset on flash +Length =3D 0x00010000 # Length +ImageOffset =3D 0x002F0000 # Image offset of this SystemFirmware image +FileGuid =3D 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFi= rmwareFileGuid + +[SysNvRam] +FirmwareType =3D 1 # 0 - SystemFirmware, 1 - NvRam +AddressType =3D 0 # 0 - relative address, 1 - absolute addre= ss. +BaseAddress =3D 0x002D0000 # Base address offset on flash +Length =3D 0x00020000 # Length +ImageOffset =3D 0x002D0000 # Image offset of this SystemFirmware image +FileGuid =3D 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFi= rmwareFileGuid diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index e1e3b14..82c8bb4 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -65,7 +65,6 @@ OemAddressMapLib|Platform/Hisilicon/D03/Library/OemAddressMap2P/OemAddre= ssMap2PHi1610.inf PlatformSysCtrlLib|Silicon/Hisilicon/Hi1610/Library/PlatformSysCtrlLibHi= 1610/PlatformSysCtrlLibHi1610.inf =20 - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLi= b.inf PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformInt= elBdsLib.inf BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBoo= tLib.inf @@ -115,6 +114,11 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE =20 +[PcdsDynamicExDefault.common.DEFAULT] + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor= |{0x0}|VOID*|0x100 + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29,= 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0x= c5, 0x04, 0x89} + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf,= 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0x= c5, 0x7b, 0x55} + [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|8 =20 @@ -305,6 +309,8 @@ Platform/Hisilicon/D03/EarlyConfigPeim/EarlyConfigPeimD03.inf Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf =20 + Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwareDe= scriptor.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCus= tomDecompressLib.inf @@ -405,6 +411,9 @@ =20 Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf =20 + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.= inf + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + # # FAT filesystem + GPT/MBR partitioning # @@ -472,6 +481,12 @@ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.= inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/F= mpAuthenticationLibPkcs7.inf + } + + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf =20 # # UEFI application (Shell Embedded Boot Loader) diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 474f37f..6462a53 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -275,6 +275,8 @@ READ_LOCK_STATUS =3D TRUE INF Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf =20 + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReport= Dxe.inf + INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf # # Build Shell from latest source code instead of prebuilt binary # @@ -330,12 +332,80 @@ READ_LOCK_STATUS =3D TRUE =20 INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf =20 + INF RuleOverride =3D FMP_IMAGE_DESC Platform/Hisilicon/D03/Drivers/Syste= mFirmwareDescriptor/SystemFirmwareDescriptor.inf + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { SECTION FV_IMAGE =3D FVMAIN } } =20 +[FV.CapsuleDispatchFv] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdate= Dxe.inf + +[FV.SystemFirmwareUpdateCargo] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + FILE RAW =3D 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirm= wareFileGuid + FD =3D D03 + } + + FILE RAW =3D ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCap= suleDriverFvFileGuid + FV =3D CapsuleDispatchFv + } + + FILE RAW =3D 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCap= suleConfigFileGuid + Platform/Hisilicon/D03/Capsule/SystemFirmwareUpdateConfig/SystemFirmwa= reUpdateConfig.ini + } + +[FmpPayload.FmpPayloadSystemFirmwarePkcs7] +IMAGE_HEADER_INIT_VERSION =3D 0x02 +IMAGE_TYPE_ID =3D 44c850f2-85ff-4be5-bf34-a59528df22d3 # PcdSy= stemFmpCapsuleImageTypeIdGuid +IMAGE_INDEX =3D 0x1 +HARDWARE_INSTANCE =3D 0x0 +MONOTONIC_COUNT =3D 0x1 +CERTIFICATE_GUID =3D 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 + + FV =3D SystemFirmwareUpdateCargo + +[Capsule.StyxFirmwareUpdateCapsuleFmpPkcs7] +CAPSULE_GUID =3D 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEf= iFmpCapsuleGuid +CAPSULE_HEADER_SIZE =3D 0x20 +CAPSULE_HEADER_INIT_VERSION =3D 0x1 + + FMP_PAYLOAD =3D FmpPayloadSystemFirmwarePkcs7 =20 !include Silicon/Hisilicon/Hisilicon.fdf.inc =20 diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/System= FirmwareDescriptor.aslc b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDesc= riptor/SystemFirmwareDescriptor.aslc new file mode 100644 index 0000000..2589e20 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwar= eDescriptor.aslc @@ -0,0 +1,81 @@ +/** @file + System Firmware descriptor. + + Copyright (c) 2018, Hisilicon Limited. All rights reserved. + Copyright (c) 2018, Linaro Limited. All rights reserved. + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include + +#define PACKAGE_VERSION 0xFFFFFFFF +#define PACKAGE_VERSION_STRING L"Unknown" + +#define CURRENT_FIRMWARE_VERSION 0x00000002 +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002" +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 + +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R',= 'M', '_', 'F', 'd') +#define IMAGE_ID_STRING L"ARMPlatformFd" + +// PcdSystemFmpCapsuleImageTypeIdGuid +#define IMAGE_TYPE_ID_GUID { 0x44c850f2, 0x85ff, 0x4be5, = { 0xbf, 0x34, 0xa5, 0x95, 0x28, 0xdf, 0x22, 0xd3 } } + +typedef struct { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor; + // real string data + CHAR16 ImageIdNameStr[ARRAY_SIZE (IMAGE= _ID_STRING)]; + CHAR16 VersionNameStr[ARRAY_SIZE (CURRE= NT_FIRMWARE_VERSION_STRING)]; + CHAR16 PackageVersionNameStr[ARRAY_SIZE= (PACKAGE_VERSION_STRING)]; +} IMAGE_DESCRIPTOR; + +IMAGE_DESCRIPTOR mImageDescriptor =3D +{ + { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE, + sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR), + sizeof (IMAGE_DESCRIPTOR), + PACKAGE_VERSION, // PackageVersi= on + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersi= onName + 1, // ImageIndex; + {0x0}, // Reserved + IMAGE_TYPE_ID_GUID, // ImageTypeId; + IMAGE_ID, // ImageId; + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName; + CURRENT_FIRMWARE_VERSION, // Version; + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; + {0x0}, // Reserved2 + FixedPcdGet32 (PcdFdSize), // Size; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE, // AttributesSu= pported; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE, // AttributesSe= tting; + 0x0, // Compatibilit= ies; + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSuppor= tedImageVersion; + 0x00000000, // LastAttemptV= ersion; + 0, // LastAttemptS= tatus; + {0x0}, // Reserved3 + 0, // HardwareInst= ance; + }, + // real string data + {IMAGE_ID_STRING}, + {CURRENT_FIRMWARE_VERSION_STRING}, + {PACKAGE_VERSION_STRING}, +}; + +VOID* CONST ReferenceAcpiTable =3D &mImageDescriptor; diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/System= FirmwareDescriptor.inf b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescr= iptor/SystemFirmwareDescriptor.inf new file mode 100644 index 0000000..fc1832f --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwar= eDescriptor.inf @@ -0,0 +1,50 @@ +## @file +# System Firmware descriptor. +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SystemFirmwareDescriptor + FILE_GUID =3D 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SystemFirmwareDescriptorPeimEntry + +[Sources] + SystemFirmwareDescriptorPei.c + SystemFirmwareDescriptor.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + SignedCapsulePkg/SignedCapsulePkg.dec + +[LibraryClasses] + DebugLib + PcdLib + PeimEntryPoint + PeiServicesLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdSize + +[Pcd] + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor + +[Depex] + TRUE diff --git a/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/System= FirmwareDescriptorPei.c b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDesc= riptor/SystemFirmwareDescriptorPei.c new file mode 100644 index 0000000..27c0a71 --- /dev/null +++ b/Platform/Hisilicon/D03/Drivers/SystemFirmwareDescriptor/SystemFirmwar= eDescriptorPei.c @@ -0,0 +1,70 @@ +/** @file + System Firmware descriptor producer. + + Copyright (c) 2018, Hisilicon Limited. All rights reserved. + Copyright (c) 2018, Linaro Limited. All rights reserved. + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Entrypoint for SystemFirmwareDescriptor PEIM. + + @param[in] FileHandle Handle of the file being invoked. + @param[in] PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS PPI successfully installed. +**/ +EFI_STATUS +EFIAPI +SystemFirmwareDescriptorPeimEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor; + UINTN Size; + UINTN Index; + UINT32 AuthenticationStatus; + + // + // Search RAW section. + // + + Index =3D 0; + while (TRUE) { + Status =3D PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, Fil= eHandle, (VOID **)&Descriptor, &AuthenticationStatus); + if (EFI_ERROR (Status)) { + // Should not happen, must something wrong in FDF. + DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n"= )); + return EFI_NOT_FOUND; + } + if (Descriptor->Signature =3D=3D EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTO= R_SIGNATURE) { + break; + } + Index++; + } + + DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\= n", Descriptor->Length)); + + Size =3D Descriptor->Length; + PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor); + + return EFI_SUCCESS; +} diff --git a/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/Syst= emFirmwareUpdateConfig.ini b/Platform/Hisilicon/D05/Capsule/SystemFirmwareU= pdateConfig/SystemFirmwareUpdateConfig.ini new file mode 100644 index 0000000..fc834d9 --- /dev/null +++ b/Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmw= areUpdateConfig.ini @@ -0,0 +1,45 @@ +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Head] +NumOfUpdate =3D 3 +NumOfRecovery =3D 0 +Update0 =3D SysFvMain +Update1 =3D SysCustom +Update2 =3D SysNvRam + +[SysFvMain] +FirmwareType =3D 0 # 0 - SystemFirmware, 1 - NvRam +AddressType =3D 0 # 0 - relative address, 1 - absolute addre= ss. +BaseAddress =3D 0x00000000 # Base address offset on flash +Length =3D 0x002D0000 # Length +ImageOffset =3D 0x00000000 # Image offset of this SystemFirmware image +FileGuid =3D 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFi= rmwareFileGuid + +[SysCustom] +FirmwareType =3D 0 # 0 - SystemFirmware, 1 - NvRam +AddressType =3D 0 # 0 - relative address, 1 - absolute addre= ss. +BaseAddress =3D 0x002F0000 # Base address offset on flash +Length =3D 0x00010000 # Length +ImageOffset =3D 0x002F0000 # Image offset of this SystemFirmware image +FileGuid =3D 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFi= rmwareFileGuid + +[SysNvRam] +FirmwareType =3D 1 # 0 - SystemFirmware, 1 - NvRam +AddressType =3D 0 # 0 - relative address, 1 - absolute addre= ss. +BaseAddress =3D 0x002D0000 # Base address offset on flash +Length =3D 0x00020000 # Length +ImageOffset =3D 0x002D0000 # Image offset of this SystemFirmware image +FileGuid =3D 642e4fcf-2df7-4415-8b70-a03909c57b55 # PcdEdkiiSystemFi= rmwareFileGuid diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index ac7da04..e39acb1 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -81,7 +81,6 @@ OemAddressMapLib|Platform/Hisilicon/D05/Library/OemAddressMapD05/OemAddr= essMapD05.inf PlatformSysCtrlLib|Silicon/Hisilicon/Hi1616/Library/PlatformSysCtrlLibHi= 1616/PlatformSysCtrlLibHi1616.inf =20 - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLi= b.inf PlatformBdsLib|Silicon/Hisilicon/Library/PlatformIntelBdsLib/PlatformInt= elBdsLib.inf BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBoo= tLib.inf @@ -128,6 +127,11 @@ gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE =20 +[PcdsDynamicExDefault.common.DEFAULT] + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor= |{0x0}|VOID*|0x100 + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29,= 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0x= c5, 0x04, 0x89} + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf,= 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0x= c5, 0x7b, 0x55} + [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdCoreCount|8 =20 @@ -444,6 +448,8 @@ Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf =20 + Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwareDe= scriptor.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCus= tomDecompressLib.inf @@ -560,6 +566,9 @@ =20 Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf =20 + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.= inf + MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf + # # FAT filesystem + GPT/MBR partitioning # @@ -625,6 +634,14 @@ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.= inf { + + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/F= mpAuthenticationLibPkcs7.inf + } + + MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf + # # UEFI application (Shell Embedded Boot Loader) # diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 9f8dc2a..b0296e1 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -297,6 +297,8 @@ READ_LOCK_STATUS =3D TRUE INF Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf =20 + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReport= Dxe.inf + INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf # # Build Shell from latest source code instead of prebuilt binary # @@ -355,12 +357,80 @@ READ_LOCK_STATUS =3D TRUE =20 INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf =20 + INF RuleOverride =3D FMP_IMAGE_DESC Platform/Hisilicon/D05/Drivers/Syste= mFirmwareDescriptor/SystemFirmwareDescriptor.inf + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { SECTION FV_IMAGE =3D FVMAIN } } =20 +[FV.CapsuleDispatchFv] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdate= Dxe.inf + +[FV.SystemFirmwareUpdateCargo] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + FILE RAW =3D 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirm= wareFileGuid + FD =3D D05 + } + + FILE RAW =3D ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCap= suleDriverFvFileGuid + FV =3D CapsuleDispatchFv + } + + FILE RAW =3D 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCap= suleConfigFileGuid + Platform/Hisilicon/D05/Capsule/SystemFirmwareUpdateConfig/SystemFirmwa= reUpdateConfig.ini + } + +[FmpPayload.FmpPayloadSystemFirmwarePkcs7] +IMAGE_HEADER_INIT_VERSION =3D 0x02 +IMAGE_TYPE_ID =3D 7978365d-7978-45fd-ad77-b27693cfe85b # PcdSy= stemFmpCapsuleImageTypeIdGuid +IMAGE_INDEX =3D 0x1 +HARDWARE_INSTANCE =3D 0x0 +MONOTONIC_COUNT =3D 0x1 +CERTIFICATE_GUID =3D 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7 + + FV =3D SystemFirmwareUpdateCargo + +[Capsule.StyxFirmwareUpdateCapsuleFmpPkcs7] +CAPSULE_GUID =3D 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEf= iFmpCapsuleGuid +CAPSULE_HEADER_SIZE =3D 0x20 +CAPSULE_HEADER_INIT_VERSION =3D 0x1 + + FMP_PAYLOAD =3D FmpPayloadSystemFirmwarePkcs7 =20 !include Silicon/Hisilicon/Hisilicon.fdf.inc =20 diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/System= FirmwareDescriptor.aslc b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDesc= riptor/SystemFirmwareDescriptor.aslc new file mode 100644 index 0000000..5091c7a --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwar= eDescriptor.aslc @@ -0,0 +1,81 @@ +/** @file + System Firmware descriptor. + + Copyright (c) 2018, Hisilicon Limited. All rights reserved. + Copyright (c) 2018, Linaro Limited. All rights reserved. + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include + +#define PACKAGE_VERSION 0xFFFFFFFF +#define PACKAGE_VERSION_STRING L"Unknown" + +#define CURRENT_FIRMWARE_VERSION 0x00000002 +#define CURRENT_FIRMWARE_VERSION_STRING L"0x00000002" +#define LOWEST_SUPPORTED_FIRMWARE_VERSION 0x00000001 + +#define IMAGE_ID SIGNATURE_64('H','W','A', 'R',= 'M', '_', 'F', 'd') +#define IMAGE_ID_STRING L"ARMPlatformFd" + +// PcdSystemFmpCapsuleImageTypeIdGuid +#define IMAGE_TYPE_ID_GUID { 0x7978365d, 0x7978, 0x45fd, = { 0xad, 0x77, 0xb2, 0x76, 0x93, 0xcf, 0xe8, 0x5b } } + +typedef struct { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR Descriptor; + // real string data + CHAR16 ImageIdNameStr[ARRAY_SIZE (IMAGE= _ID_STRING)]; + CHAR16 VersionNameStr[ARRAY_SIZE (CURRE= NT_FIRMWARE_VERSION_STRING)]; + CHAR16 PackageVersionNameStr[ARRAY_SIZE= (PACKAGE_VERSION_STRING)]; +} IMAGE_DESCRIPTOR; + +IMAGE_DESCRIPTOR mImageDescriptor =3D +{ + { + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE, + sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR), + sizeof (IMAGE_DESCRIPTOR), + PACKAGE_VERSION, // PackageVersi= on + OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr), // PackageVersi= onName + 1, // ImageIndex; + {0x0}, // Reserved + IMAGE_TYPE_ID_GUID, // ImageTypeId; + IMAGE_ID, // ImageId; + OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr), // ImageIdName; + CURRENT_FIRMWARE_VERSION, // Version; + OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr), // VersionName; + {0x0}, // Reserved2 + FixedPcdGet32 (PcdFdSize), // Size; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE, // AttributesSu= pported; + IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | + IMAGE_ATTRIBUTE_RESET_REQUIRED | + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED | + IMAGE_ATTRIBUTE_IN_USE, // AttributesSe= tting; + 0x0, // Compatibilit= ies; + LOWEST_SUPPORTED_FIRMWARE_VERSION, // LowestSuppor= tedImageVersion; + 0x00000000, // LastAttemptV= ersion; + 0, // LastAttemptS= tatus; + {0x0}, // Reserved3 + 0, // HardwareInst= ance; + }, + // real string data + {IMAGE_ID_STRING}, + {CURRENT_FIRMWARE_VERSION_STRING}, + {PACKAGE_VERSION_STRING}, +}; + +VOID* CONST ReferenceAcpiTable =3D &mImageDescriptor; diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/System= FirmwareDescriptor.inf b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescr= iptor/SystemFirmwareDescriptor.inf new file mode 100644 index 0000000..fc1832f --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwar= eDescriptor.inf @@ -0,0 +1,50 @@ +## @file +# System Firmware descriptor. +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SystemFirmwareDescriptor + FILE_GUID =3D 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SystemFirmwareDescriptorPeimEntry + +[Sources] + SystemFirmwareDescriptorPei.c + SystemFirmwareDescriptor.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + SignedCapsulePkg/SignedCapsulePkg.dec + +[LibraryClasses] + DebugLib + PcdLib + PeimEntryPoint + PeiServicesLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdSize + +[Pcd] + gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor + +[Depex] + TRUE diff --git a/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/System= FirmwareDescriptorPei.c b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDesc= riptor/SystemFirmwareDescriptorPei.c new file mode 100644 index 0000000..27c0a71 --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/SystemFirmwareDescriptor/SystemFirmwar= eDescriptorPei.c @@ -0,0 +1,70 @@ +/** @file + System Firmware descriptor producer. + + Copyright (c) 2018, Hisilicon Limited. All rights reserved. + Copyright (c) 2018, Linaro Limited. All rights reserved. + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include + +/** + Entrypoint for SystemFirmwareDescriptor PEIM. + + @param[in] FileHandle Handle of the file being invoked. + @param[in] PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS PPI successfully installed. +**/ +EFI_STATUS +EFIAPI +SystemFirmwareDescriptorPeimEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR *Descriptor; + UINTN Size; + UINTN Index; + UINT32 AuthenticationStatus; + + // + // Search RAW section. + // + + Index =3D 0; + while (TRUE) { + Status =3D PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, Fil= eHandle, (VOID **)&Descriptor, &AuthenticationStatus); + if (EFI_ERROR (Status)) { + // Should not happen, must something wrong in FDF. + DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n"= )); + return EFI_NOT_FOUND; + } + if (Descriptor->Signature =3D=3D EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTO= R_SIGNATURE) { + break; + } + Index++; + } + + DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\= n", Descriptor->Length)); + + Size =3D Descriptor->Length; + PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor); + + return EFI_SUCCESS; +} diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisili= con.dsc.inc index 308064b..dfa11d1 100644 --- a/Silicon/Hisilicon/Hisilicon.dsc.inc +++ b/Silicon/Hisilicon/Hisilicon.dsc.inc @@ -104,6 +104,15 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf =20 + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAu= thenticationLibPkcs7.inf + EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/Edk= iiSystemCapsuleLib.inf + IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf + PlatformFlashAccessLib|Silicon/Hisilicon/Library/PlatformFlashAccessLib/= PlatformFlashAccessLibDxe.inf + # # It is not possible to prevent the ARM compiler for generic intrinsic f= unctions. # This library provides the instrinsic functions generate by a given com= piler. @@ -198,7 +207,7 @@ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf - CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortRuntimeLib/Dw825= 0SerialPortRuntimeLib.inf DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/= PeiDxeDebugLibReportStatusCode.inf =20 diff --git a/Silicon/Hisilicon/Hisilicon.fdf.inc b/Silicon/Hisilicon/Hisili= con.fdf.inc index ee87cd1..986dd75 100644 --- a/Silicon/Hisilicon/Hisilicon.fdf.inc +++ b/Silicon/Hisilicon/Hisilicon.fdf.inc @@ -76,6 +76,15 @@ } } =20 +[Rule.Common.PEIM.FMP_IMAGE_DESC] + FILE PEIM =3D $(NAMED_GUID) { + RAW BIN |.acpi + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NU= MBER) + } + [Rule.Common.DXE_CORE] FILE DXE_CORE =3D $(NAMED_GUID) { PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi diff --git a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlash= AccessLibDxe.c b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformF= lashAccessLibDxe.c new file mode 100644 index 0000000..62da61c --- /dev/null +++ b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessL= ibDxe.c @@ -0,0 +1,123 @@ +/** @file + Platform Flash Access library. + + Copyright (c) 2018, Hisilicon Limited. All rights reserved. + Copyright (c) 2018, Linaro Limited. All rights reserved. + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress; +STATIC EFI_PHYSICAL_ADDRESS mSFCMEM0BaseAddress; + +STATIC HISI_SPI_FLASH_PROTOCOL *mSpiProtocol; + +/** + Perform flash write opreation. + + @param[in] FirmwareType The type of firmware. + @param[in] FlashAddress The address of flash device to be accessed. + @param[in] FlashAddressType The type of flash device address. + @param[in] Buffer The pointer to the data buffer. + @param[in] Length The length of data buffer in bytes. + + @retval EFI_SUCCESS The operation returns successfully. + @retval EFI_WRITE_PROTECTED The flash device is read only. + @retval EFI_UNSUPPORTED The flash device access is unsupported. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. +**/ +EFI_STATUS +EFIAPI +PerformFlashWrite ( + IN PLATFORM_FIRMWARE_TYPE FirmwareType, + IN EFI_PHYSICAL_ADDRESS FlashAddress, + IN FLASH_ADDRESS_TYPE FlashAddressType, + IN VOID *Buffer, + IN UINTN Length + ) +{ + UINT32 RomAddress; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, + "PerformFlashWrite - 0x%x(%x) - 0x%x\n", + (UINTN)FlashAddress, + (UINTN)FlashAddressType, + Length)); + + if (FlashAddressType =3D=3D FlashAddressTypeAbsoluteAddress) { + FlashAddress =3D FlashAddress - mInternalFdAddress; + } + + RomAddress =3D (UINT32)FlashAddress + (mInternalFdAddress - mSFCMEM0Base= Address); + + DEBUG ((DEBUG_INFO, "Erase and Write Flash Start\n")); + + Status =3D mSpiProtocol->EraseWrite ( + mSpiProtocol, + (UINT32) RomAddress, + (UINT8 *)Buffer, + (UINT32) Length + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Erase and Write Status =3D %r \n", Status)); + } + + return Status; +} + +/** + Platform Flash Access Lib Constructor. + + @param[in] ImageHandle The firmware allocated handle for the EFI = image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS Constructor returns successfully. +**/ +EFI_STATUS +EFIAPI +PerformFlashAccessLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mInternalFdAddress =3D (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdFdBaseAddress= ); + + mSFCMEM0BaseAddress =3D (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdSFCMEM0BaseA= ddress); + + DEBUG ((DEBUG_INFO, + "PcdFlashAreaBaseAddress - 0x%x, PcdSFCMEM0BaseAddress - 0x%x \n= ", + mInternalFdAddress, + mSFCMEM0BaseAddress)); + + Status =3D gBS->LocateProtocol ( + &gHisiSpiFlashProtocolGuid, + NULL, + (VOID **)&mSpiProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "LocateProtocol gHisiSpiFlashProtocolGuid Status =3D %r \n", + Status)); + } + + return Status; +} diff --git a/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlash= AccessLibDxe.inf b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/Platfor= mFlashAccessLibDxe.inf new file mode 100644 index 0000000..ba209c9 --- /dev/null +++ b/Silicon/Hisilicon/Library/PlatformFlashAccessLib/PlatformFlashAccessL= ibDxe.inf @@ -0,0 +1,51 @@ +## @file +# Platform Flash Access library. +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D PlatformFlashAccessLibDxe + FILE_GUID =3D c230e06c-c0d8-4935-8c23-9b8f7d33d1c4 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformFlashAccessLib|DXE_DRIVER + CONSTRUCTOR =3D PerformFlashAccessLibConstructor + +[Sources] + PlatformFlashAccessLibDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + SignedCapsulePkg/SignedCapsulePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + PcdLib + UefiBootServicesTableLib + +[Protocols] + gHisiSpiFlashProtocolGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress + +[Depex] + gHisiSpiFlashProtocolGuid --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 07 Feb 2018 00:24:38 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::243; helo=mail-pg0-x243.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SEEo2+dsW2gmvZPzsICoG5j6rysvV/rywmgZWs7BOhE=; b=juMMmfw6OV4362dQWDW4We+V15cK4avLzRaXCfUbXiON9EDlXmO3PecWBxyp4z4xsA jNM28Wb7ubwpAkYqSowEW7P88UpGIOEP0S4oxCkhaMDIEb5K7tqLjqVsJlBj3QdaPKjn dvhkeo41RkFtAXuiFgEzYrSWSnGunokClWWK4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SEEo2+dsW2gmvZPzsICoG5j6rysvV/rywmgZWs7BOhE=; b=jUJyRVB6gzkRys/xIuo5ZJT2OhKmOGQbVr0FMoB5egrEeFWiccYola/50dH2VOBVte 6lW9dyrXWVQ+Mv6UXo4eu25kegdM4gdhLaNaiKZaXNj5QnKZaNpm6rFM9SbcyqdmCe7E can+GZjFtz01Pa8D8F49rmP7VRlAOuKrh2i8zpCEQhSvPFdzg9xZm9VsH9XK/O+VB3hx TaNEUmDk/zGtDXKtZsY3Rv2h1AwvCOvl2YB8PcFhGJU1pKM8RKz/OgKL+haVa4eZGz7q RymOLhTV13wOT2531YtBWrmBG4LtNN8ekctxsuk2Tk/sTyukN7MZMGj4XJiWVgx4Acne niPw== X-Gm-Message-State: APf1xPCwuNQN9GCX+8aJWiLeJQ0LRQlSjmTIinajayYB8FeAvOf128KP CAGe7PsT2Ky//pINoMhBNrqARw== X-Google-Smtp-Source: AH8x226ieVVNnjvd2NHczrNJtCXAZyv+dYQKWh5mcyr4b1GUmSb4HRHllAztca1wqmNdo1isGAj0JQ== X-Received: by 10.98.217.141 with SMTP id b13mr5100061pfl.239.1517991879126; Wed, 07 Feb 2018 00:24:39 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:40 +0800 Message-Id: <1517991769-5485-7-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 06/15] Hisilicon D03/D05: Open SasPlatform source code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This module install a protocol for SasDriverDxe. the protocol include main information of sas controller, like controller ID, enable or disable,base address of registers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason Zhang Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Hisilicon/D03/D03.dsc | 1 + Platform/Hisilicon/D03/D03.fdf | 2 +- Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D05/D05.fdf | 2 +- Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c | 106 +++++++= +++++++++++++ Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf | 45 +++++++= ++ Silicon/Hisilicon/HisiPkg.dec | 2 + Silicon/Hisilicon/Include/Library/OemDevicePath.h | 52 +++++++= +++ Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h | 30 ++++++ 9 files changed, 239 insertions(+), 2 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 82c8bb4..07da597 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -468,6 +468,7 @@ Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf =20 + Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf =20 =20 diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 6462a53..919f9d7 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -272,7 +272,7 @@ READ_LOCK_STATUS =3D TRUE # INF Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf =20 - INF Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf + INF Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf =20 INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReport= Dxe.inf diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index e39acb1..b279c9e 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -621,6 +621,7 @@ Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugD= idVidToBmc.inf Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf + Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf =20 diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index b0296e1..b105ee2 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -294,7 +294,7 @@ READ_LOCK_STATUS =3D TRUE # INF Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - INF Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf + INF Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf =20 INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReport= Dxe.inf diff --git a/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c b/Silicon/= Hisilicon/Drivers/SasPlatform/SasPlatform.c new file mode 100644 index 0000000..7ae1f5d --- /dev/null +++ b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.c @@ -0,0 +1,106 @@ +/** @file +* +* Copyright (c) 2017, Hisilicon Limited. All rights reserved. +* Copyright (c) 2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define SAS0BusAddr 0xc3000000 +#define SAS1BusAddr 0xa2000000 +#define SAS2BusAddr 0xa3000000 + +#define SAS0ResetAddr 0xc0000000 +#define SAS1ResetAddr 0xa0000000 +#define SAS2ResetAddr 0xa0000000 + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + HISI_PLATFORM_SAS_PROTOCOL SasPlatformProtocol; +} SAS_PLATFORM_INSTANCE; + + +STATIC HISI_PLATFORM_SAS_PROTOCOL mSasPlatformProtocol[] =3D { + { + 0, + FALSE, + SAS0BusAddr, + SAS0ResetAddr + }, + { + 1, + TRUE, + SAS1BusAddr, + SAS1ResetAddr + }, + { + 2, + FALSE, + SAS2BusAddr, + SAS2ResetAddr + } +}; + +EFI_STATUS +EFIAPI +SasPlatformInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINTN Loop; + SAS_PLATFORM_INSTANCE *PrivateData; + EFI_STATUS Status; + + for (Loop =3D 0; Loop < ARRAY_SIZE (mSasPlatformProtocol); Loop++) { + if (mSasPlatformProtocol[Loop].Enable !=3D TRUE) { + continue; + } + PrivateData =3D AllocateZeroPool (sizeof(SAS_PLATFORM_INSTANCE)); + if (PrivateData =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PrivateData->SasPlatformProtocol =3D mSasPlatformProtocol[Loop]; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &PrivateData->Handle, + &gHisiPlatformSasProtocolGuid, + &PrivateData->SasPlatformProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (PrivateData); + DEBUG ((DEBUG_ERROR, + "[%a]:[%dL] InstallProtocolInterface fail. %r\n", + __FUNCTION__, + __LINE__, + Status)); + continue; + } + } + + DEBUG ((DEBUG_INFO, "sas platform init driver Ok!!!\n")); + return EFI_SUCCESS; +} + diff --git a/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf b/Silico= n/Hisilicon/Drivers/SasPlatform/SasPlatform.inf new file mode 100644 index 0000000..fe33623 --- /dev/null +++ b/Silicon/Hisilicon/Drivers/SasPlatform/SasPlatform.inf @@ -0,0 +1,45 @@ +#/** @file +# +# Copyright (c) 2017, Hisilicon Limited. All rights reserved. +# Copyright (c) 2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the= BSD License +# which accompanies this distribution. The full text of the license may= be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D SasPlatform + FILE_GUID =3D 67B9CDE8-257D-44f9-9DE7-39DE866E3539 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SasPlatformInitialize + +[Sources] + SasPlatform.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DxeServicesTableLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gHisiPlatformSasProtocolGuid + +[Depex] + TRUE diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec index 889a181..4c9d379 100644 --- a/Silicon/Hisilicon/HisiPkg.dec +++ b/Silicon/Hisilicon/HisiPkg.dec @@ -37,6 +37,7 @@ gBmcInfoProtocolGuid =3D {0x43fa6ffd, 0x35e4, 0x479e, {0xab, 0xec, 0x5, = 0x3, 0xf6, 0x48, 0x0, 0xf5}} gSataEnableFlagProtocolGuid =3D {0xc2b3c770, 0x8b4a, 0x4796, {0xb2, 0xcf= , 0x1d, 0xee, 0x44, 0xd0, 0x32, 0xf3}} gPlatformSasProtocolGuid =3D {0x40e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0= x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}} + gHisiPlatformSasProtocolGuid =3D {0x20e9829f, 0x3a2c, 0x479a, {0x9a, 0x9= 3, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x6d}} =20 [Guids] gHisiTokenSpaceGuid =3D {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, = 0xf7, 0x7c, 0xfd, 0x52, 0x1d}} @@ -44,6 +45,7 @@ gHisiEfiMemoryMapGuid =3D {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xb= d, 0x56, 0xda, 0x91, 0xc0, 0x7f}} gVersionInfoHobGuid =3D {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0= xe, 0xe1, 0x42, 0x12, 0xbf}} gOemBootVariableGuid =3D {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4,= 0xa4, 0x2f, 0x45, 0x06, 0xf8}} + gEfiHisiSocControllerGuid =3D {0xee369cc3, 0xa743, 0x5382, {0x75, 0x64, = 0x53, 0xe4, 0x31, 0x19, 0x38, 0x35}} =20 [LibraryClasses] PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h diff --git a/Silicon/Hisilicon/Include/Library/OemDevicePath.h b/Silicon/Hi= silicon/Include/Library/OemDevicePath.h new file mode 100644 index 0000000..9d66c21 --- /dev/null +++ b/Silicon/Hisilicon/Include/Library/OemDevicePath.h @@ -0,0 +1,52 @@ +/** @file +* +* Copyright (c) 2015 - 2017, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef _OEM_DEVICE_PATH_H_ +#define _OEM_DEVICE_PATH_H_ +#include + +typedef enum +{ + C_NIC =3D 1, + C_SATA =3D 2, + C_SAS =3D 3, + C_USB =3D 4, +} CONTROLLER_TYPE; + +typedef struct{ + VENDOR_DEVICE_PATH Vender; + UINT8 ControllerType; + UINT8 Socket; + UINT8 Port; +} EXT_VENDOR_DEVICE_PATH; + +typedef struct{ + UINT16 BootIndex; + UINT16 Port; +} SATADES; + +typedef struct{ + UINT16 BootIndex; + UINT16 ParentPortNumber; + UINT16 InterfaceNumber; +} USBDES; + +typedef struct{ + UINT16 BootIndex; + UINT16 Port; +} PXEDES; + +#endif + diff --git a/Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h b= /Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h new file mode 100644 index 0000000..b5edb99 --- /dev/null +++ b/Silicon/Hisilicon/Include/Protocol/HisiPlatformSasProtocol.h @@ -0,0 +1,30 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef _HISI_PLATFORM_SAS_PROTOCOL_H_ +#define _HISI_PLATFORM_SAS_PROTOCOL_H_ + +typedef struct _HISI_PLATFORM_SAS_PROTOCOL HISI_PLATFORM_SAS_PROTOCOL; + +struct _HISI_PLATFORM_SAS_PROTOCOL { + UINT32 ControllerId; + BOOLEAN Enable; + UINT64 BaseAddr; + UINT64 ResetAddr; +}; + +extern EFI_GUID gHisiPlatformSasProtocolGuid; + +#endif --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151799189320118.393766305889812; Wed, 7 Feb 2018 00:24:53 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 85B992215BDB8; Wed, 7 Feb 2018 00:19:08 -0800 (PST) Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F1580223972C4 for ; Wed, 7 Feb 2018 00:19:06 -0800 (PST) Received: by mail-pl0-x242.google.com with SMTP id j19so44305pll.2 for ; Wed, 07 Feb 2018 00:24:50 -0800 (PST) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id k127sm1984999pga.92.2018.02.07.00.24.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Feb 2018 00:24:49 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mEpMw8OlgS8J5OB5sN20klJpR3sganuIq7hXFvMhPcE=; b=RIM8fAblUGcLbMxyrOjFnKppUr76Dj3XGza4UeU47CWMC2FXAiBZ965+zsDvCjHFF1 hYQfiOtaMoKtahDM3K+DlPRxUybEBerJULw1es/CsHmDJmk93CQF/ZwL3/3GFjIJnn4V QdoqW433ppL1fzXJ6GVCqTTrj+wzD+1HBDlC4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mEpMw8OlgS8J5OB5sN20klJpR3sganuIq7hXFvMhPcE=; b=f/Nh+xaEJDUrvsq6AW7i9Ol8Ku4Ii1oB8Bw5cGeEHc+okpGyezaM4v2Fom/6aPjJS+ fROVkCAmYkxmKrT4GBIR9tGmT2XDsj9QX5uSL1/sJOD1v1WXgukqzrWHibR6T4gw/uvB n8Ps6SeWsHOmjNNasvWPhBsSiYB2pu2mKov8hBZnGqHD87SFeT/84fi2jSYShpoZF/6U SjD4fmWb6abe5eoKz90mELxg8oTo1eeFwuKsrb2VoHKRRGco2Zfi5e7u03VjX7uAVpZC x+pID1GqSzA2Yanf/U95Chm2eyP4V84qIi2ARxaPnU9tyVceReOleYzfFFVddd6nT0Xj 6gsw== X-Gm-Message-State: APf1xPAy96BRZmu2AT0qs9lywmXud2KuJrjKauJFWEDdxjqz7pFw6o8d +8b6w7QELSTLpNJBgK4SAZDN5w== X-Google-Smtp-Source: AH8x227qakutyt6DthNy/kKqbjlXWW62ThXspoX3F9Dxwt06ns1j3zkx/y4+oNhXoifCUgRPZdnH2g== X-Received: by 2002:a17:902:aa8e:: with SMTP id d14-v6mr5087726plr.94.1517991890326; Wed, 07 Feb 2018 00:24:50 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:41 +0800 Message-Id: <1517991769-5485-8-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 07/15] Hisilicon D03/D05: Open SnpPlatform source code X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" 1. This driver install a protocol for SnpPV600Dxe driver. The protocol indicate which ethernet port to use and port sequence. 2. Fixed bug:Confusing Ethernet port sequence. Move the most right Ethernet port (when looking from the front of the chassis) to the first one in BootManage for PXE boot. https://bugs.linaro.org/show_bug.cgi?id=3D2657 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason Zhang Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Hisilicon/D03/D03.dsc | 2 + Platform/Hisilicon/D03/D03.fdf | 2 +- Platform/Hisilicon/D05/D05.dsc | 2 + Platform/Hisilicon/D05/D05.fdf | 2 +- Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c | 115 +++++++++++= +++++++++ Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf | 46 ++++++++ Silicon/Hisilicon/HisiPkg.dec | 1 + Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h | 32 ++++++ 8 files changed, 200 insertions(+), 2 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 07da597..947a8a5 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -399,6 +399,8 @@ =20 Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf =20 + Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 919f9d7..1c55761 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -242,7 +242,7 @@ READ_LOCK_STATUS =3D TRUE #Network # =20 - INF Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf + INF Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf INF Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf =20 INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index b279c9e..6e44041 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -537,6 +537,8 @@ =20 Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf =20 + Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf + MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index b105ee2..e829494 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -248,7 +248,7 @@ READ_LOCK_STATUS =3D TRUE #Network # =20 - INF Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf + INF Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf INF Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf =20 INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf diff --git a/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c b/Silicon/= Hisilicon/Drivers/SnpPlatform/SnpPlatform.c new file mode 100644 index 0000000..0d6e86e --- /dev/null +++ b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.c @@ -0,0 +1,115 @@ +/** @file +* +* Copyright (c) 2017, Hisilicon Limited. All rights reserved. +* Copyright (c) 2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + HISI_PLATFORM_SNP_PROTOCOL SnpPlatformProtocol; +} SNP_PLATFORM_INSTANCE; + +STATIC HISI_PLATFORM_SNP_PROTOCOL mSnpPlatformProtocol[] =3D { + { + 4, + 1 + }, + { + 5, + 1 + }, + { + 2, + 0 + }, + { + 3, + 0 + }, + { + 0, + 1 + }, + { + 1, + 1 + }, + { + 6, + 0 + }, + { + 7, + 0 + } +}; + + +EFI_STATUS +EFIAPI +SnpPlatformInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINTN Loop; + SNP_PLATFORM_INSTANCE *PrivateData; + EFI_STATUS Status; + + for (Loop =3D 0; Loop < ARRAY_SIZE (mSnpPlatformProtocol); Loop++) { + if(mSnpPlatformProtocol[Loop].Enable !=3D 1) { + continue; + } + PrivateData =3D AllocateZeroPool (sizeof(SNP_PLATFORM_INSTANCE)); + if (PrivateData =3D=3D NULL) { + DEBUG ((DEBUG_INFO,"SnpPlatformInitialize error 1\n")); + return EFI_OUT_OF_RESOURCES; + } + + + PrivateData->SnpPlatformProtocol =3D mSnpPlatformProtocol[Loop]; + + // + // Install the snp protocol, device path protocol + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &PrivateData->Handle, + &gHisiSnpPlatformProtocolGuid, + &PrivateData->SnpPlatformProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (PrivateData); + DEBUG ((DEBUG_ERROR, "InstallProtocolInterface fail. %r\n", Status)); + continue; + } + } + + DEBUG ((DEBUG_INFO,"SnpPlatformInitialize succes!\n")); + + return EFI_SUCCESS; +} diff --git a/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf b/Silico= n/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf new file mode 100644 index 0000000..3301abf --- /dev/null +++ b/Silicon/Hisilicon/Drivers/SnpPlatform/SnpPlatform.inf @@ -0,0 +1,46 @@ +#/** @file +# +# Copyright (c) 2017, Hisilicon Limited. All rights reserved. +# Copyright (c) 2017, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the= BSD License +# which accompanies this distribution. The full text of the license may= be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D SnpPlatform + FILE_GUID =3D 102D8FC9-20A4-42eb-AC14-1C98BA5B17A8 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SnpPlatformInitialize + +[Sources] + SnpPlatform.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DxeServicesTableLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gHisiSnpPlatformProtocolGuid + +[Depex] + TRUE + diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec index 4c9d379..35bea97 100644 --- a/Silicon/Hisilicon/HisiPkg.dec +++ b/Silicon/Hisilicon/HisiPkg.dec @@ -38,6 +38,7 @@ gSataEnableFlagProtocolGuid =3D {0xc2b3c770, 0x8b4a, 0x4796, {0xb2, 0xcf= , 0x1d, 0xee, 0x44, 0xd0, 0x32, 0xf3}} gPlatformSasProtocolGuid =3D {0x40e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0= x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}} gHisiPlatformSasProtocolGuid =3D {0x20e9829f, 0x3a2c, 0x479a, {0x9a, 0x9= 3, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x6d}} + gHisiSnpPlatformProtocolGuid =3D {0x81321f27, 0xff58, 0x4a1d, {0x99, 0x9= 7, 0xd, 0xcc, 0xfa, 0x82, 0xf4, 0x6f}} =20 [Guids] gHisiTokenSpaceGuid =3D {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, = 0xf7, 0x7c, 0xfd, 0x52, 0x1d}} diff --git a/Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h b/Sil= icon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h new file mode 100644 index 0000000..0d9f0b4 --- /dev/null +++ b/Silicon/Hisilicon/Include/Protocol/SnpPlatformProtocol.h @@ -0,0 +1,32 @@ +/** @file +* +* Copyright (c) 2017, Hisilicon Limited. All rights reserved. +* Copyright (c) 2017, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef _SNP_PLATFORM_PROTOCOL_H_ +#define _SNP_PLATFORM_PROTOCOL_H_ +#define HISI_SNP_PLATFORM_PROTOCOL_GUID \ + { \ + 0x81321f27, 0xff58, 0x4a1d, 0x99, 0x97, 0xd, 0xcc, 0xfa, 0x82, 0xf4, 0= x6f \ + } + +typedef struct _HISI_PLATFORM_SNP_PROTOCOL HISI_PLATFORM_SNP_PROTOCOL; + +struct _HISI_PLATFORM_SNP_PROTOCOL { + UINT32 ControllerId; + UINT32 Enable; +}; + +extern EFI_GUID gHisiSnpPlatformProtocolGuid; + +#endif --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; 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Wed, 07 Feb 2018 00:25:09 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:42 +0800 Message-Id: <1517991769-5485-9-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 08/15] Hilisicon: Change DmaLib to CoherentDmaLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Wang Yue , Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Unify all D0x(include D06 in further) to cache coherent DmaLib. This can improve boot speed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wang Yue Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Hisilicon/D05/D05.dsc | 2 +- Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c | 2 +- Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 6e44041..dfe19b0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -614,7 +614,7 @@ Platform/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf } =20 diff --git a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c = b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c index 706eb12..63de50b 100644 --- a/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c +++ b/Silicon/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.c @@ -26,7 +26,7 @@ EhciVirtualPciIoInitialize ( { return RegisterNonDiscoverableMmioDevice ( NonDiscoverableDeviceTypeEhci, - NonDiscoverableDeviceDmaTypeNonCoherent, + NonDiscoverableDeviceDmaTypeCoherent, NULL, NULL, 1, diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c b/Silic= on/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c index 2310ee4..3e272f8 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.c @@ -27,7 +27,6 @@ ExitBootServicesEventSmmu ( IN VOID *Context ) { - SmmuConfigForOS (); DEBUG((EFI_D_INFO,"SMMU ExitBootServicesEvent\n")); } =20 @@ -43,7 +42,7 @@ IoInitDxeEntry ( =20 (VOID) EfiSerdesInitWrap (); =20 - SmmuConfigForBios (); + SmmuConfigForOS (); =20 Status =3D gBS->CreateEvent ( EVT_SIGNAL_EXIT_BOOT_SERVICES, --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1517991925587252.67082697892863; Wed, 7 Feb 2018 00:25:25 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E2E2D21F0DA75; Wed, 7 Feb 2018 00:19:40 -0800 (PST) Received: from mail-pg0-x243.google.com (mail-pg0-x243.google.com [IPv6:2607:f8b0:400e:c05::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D626921F0DA6F for ; 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charset="utf-8" modify processorFamily of type 4 to ProcessorFamilyIndicatorFamily2, indicator to obtain the processor family from the Processor Family 2 field. ProcessorFamily2 is already specified as ProcessorFamilyARM in the existing table. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c = | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/Processo= rSubClass.c b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/Process= orSubClass.c index 61473e8..c9903ba 100644 --- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubCla= ss.c +++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubCla= ss.c @@ -125,7 +125,7 @@ SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] =3D { }, 1, //Socket CentralProcessor, //ProcessorType - ProcessorFamilyOther, //ProcessorFamily + ProcessorFamilyIndicatorFamily2, //ProcessorFamily 2, //ProcessorManufac= ture { //ProcessorId { //Signature @@ -172,7 +172,7 @@ SMBIOS_TABLE_TYPE4 mSmbiosProcessorTable[] =3D { }, 1, //Socket CentralProcessor, //ProcessorType - ProcessorFamilyOther, //ProcessorFamily + ProcessorFamilyIndicatorFamily2, //ProcessorFamily 2, //ProcessorManufac= ture { //ProcessorId { //Signature --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" In order to replace command line parameter pcie_aspm=3Doff, BIOS needs to disable Pcie Aspm support during Pcie initilization. D03 and D05 do not support PCIe ASPM, so we disable it in BIOS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Signed-off-by: Yan Zhang Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 103 ++++++++= ++++++++++++ Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 + 3 files changed, 107 insertions(+) diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/= Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index f420c91..c1c3fbb 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -1033,6 +1033,106 @@ DisableRcOptionRom ( return; } =20 +STATIC +VOID +PcieDbiCs2Enable ( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN BOOLEAN Val + ) +{ + UINT32 RegVal; + + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_S= YS_CTRL21, + RegVal + ); + if (Val) { + RegVal =3D RegVal | BIT2; + /* BIT2: DBI Chip Select indicator. 0 indicates CS, 1 indicates CS2.*/ + } else { + RegVal =3D RegVal & (~BIT2); + } + RegWrite ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_S= YS_CTRL21, + RegVal + ); +} + +STATIC +BOOLEAN +PcieDBIReadOnlyWriteEnable ( + IN UINT32 HostBridgeNum, + IN UINT32 Port + ) +{ + UINT32 Val; + + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRI= TE_ENABLE, + Val + ); + if (Val =3D=3D 0x1) { + return TRUE; + } else { + RegWrite ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_W= RITE_ENABLE, + 0x1 + ); + /* Delay 10us to make sure the PCIE device have enouph time to respons= e. */ + MicroSecondDelay(10); + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_W= RITE_ENABLE, + Val + ); + if (Val =3D=3D 0x1) { + return TRUE; + } + } + DEBUG ((DEBUG_ERROR,"PcieDBIReadOnlyWriteEnable Fail!!!\n")); + return FALSE; +} + +STATIC +VOID +SwitchPcieASPMSupport ( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN UINT8 Val + ) +{ + PCIE_EP_PCIE_CAP3_U PcieCap3; + + if (Port >=3D PCIE_MAX_ROOTBRIDGE) { + DEBUG ((DEBUG_ERROR, "Port is not valid\n")); + return; + } + if (!PcieDBIReadOnlyWriteEnable (HostBridgeNum, Port)) { + DEBUG ((DEBUG_INFO, "PcieDBI ReadOnly Reg do not Enable!!!\n")); + return; + } + PcieDbiCs2Enable (HostBridgeNum, Port, FALSE); + + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, + PcieCap3.UInt32 + ); + PcieCap3.Bits.active_state_power_management =3D Val; + RegWrite ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, + PcieCap3.UInt32 + ); + RegRead ( + PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, + PcieCap3.UInt32 + ); + DEBUG ((DEBUG_INFO, + "ASPI active state power management: %d\n", + PcieCap3.Bits.active_state_power_management)); + + PcieDbiCs2Enable (HostBridgeNum, Port, TRUE); +} + EFI_STATUS EFIAPI PciePortInit ( @@ -1090,6 +1190,9 @@ PciePortInit ( /* disable link up interrupt */ (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex); =20 + /* disable ASPM */ + SwitchPcieASPMSupport (HostBridgeNum, PortIndex, PCIE_ASPM_DISABLE); + /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex); =20 diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/= Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9a0f636..e96c53c 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -77,6 +77,8 @@ #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) =3D MmioRead32 (addr)) =20 +#define PCIE_ASPM_DISABLE 0x0 +#define PCIE_ASPM_ENABLE 0x1 =20 typedef struct tagPcieDebugInfo { diff --git a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Silicon= /Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index bf57652..c8b9781 100644 --- a/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Silicon/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -135,6 +135,7 @@ #define PCIE_EEP_PORTLOGIC53_REG (0x888) #define PCIE_EEP_GEN3_CONTRL_REG (0x890) #define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8) +#define PCIE_DBI_READ_ONLY_WRITE_ENABLE (0x8BC) #define PCIE_EEP_PORTLOGIC54_REG (0x900) #define PCIE_EEP_PORTLOGIC55_REG (0x904) #define PCIE_EEP_PORTLOGIC56_REG (0x908) @@ -12556,6 +12557,7 @@ typedef union tagPortlogic93 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_B= ASE + 0x1018) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_B= ASE + 0x101C) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_B= ASE + 0x1020) +#define PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21 (PCIE_SUBCTRL_B= ASE + 0x1024) #define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_B= ASE + 0x1030) #define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_B= ASE + 0x1100) #define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_B= ASE + 0x1104) --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, GongChengYa , guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In SCT test,we find SP805 watchdog driver can't reset when timeout so we use another driver in MdeModulePkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Signed-off-by: GongChengYa Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Hisilicon/D05/D05.dsc | 2 +- Platform/Hisilicon/D05/D05.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index dfe19b0..b2ccd0e 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -511,7 +511,7 @@ =20 ArmPkg/Drivers/TimerDxe/TimerDxe.inf =20 - ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntim= eDxe.inf # #ACPI diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index e829494..22609bb 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -193,7 +193,7 @@ READ_LOCK_STATUS =3D TRUE INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf =20 - INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf =20 # # FAT filesystem + GPT/MBR partitioning --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151799195082241.35724125886611; Wed, 7 Feb 2018 00:25:50 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2E4C62222C232; Wed, 7 Feb 2018 00:20:06 -0800 (PST) Received: from mail-pg0-x242.google.com (mail-pg0-x242.google.com [IPv6:2607:f8b0:400e:c05::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 15B29223972A1 for ; Wed, 7 Feb 2018 00:20:03 -0800 (PST) Received: by mail-pg0-x242.google.com with SMTP id s73so21325pgc.1 for ; Wed, 07 Feb 2018 00:25:47 -0800 (PST) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id k127sm1984999pga.92.2018.02.07.00.25.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 07 Feb 2018 00:25:47 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::242; helo=mail-pg0-x242.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mOf0EEDq8uz8RBUZlymJpLBJViqRMXp4zhYvu6zU5YE=; b=WhBX7oQNi/mPkbwwF1tDy73pkRkMCBLZ3+4OPlONadqfBPzXYOEl60KqtU5YRsLZ64 4ZYkQrTmU/o0QSow5/jrqH2La3Ejp/ngaqb6QWkNeiyQu+Jmvj936kgLfD0F1RnMoOAs OGkxBnS96ROryaEI349+fRg81j8K3GzjjDjzQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mOf0EEDq8uz8RBUZlymJpLBJViqRMXp4zhYvu6zU5YE=; b=YVUe4Q9QfJUP8PlV59Xwn1oWW1L4wQFp4wp7woujVtpe9v0M6vVEqGspvqL2lgZaLO Hv42h60/UUkzbPTteMqDSBnQXTNweUnZLIsnGUB+RmdXPp+hdqGXRTG+iRyy28Y/dYik cm/C6yh20psjhNKWyPHwlwovQYtLCZuaBNQhT4vmreJSiZM8Sf5Vu4l17gfA2SUJDrtO von70E6pkkSEOwd9AlvrYqesjnzrRP64iq2xVrX+eSY0z2ctk4ha7qYc5unqtPvoUmp9 8WmaRavoflScLWYlna/ZDs9rQPZcaJEgPjWsNZxj3jzdrBwO91HE975DRLYBKN1icxhr ZPLA== X-Gm-Message-State: APf1xPDeeMlWka8+0ykSB2wly0rB74+LsSML9MZI9mV7GCOh+h348NgT rSX/Icy2IYFx3Z59iC/NpoeaNQ== X-Google-Smtp-Source: AH8x224o1rluIRDq01MTHaXdOHItSMWCunX0fcHXrKnrXQr6Sz0Nz7NiTwGE+OYWrVaBOVqGFmIzZg== X-Received: by 10.99.126.89 with SMTP id o25mr4173942pgn.94.1517991947496; Wed, 07 Feb 2018 00:25:47 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:46 +0800 Message-Id: <1517991769-5485-13-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 12/15] Hisilicon/D03: Replace SP805Watchdog by WatchdogTimer driver. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, GongChengYa , guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In SCT test,we find SP805 watchdog driver can't reset when timeout so we use another driver in MdeModulePkg. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Signed-off-by: GongChengYa Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel --- Platform/Hisilicon/D03/D03.dsc | 2 +- Platform/Hisilicon/D03/D03.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 947a8a5..37bec9e 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -374,7 +374,7 @@ =20 ArmPkg/Drivers/TimerDxe/TimerDxe.inf =20 - ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntim= eDxe.inf # #ACPI diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index 1c55761..e6a4820 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -189,7 +189,7 @@ READ_LOCK_STATUS =3D TRUE INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf =20 - INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf =20 # # FAT filesystem + GPT/MBR partitioning --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Add ITS affinity structure in SRAT. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm Reviewed-by: Graeme Gregory --- Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc | 10 ++++++++++ Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 10 +++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Silicon/= Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc index b448a29..8ea0c4b 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc @@ -121,6 +121,16 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat =3D { EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x0000= 0001,0x00000000), //GICC Affinity Processor 62 EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x0000= 0001,0x00000000) //GICC Affinity Processor 63 }, + { + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000000, 0x00000000), + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000001), + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000000, 0x00000002), + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000003), + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000002, 0x00000004), + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000005), + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000002, 0x00000006), + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000007) + }, }; =20 // diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h b/Silicon/Hisi= licon/Include/Library/AcpiNextLib.h index 60f9925..fd05a3b 100644 --- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h +++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h @@ -39,6 +39,13 @@ ACPIProcessorUID, Flags, ClockDomain = \ } =20 +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT( = \ + ProximityDomain, ItsId) = \ + { = \ + 4, sizeof (EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE), ProximityDomain, = \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, ItsId = \ + } + #define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( = \ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHig= h, Flags) \ { = \ @@ -70,12 +77,13 @@ // #define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT 64 #define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10 - +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8 =20 typedef struct { EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE Memory[EFI_A= CPI_MEMORY_AFFINITY_STRUCTURE_COUNT]; EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACP= I_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT]; + EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE Its[EFI_ACPI= _6_2_ITS_AFFINITY_STRUCTURE_COUNT]; } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE; =20 #pragma pack() --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1517991971627875.8052659229052; Wed, 7 Feb 2018 00:26:11 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F23D621F0DA7F; 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Wed, 07 Feb 2018 00:26:08 -0800 (PST) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Wed, 7 Feb 2018 16:22:48 +0800 Message-Id: <1517991769-5485-15-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> References: <1517991769-5485-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 14/15] Hisilicon/D05/ACPI: Add Pcie, HNS and SAS PXM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com, huangdaode@hisilicon.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add PXM method for Pcie device, HNS device and SAS device. Add STA method for HNS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: hensonwang Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm Reviewed-by: Graeme Gregory --- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl | 9 ++++++ Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 34 ++++++++++++++= ++++-- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 19 +++++++++-- 3 files changed, 57 insertions(+), 5 deletions(-) diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Silic= on/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl index 11c28ba..7aa04af 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl @@ -233,6 +233,15 @@ Scope(_SB) } }) =20 + Method (_PXM, 0, NotSerialized) + { + Return(0x00) + } + Method (_STA, 0, NotSerialized) + { + Return(0x0F) + } + //reset XGE port //Arg0 : XGE port index in dsaf //Arg1 : 0 reset, 1 cancle reset diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silic= on/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 55c7f50..122e4f0 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -141,7 +141,10 @@ Scope(_SB) { Return (0xf) } - + Method (_PXM, 0, NotSerialized) + { + Return(0x00) + } } // Device(PCI2) =20 Device (RES2) @@ -240,7 +243,10 @@ Scope(_SB) { Return (RBYV()) } - + Method (_PXM, 0, NotSerialized) + { + Return(0x01) + } } // Device(PCI4) Device (RES4) { @@ -338,6 +344,10 @@ Scope(_SB) { Return (RBYV()) } + Method (_PXM, 0, NotSerialized) + { + Return(0x01) + } } // Device(PCI5) Device (RES5) { @@ -435,6 +445,10 @@ Scope(_SB) { Return (RBYV()) } + Method (_PXM, 0, NotSerialized) + { + Return(0x01) + } } // Device(PCI6) Device (RES6) { @@ -531,6 +545,10 @@ Scope(_SB) { Return (RBYV()) } + Method (_PXM, 0, NotSerialized) + { + Return(0x01) + } } // Device(PCI7) Device (RES7) { @@ -690,6 +708,10 @@ Scope(_SB) { Return (0xf) } + Method (_PXM, 0, NotSerialized) + { + Return(0x02) + } } // Device(PCIa) Device (RESa) { @@ -810,6 +832,10 @@ Scope(_SB) { Return (RBYV()) } + Method (_PXM, 0, NotSerialized) + { + Return(0x03) + } } // Device(PCIc) =20 Device (RESc) @@ -907,6 +933,10 @@ Scope(_SB) { Return (RBYV()) } + Method (_PXM, 0, NotSerialized) + { + Return(0x03) + } } // Device(PCId) Device (RESd) { diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Silic= on/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl index 6455130..d5b7e2f 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -88,7 +88,10 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } - + Method (_PXM, 0, NotSerialized) + { + Return(0x00) + } Method (_STA, 0, NotSerialized) { Return (0x0) @@ -169,8 +172,15 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } + Method (_PXM, 0, NotSerialized) + { + Return(0x00) + } + Method (_STA, 0, NotSerialized) + { + Return(0x0F) + } } - Device(SAS2) { Name(_HID, "HISI0162") Name(_CCA, 1) @@ -244,7 +254,10 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } - + Method (_PXM, 0, NotSerialized) + { + Return(0x00) + } Method (_STA, 0, NotSerialized) { Return (0x0) --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 04:03:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Replace the old string with short one. The old one is too long that can not be show integrallty in Setup nemu. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm Reviewed-by: Ard Biesheuvel Reviewed-by: Graeme Gregory --- Platform/Hisilicon/D03/D03.dsc | 2 +- Platform/Hisilicon/D05/D05.dsc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 37bec9e..c496306 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -168,7 +168,7 @@ !ifdef $(FIRMWARE_VER) gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_V= ER)" !else - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development = build base on Hisilicon D03 UEFI 17.10 Release" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development = build 18.02 for Hisilicon D03" !endif =20 gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index b2ccd0e..0792b08 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -187,7 +187,7 @@ !ifdef $(FIRMWARE_VER) gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_V= ER)" !else - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development = build base on Hisilicon D05 UEFI 17.10 Release" + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development = build 18.02 for Hisilicon D05" !endif =20 gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel