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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB2354 Subject: [edk2] [PATCH edk2-platforms 1/3] USB: Added Support of DWC3 USB controller. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Added library for DWC3 USB controller and enabled USB support in pci emulation layer. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- .../NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c | 25 +++++++++++++++++++ .../NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf | 28 ++++++++++++++++++= ++++ Platform/NXP/NxpQoriqLs.dsc | 9 +++++++ 3 files changed, 62 insertions(+) create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c create mode 100644 Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf diff --git a/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c b/Platf= orm/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c new file mode 100644 index 0000000..51a9b16 --- /dev/null +++ b/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdLibNull.c @@ -0,0 +1,25 @@ +/** @file + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include + +EFI_STATUS +EFIAPI +InitializeUsbController ( + IN UINTN UsbReg + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf b/Platfo= rm/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf new file mode 100644 index 0000000..76a414e --- /dev/null +++ b/Platform/NXP/Library/UsbHcdNullLibrary/UsbHcdNull.inf @@ -0,0 +1,28 @@ +# UsbHcdNull.inf +# NULL Library fr DWC3 +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +*/ + +[Defines] + INF_VERSION =3D 0x0001000A + BASE_NAME =3D UsbHcdNull + FILE_GUID =3D 0946b308-9ac9-4e01-b4ec-e6e4d72991ec + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D UsbHcdLib + +[Sources.common] + UsbHcdLibNull.c + +[Packages] + MdePkg/MdePkg.dec diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc index 54f0c2c..9b450fa 100644 --- a/Platform/NXP/NxpQoriqLs.dsc +++ b/Platform/NXP/NxpQoriqLs.dsc @@ -392,6 +392,15 @@ FatPkg/EnhancedFatDxe/Fat.inf =20 # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # # Bds # MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun May 5 01:30:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB0733 Subject: [edk2] [PATCH edk2-platforms 2/3] PciEmulation : Add support for Pci Emulation layer. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============8410973760582140696==" Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 --===============8410973760582140696== Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" SATA and USB will use this pci emulation layer Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Platform/NXP/Drivers/PciEmulation/PciEmulation.c | 624 +++++++++++++++++= ++++ Platform/NXP/Drivers/PciEmulation/PciEmulation.h | 306 ++++++++++ Platform/NXP/Drivers/PciEmulation/PciEmulation.inf | 54 ++ .../NXP/Drivers/PciEmulation/PciRootBridgeIo.c | 286 ++++++++++ Platform/NXP/NxpQoriqLs.dec | 9 +- 5 files changed, 1277 insertions(+), 2 deletions(-) create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.c create mode 100755 Platform/NXP/Drivers/PciEmulation/PciEmulation.h create mode 100644 Platform/NXP/Drivers/PciEmulation/PciEmulation.inf create mode 100644 Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c diff --git a/Platform/NXP/Drivers/PciEmulation/PciEmulation.c b/Platform/NX= P/Drivers/PciEmulation/PciEmulation.c new file mode 100644 index 0000000..6635eb4 --- /dev/null +++ b/Platform/NXP/Drivers/PciEmulation/PciEmulation.c @@ -0,0 +1,624 @@ +/** PciEmulation.c + Provides all functions of PCI Host Bridge Resource Allocation Protocol + + Reference taken from PCI Emulation implementation in + Omap35xxPkg/PciEmulation/ + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "PciEmulation.h" + +EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =3D +{ + { + { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } }, + EISA_PNP_ID(0x0A03), // HID + 0 // UID + }, + { + { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } }, + 0, + 0 + }, + { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DE= VICE_PATH_PROTOCOL), 0} } +}; + +EFI_STATUS +PciIoPollMem ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoMemRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + + Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + + return PciRootBridgeIoMemRead (&Private->RootBridge.Io, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) W= idth, + Private->ConfigSpace->Device.Bar[0] + Off= set, + Count, + Buffer + ); +} + +EFI_STATUS +PciIoMemWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + + Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + + return PciRootBridgeIoMemWrite (&Private->RootBridge.Io, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) = Width, + Private->ConfigSpace->Device.Bar[0] + Of= fset, + Count, + Buffer + ); +} + +EFI_STATUS +PciIoIoWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +/** + Enable a PCI driver to read PCI controller registers in PCI configuratio= n space. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL ins= tance. + @param[in] Width Signifies the width of the memory operat= ions. + @param[in] Offset The offset within the PCI configuration = space for + the PCI controller. + @param[in] Count The number of PCI configuration operatio= ns to + perform. Bytes moved is Width size * Cou= nt, + starting at Offset. + + @param[in out] Buffer The destination buffer to store the resu= lts. + + @retval EFI_SUCCESS The data was read from the PCI controlle= r. + @retval EFI_INVALID_PARAMETER "Width" is invalid. + @retval EFI_INVALID_PARAMETER "Buffer" is NULL. + +**/ +EFI_STATUS +PciIoPciRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT32 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + EFI_STATUS Status; + UINT64 Address; + + Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + + if ((Width < 0) || (Width >=3D EfiPciIoWidthMaximum) || (Buffer =3D=3D N= ULL)) { + return EFI_INVALID_PARAMETER; + } + + Address =3D (UINT64)((UINT8 *)Private->ConfigSpace + Offset); + Status =3D PciRootBridgeIoMemRW (FALSE, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Wi= dth, + Address, + Count, + Buffer + ); + + return Status; +} + +/** + Enable a PCI driver to write PCI controller registers in PCI configurati= on space. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL ins= tance. + @param[in] Width Signifies the width of the memory operat= ions. + @param[in] Offset The offset within the PCI configuration = space for + the PCI controller. + @param[in] Count The number of PCI configuration operatio= ns to + perform. Bytes moved is Width size * Cou= nt, + starting at Offset. + + @param[in out] Buffer The source buffer to write data from. + + @retval EFI_SUCCESS The data was read from the PCI controlle= r. + @retval EFI_INVALID_PARAMETER "Width" is invalid. + @retval EFI_INVALID_PARAMETER "Buffer" is NULL. + +**/ +EFI_STATUS +PciIoPciWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT32 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + + Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + + if ((Width < 0) || (Width >=3D EfiPciIoWidthMaximum) || (Buffer =3D=3D N= ULL)) { + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoMemRW (TRUE, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Wid= th, + (UINT64)(Private->ConfigSpace + Offset), + Count, + Buffer + ); +} + +EFI_STATUS +PciIoCopyMem ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 DestBarIndex, + IN UINT64 DestOffset, + IN UINT8 SrcBarIndex, + IN UINT64 SrcOffset, + IN UINTN Count + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoMap ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + DMA_MAP_OPERATION DmaOperation; + + if (Operation =3D=3D EfiPciIoOperationBusMasterRead) { + DmaOperation =3D MapOperationBusMasterRead; + } else if (Operation =3D=3D EfiPciIoOperationBusMasterWrite) { + DmaOperation =3D MapOperationBusMasterWrite; + } else if (Operation =3D=3D EfiPciIoOperationBusMasterCommonBuffer) { + DmaOperation =3D MapOperationBusMasterCommonBuffer; + } else { + return EFI_INVALID_PARAMETER; + } + + return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, = Mapping); +} + +EFI_STATUS +PciIoUnmap ( + IN EFI_PCI_IO_PROTOCOL *This, + IN VOID *Mapping + ) +{ + return DmaUnmap (Mapping); +} + +/** + Allocate pages that are suitable for an EfiPciIoOperationBusMasterCommon= Buffer + mapping. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL ins= tance. + @param[in] Type This parameter is not used and must be i= gnored. + @param[in] MemoryType The type of memory to allocate, EfiBootS= ervicesData or + EfiRuntimeServicesData. + @param[in] Pages The number of pages to allocate. + @param[out] HostAddress A pointer to store the base system memor= y address of + the allocated range. + @param[in] Attributes The requested bit mask of attributes for= the allocated + range. Only the attributes, + EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE a= nd + EFI_PCI_ATTRIBUTE_MEMORY_CACHED may be u= sed with this + function. If any other bits are set, the= n EFI_UNSUPPORTED + is returned. This function ignores this = bit mask. + + @retval EFI_SUCCESS The requested memory pages were allocate= d. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_INVALID_PARAMETER MemoryType is invalid. + @retval EFI_UNSUPPORTED Attributes is unsupported. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +EFI_STATUS +PciIoAllocateBuffer ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ) +{ + if (Attributes & + (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | + EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) { + return EFI_UNSUPPORTED; + } + + return DmaAllocateBuffer (MemoryType, Pages, HostAddress); +} + +/** + Frees memory that was allocated with AllocateBuffer(). + + The FreeBuffer() function frees memory that was allocated with Allocate= Buffer(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_= PROTOCOL. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the al= located range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddres= s and Pages + was not allocated with AllocateBuffer(). + +**/ + +EFI_STATUS +PciIoFreeBuffer ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINTN Pages, + IN VOID *HostAddress + ) +{ + return DmaFreeBuffer (Pages, HostAddress); +} + +EFI_STATUS +PciIoFlush ( + IN EFI_PCI_IO_PROTOCOL *This + ) +{ + // + // not supported yet + // + return EFI_SUCCESS; +} + +/** + Retrieves this PCI controller's current PCI bus number, device number, a= nd function number. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL ins= tance. + @param[out] SegmentNumber The PCI controller's current PCI segment= number. + @param[out] BusNumber The PCI controller's current PCI bus num= ber. + @param[out] DeviceNumber The PCI controller's current PCI device = number. + @param[out] FunctionNumber The PCI controller=E2=80=99s current PCI= function number. + + @retval EFI_SUCCESS The PCI controller location was returned. + @retval EFI_INVALID_PARAMETER At least one out of the four output para= meters is + a NULL pointer. +**/ +EFI_STATUS +PciIoGetLocation ( + IN EFI_PCI_IO_PROTOCOL *This, + OUT UINTN *SegmentNumber, + OUT UINTN *BusNumber, + OUT UINTN *DeviceNumber, + OUT UINTN *FunctionNumber + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private; + + if ((SegmentNumber =3D=3D NULL) || (BusNumber =3D=3D NULL) || + (DeviceNumber =3D=3D NULL) || (FunctionNumber =3D=3D NULL) ) { + return EFI_INVALID_PARAMETER; + } + + Private =3D EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This); + *SegmentNumber =3D Private->Segment; + *BusNumber =3D 0xff; + *DeviceNumber =3D 0; + *FunctionNumber =3D 0; + + return EFI_SUCCESS; +} + +/** + Performs an operation on the attributes that this PCI controller support= s. + + The operations include getting the set of supported attributes, retrievi= ng + the current attributes, setting the current attributes, enabling attribu= tes, + and disabling attributes. + + @param[in] This A pointer to the EFI_PCI_IO_PROTOCOL ins= tance. + @param[in] Operation The operation to perform on the attribut= es for this + PCI controller. + @param[in] Attributes The mask of attributes that are used for= Set, + Enable and Disable operations. + @param[out] Result A pointer to the result mask of attribut= es that are + returned for the Get and Supported opera= tions. This + is an optional parameter that may be NUL= L for the + Set, Enable, and Disable operations. + + @retval EFI_SUCCESS The operation on the PCI controller's + attributes was completed. If the operati= on + was Get or Supported, then the attribute= mask + is returned in Result. + @retval EFI_INVALID_PARAMETER Operation is greater than or equal to + EfiPciIoAttributeOperationMaximum. + @retval EFI_INVALID_PARAMETER Operation is Get and Result is NULL. + @retval EFI_INVALID_PARAMETER Operation is Supported and Result is NUL= L. + +**/ +EFI_STATUS +PciIoAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, + IN UINT64 Attributes, + OUT UINT64 *Result OPTIONAL + ) +{ + switch (Operation) { + case EfiPciIoAttributeOperationGet: + case EfiPciIoAttributeOperationSupported: + if (Result =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + // + // We are not a real PCI device so just say things we kind of do + // + *Result =3D EFI_PCI_DEVICE_ENABLE; + break; + + case EfiPciIoAttributeOperationSet: + case EfiPciIoAttributeOperationEnable: + case EfiPciIoAttributeOperationDisable: + if (Attributes & (~EFI_PCI_DEVICE_ENABLE)) { + return EFI_UNSUPPORTED; + } + // + // Since we are not a real PCI device no enable/set or disable operati= ons exist. + // + break; + + default: + return EFI_INVALID_PARAMETER; + }; + return EFI_SUCCESS; +} + +EFI_STATUS +PciIoGetBarAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT8 BarIndex, + OUT UINT64 *Supports, OPTIONAL + OUT VOID **Resources OPTIONAL + ) +{ + if (Supports =3D=3D NULL && Resources =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoSetBarAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN UINT8 BarIndex, + IN OUT UINT64 *Offset, + IN OUT UINT64 *Length + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_PCI_IO_PROTOCOL PciIoTemplate =3D +{ + PciIoPollMem, + 0, + { PciIoMemRead, PciIoMemWrite }, + { 0, PciIoIoWrite }, + { PciIoPciRead, PciIoPciWrite }, + PciIoCopyMem, + PciIoMap, + PciIoUnmap, + PciIoAllocateBuffer, + PciIoFreeBuffer, + PciIoFlush, + PciIoGetLocation, + PciIoAttributes, + PciIoGetBarAttributes, + PciIoSetBarAttributes, + 0, + 0 +}; + +EFI_STATUS +PciInstallDevice ( + IN UINTN DeviceId, + IN PHYSICAL_ADDRESS MemoryStart, + IN UINT64 MemorySize, + IN UINTN ClassCode1, + IN UINTN ClassCode2, + IN UINTN ClassCode3 + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + EFI_PCI_IO_PRIVATE_DATA *Private; + + // + // Create a private structure + // + Private =3D AllocatePool (sizeof (EFI_PCI_IO_PRIVATE_DATA)); + if (Private =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "Failed to allocate memory for EFI_PCI_IO_PRIVATE= _DATA\n")); + return Status; + } + + Private->Signature =3D EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; = // Fill in signature + Private->RootBridge.Signature =3D PCI_ROOT_BRIDGE_SIGNATURE; = // Fake Root Bridge structure needs a signature too + Private->RootBridge.MemoryStart =3D MemoryStart; // Get the controller r= egister base + Private->Segment =3D 0; = // Default to segment zero + + // + // Calculate the total size of the controller. + // + Private->RootBridge.MemorySize =3D MemorySize; + + // + // HBA reset + // + if (PCI_CLASS_MASS_STORAGE_SATADPA =3D=3D ClassCode2) { + MmioWrite32 ((Private->RootBridge.MemoryStart + HBA_GHC), HBA_RESET); + } + + // + // Create fake PCI config space + // + Private->ConfigSpace =3D AllocateZeroPool (sizeof (PCI_TYPE00)); + if (Private->ConfigSpace =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "Failed to allocate memory for PCI_TYPE00\n")); + FreePool (Private); + return Status; + } + + // + // Configure PCI config space + // + Private->ConfigSpace->Hdr.VendorId =3D 0xFFFF; // Invalid vendor Id = as it is not an actual device. + Private->ConfigSpace->Hdr.DeviceId =3D 0x0000; // Not relevant as th= e vendor id is not valid. + Private->ConfigSpace->Hdr.ClassCode[0] =3D ClassCode1; + Private->ConfigSpace->Hdr.ClassCode[1] =3D ClassCode2; + Private->ConfigSpace->Hdr.ClassCode[2] =3D ClassCode3; + Private->ConfigSpace->Device.Bar[0] =3D Private->RootBridge.MemorySta= rt; + + Handle =3D NULL; + + // Unique device path. + CopyMem (&Private->DevicePath, &PciIoDevicePathTemplate, sizeof (PciIoDe= vicePathTemplate)); + Private->DevicePath.AcpiDevicePath.UID =3D 0; + Private->DevicePath.PciDevicePath.Device =3D DeviceId; + + // Copy protocol structure + CopyMem (&Private->PciIoProtocol, &PciIoTemplate, sizeof (PciIoTemplate)= ); + + Status =3D gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEfiPciIoProtocolGuid, + &Private->PciIoProtocol, + &gEfiDevicePathProtocol= Guid, + &Private->DevicePath, + NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PciInstallDevice InstallMultipleProtocolInterfac= es () failed.\n")); + FreePool (Private->ConfigSpace); + FreePool (Private); + } + + return Status; +} + +EFI_STATUS +PciEmulationEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + BOOLEAN SuccessFlag; + UINT8 DeviceId; + UINTN ControllerAddr; + + DeviceId =3D 0; + + while (DeviceId < PcdGet32 (PcdNumUsbController)) { + ControllerAddr =3D PcdGet32 (PcdUsbBaseAddr) + (DeviceId * PcdGet32 (P= cdUsbSize)); + Status =3D InitializeUsbController (ControllerAddr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "USB HC initialization Failed for %d (0x%x)\n", + ControllerAddr, Status)); + continue; + } + + Status =3D PciInstallDevice (DeviceId, ControllerAddr, PcdGet32 (PcdUs= bSize), + PCI_IF_XHCI, PCI_CLASS_SERIAL_USB, + PCI_CLASS_SERIAL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PciEmulation: failed to install USB %d device\= n", DeviceId)); + } else { + SuccessFlag =3D TRUE; + } + DeviceId++; + } + + while (DeviceId < (PcdGet32 (PcdNumUsbController) + PcdGet32 (PcdNumSata= Controller))) { + ControllerAddr =3D PcdGet32 (PcdSataBaseAddr) + + ((DeviceId - PcdGet32 (PcdNumUsbController)) * PcdGet= 32 (PcdSataSize)); + + Status =3D PciInstallDevice (DeviceId, ControllerAddr, PcdGet32 (PcdSa= taSize), + PCI_IF_MASS_STORAGE_SATA, PCI_CLASS_MASS_ST= ORAGE_SATADPA, + PCI_CLASS_MASS_STORAGE); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PciEmulation: failed to install SATA %d device= \n", + DeviceId - PcdGet32 (PcdNumUsbController))); + } else { + SuccessFlag =3D TRUE; + } + DeviceId++; + } + + if (SuccessFlag) { + return EFI_SUCCESS; + } else { + return Status; + } +} diff --git a/Platform/NXP/Drivers/PciEmulation/PciEmulation.h b/Platform/NX= P/Drivers/PciEmulation/PciEmulation.h new file mode 100755 index 0000000..870d870 --- /dev/null +++ b/Platform/NXP/Drivers/PciEmulation/PciEmulation.h @@ -0,0 +1,306 @@ +/** PciEmulation.h + Provides all declararyion of PCI Root Bridge IO Protocol + + Reference taken from PCI Emulation implementation in + Omap35xxPkg/PciEmulation/ + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _PCI_EMULATION_H_ +#define _PCI_EMULATION_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'C', '= I', '3') +#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'C', '= I', 'L') +#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR (a, EFI_PCI_IO_PRIVATE= _DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE) +#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, I= o, PCI_ROOT_BRIDGE_SIGNATURE) + + +#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL +#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL +#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL + +#define HBA_GHC 0x04 +#define HBA_RESET 0x80000001 + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + + +#define ACPI_CONFIG_IO 0 +#define ACPI_CONFIG_MMIO 1 +#define ACPI_CONFIG_BUS 2 + +typedef struct { + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3]; + EFI_ACPI_END_TAG_DESCRIPTOR EndDesc; +} ACPI_CONFIG_INFO; + + + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath; + UINT8 StartBus; + UINT8 EndBus; + UINT16 Type; + UINT32 MemoryStart; + UINT32 MemorySize; + UINTN IoOffset; + UINT32 IoStart; + UINT32 IoSize; + UINT64 PciAttributes; + ACPI_CONFIG_INFO *Config; +} PCI_ROOT_BRIDGE; + + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + PCI_DEVICE_PATH PciDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_IO_DEVICE_PATH; + +typedef struct { + UINT32 Signature; + EFI_PCI_IO_DEVICE_PATH DevicePath; + EFI_PCI_IO_PROTOCOL PciIoProtocol; + PCI_TYPE00 *ConfigSpace; + PCI_ROOT_BRIDGE RootBridge; + UINTN Segment; +} EFI_PCI_IO_PRIVATE_DATA; + +// +// Driver Instance Data Prototypes +// + +typedef struct { + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation; + UINTN NumberOfBytes; + UINTN NumberOfPages; + EFI_PHYSICAL_ADDRESS HostAddress; + EFI_PHYSICAL_ADDRESS MappedHostAddress; +} MAP_INFO; + +EFI_STATUS +EFIAPI +PciRootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ); + +// +// Private Function Prototypes +// +// +EFI_STATUS +PciRootBridgeIoMemRW ( + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +BOOLEAN +PciIoMemAddressValid ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT64 Address + ); + +EFI_STATUS +EFIAPI +InitializeUsbController ( + IN UINTN UsbReg + ); + +#endif diff --git a/Platform/NXP/Drivers/PciEmulation/PciEmulation.inf b/Platform/= NXP/Drivers/PciEmulation/PciEmulation.inf new file mode 100644 index 0000000..10fcb4b --- /dev/null +++ b/Platform/NXP/Drivers/PciEmulation/PciEmulation.inf @@ -0,0 +1,54 @@ +/* PciEmulation.inf +# Component description file for PCI Host Bridge driver +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +*/ + +[Defines] + INF_VERSION =3D 0x0001000A + BASE_NAME =3D PciEmulation + FILE_GUID =3D 196e7c2a-37b2-4b85-8683-7185c055fd5b + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PciEmulationEntryPoint + +[Sources.common] + PciRootBridgeIo.c + PciEmulation.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DmaLib + UefiDriverEntryPoint + UsbHcdLibrary + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdUsbBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdUsbSize + gNxpQoriqLsTokenSpaceGuid.PcdNumUsbController + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdSataSize + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController + +[Protocols] + gEfiPciRootBridgeIoProtocolGuid + gEfiDevicePathProtocolGuid + gEfiPciHostBridgeResourceAllocationProtocolGuid + gEfiPciIoProtocolGuid + +[Depex] + TRUE diff --git a/Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c b/Platform= /NXP/Drivers/PciEmulation/PciRootBridgeIo.c new file mode 100644 index 0000000..4020cbe --- /dev/null +++ b/Platform/NXP/Drivers/PciEmulation/PciRootBridgeIo.c @@ -0,0 +1,286 @@ +/** PciRootBridgeIo.c + PCI Root Bridge Io Protocol implementation + + Reference taken from PCI Emulation implementation in + Omap35xxPkg/PciEmulation/ + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be = found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +**/ + +#include "PciEmulation.h" + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mInStride[] =3D { + 1, // EfiPciWidthUint8 + 2, // EfiPciWidthUint16 + 4, // EfiPciWidthUint32 + 8, // EfiPciWidthUint64 + 0, // EfiPciWidthFifoUint8 + 0, // EfiPciWidthFifoUint16 + 0, // EfiPciWidthFifoUint32 + 0, // EfiPciWidthFifoUint64 + 1, // EfiPciWidthFillUint8 + 2, // EfiPciWidthFillUint16 + 4, // EfiPciWidthFillUint32 + 8 // EfiPciWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mOutStride[] =3D { + 1, // EfiPciWidthUint8 + 2, // EfiPciWidthUint16 + 4, // EfiPciWidthUint32 + 8, // EfiPciWidthUint64 + 1, // EfiPciWidthFifoUint8 + 2, // EfiPciWidthFifoUint16 + 4, // EfiPciWidthFifoUint32 + 8, // EfiPciWidthFifoUint64 + 0, // EfiPciWidthFillUint8 + 0, // EfiPciWidthFillUint16 + 0, // EfiPciWidthFillUint32 + 0 // EfiPciWidthFillUint64 +}; + + +BOOLEAN +PciRootBridgeMemAddressValid ( + IN PCI_ROOT_BRIDGE *Private, + IN UINT64 Address + ) +{ + if ((Address >=3D Private->MemoryStart) && + (Address < (Private->MemoryStart + Private->MemorySize))) { + return TRUE; + } + + return FALSE; +} + +EFI_STATUS +PciRootBridgeIoMemRW ( + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + UINT8 InStride; + UINT8 OutStride; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03= ); + for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + break; + case EfiPciWidthUint16: + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + break; + case EfiPciWidthUint32: + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + break; + case EfiPciWidthUint64: + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); + break; + case EfiPciWidthUint16: + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); + break; + case EfiPciWidthUint32: + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); + break; + case EfiPciWidthUint64: + *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } + } + + return EFI_SUCCESS; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root = bridge memory space. + + @param This A pointer to the EFI_PCI_R= OOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the= memory operations. + @param Address The base address of the me= mory operations. + @param Count The number of memory opera= tions to perform. + @param Buffer For read operations, the d= estination buffer to store the results. For write + operations, the source buf= fer to write data from. + + @retval EFI_SUCCESS The data was read from or = written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be c= ompleted due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are= invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE *Private; + + if ( Buffer =3D=3D NULL ) { + return EFI_INVALID_PARAMETER; + } + + Private =3D INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (!PciRootBridgeMemAddressValid (Private, Address)) { + DEBUG ((DEBUG_ERROR, "READ ADDRESS is not valid: %llx\n", Address)); + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoMemRW (FALSE, Width, Address, Count, Buffer); + +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root = bridge memory space. + + @param This A pointer to the EFI_PCI_R= OOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the= memory operations. + @param Address The base address of the me= mory operations. + @param Count The number of memory opera= tions to perform. + @param Buffer For read operations, the d= estination buffer to store the results. For write + operations, the source buf= fer to write data from. + + @retval EFI_SUCCESS The data was read from or = written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be c= ompleted due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are= invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE *Private; + + if ( Buffer =3D=3D NULL ) { + return EFI_INVALID_PARAMETER; + } + + Private =3D INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (!PciRootBridgeMemAddressValid (Private, Address)) { + DEBUG ((DEBUG_ERROR, "WRITE ADDRESS is not valid: %llx\n", Address)); + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoMemRW (TRUE, Width, Address, Count, Buffer); +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root = bridge memory space. + + @param This A pointer to the EFI_PCI_R= OOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the= memory operations. + @param Address The base address of the me= mory operations. + @param Count The number of memory opera= tions to perform. + @param Buffer For read operations, the d= estination buffer to store the results. For write + operations, the source buf= fer to write data from. + + @retval EFI_SUCCESS The data was read from or = written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be c= ompleted due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are= invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root = bridge memory space. + + @param This A pointer to the EFI_PCI_R= OOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the= memory operations. + @param Address The base address of the me= mory operations. + @param Count The number of memory opera= tions to perform. + @param Buffer For read operations, the d= estination buffer to store the results. For write + operations, the source buf= fer to write data from. + + @retval EFI_SUCCESS The data was read from or = written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be c= ompleted due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are= invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec index fd07eee..f43ccf0 100644 --- a/Platform/NXP/NxpQoriqLs.dec +++ b/Platform/NXP/NxpQoriqLs.dec @@ -51,8 +51,8 @@ gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0|UINT64|0x0000010E gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0|UINT64|0x0000010F gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0|UINT64|0x00000110 - gNxpQoriqLsTokenSpaceGuid.PcdSataController1BaseAddress|0x0|UINT32|0x000= 00111 - gNxpQoriqLsTokenSpaceGuid.PcdSataController2BaseAddress|0x0|UINT32|0x000= 00112 + gNxpQoriqLsTokenSpaceGuid.PcdSataBaseAddr|0x0|UINT32|0x00000111 + gNxpQoriqLsTokenSpaceGuid.PcdSataSize|0x0|UINT32|0x00000112 gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000|UINT64|0x00000= 113 gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000|UINT64|0x00000114 gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000|UINT64|0x00000= 115 @@ -246,3 +246,8 @@ # gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cBus|0|UINT32|0x0000330 gNxpQoriqLsTokenSpaceGuid.PcdSysEepromI2cAddress|0|UINT32|0x0000331 + + # + # SATA Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdNumSataController|0x0|UINT32|0x00000340 --=20 1.9.1 --===============8410973760582140696== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel --===============8410973760582140696==-- From nobody Sun May 5 01:30:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513924138877592.5954273509791; Thu, 21 Dec 2017 22:28:58 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 81336222CB30A; Thu, 21 Dec 2017 22:24:07 -0800 (PST) Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0058.outbound.protection.outlook.com [104.47.37.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 06A2B222CB302 for ; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2699 Subject: [edk2] [PATCH edk2-platforms 3/3] SATA : Added SATA controller initialization driver. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add driver to initialize SATA controller and apply any platform specific errata. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Platform/NXP/Drivers/SataInitDxe/SataInit.c | 122 +++++++++++++++++++= ++++ Platform/NXP/Drivers/SataInitDxe/SataInit.h | 32 ++++++ Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf | 43 ++++++++ Platform/NXP/NxpQoriqLs.dec | 5 + Platform/NXP/NxpQoriqLs.dsc | 6 ++ 5 files changed, 208 insertions(+) create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.c create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInit.h create mode 100644 Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.c b/Platform/NXP/Dri= vers/SataInitDxe/SataInit.c new file mode 100644 index 0000000..4bda242 --- /dev/null +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.c @@ -0,0 +1,122 @@ +/** @file + This driver module performs initialization of SATA controller + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + **/ + +#include +#include +#include +#include + +#include "SataInit.h" + +/** + Write AHCI Operation register. + + @param PciIo The PCI IO protocol instance. + @param Offset The operation register offset. + @param Data The data used to write down. + +**/ +VOID +EFIAPI +AhciWriteReg ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT32 Offset, + IN UINT32 Data + ) +{ + ASSERT (PciIo !=3D NULL); + + PciIo->Mem.Write ( + PciIo, + EfiPciIoWidthUint32, + AHCI_BAR_INDEX, + (UINT64) Offset, + 1, + &Data + ); + + return; +} + +/** + The Entry Point of module. It follows the standard UEFI driver model. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry poi= nt. + +**/ +EFI_STATUS +EFIAPI +InitializeSataController ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + + // + // Impact : The SATA controller does not detect some hard drives reliabl= y with + // the default SerDes register setting. + // Workaround : write value 0x80104e20 to 0x1eb1300 (serdes 2) + // + if (PcdGetBool (PcdSataErratumA010554)) { + BeMmioWrite32 ((UINTN)SERDES2_SATA_ERRATA, 0x80104e20); + } + + // + // Impact : Device may see false CRC errors causing unreliable SATA oper= ation. + // Workaround : write 0x80000000 to the address 0x20140520 (dcsr). + // + if (PcdGetBool (PcdSataErratumA010635)) { + BeMmioWrite32 ((UINTN)DCSR_SATA_ERRATA, 0x80000000); + } + + // + // Locate PCI I/O Protocol + // + Status =3D gBS->LocateProtocol (&gEfiPciIoProtocolGuid, NULL, (VOID **)&= PciIo); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Sata controller is not able to find PCI Emulatio= n 0x%x\n", + Status)); + return Status; + } + + // + // configuring Physical Control Layer parameters for Port 0 + // + AhciWriteReg (PciIo, SATA_PPCFG, PORT_PHYSICAL); + + // + // This register controls the configuration of the + // Transport Layer for Port 0 + // Errata Description : The default Rx watermark value may be insufficie= nt for some + // hard drives and result in a false CRC or internal errors. + // Workaround: Change PTC[RXWM] field at offset 0xC8 to 0x29. Do not cha= nge + // the other reserved fields of the register. + // + + if (PcdGetBool (PcdSataErratumA009185)) { + AhciWriteReg (PciIo, SATA_PTC, PORT_RXWM); + } else { + AhciWriteReg (PciIo, SATA_PTC, PORT_TRANSPORT); + } + + return Status; +} diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInit.h b/Platform/NXP/Dri= vers/SataInitDxe/SataInit.h new file mode 100644 index 0000000..401173d --- /dev/null +++ b/Platform/NXP/Drivers/SataInitDxe/SataInit.h @@ -0,0 +1,32 @@ +/** @file + Header file for Sata Controller initialization driver. + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + + **/ + +#ifndef _SATA_INIT_H_ +#define _SATA_INIT_H_ + + +#define AHCI_BAR_INDEX 0x05 + +#define SATA_PPCFG 0xA8 +#define SATA_PTC 0xC8 + +#define PORT_PHYSICAL 0xA003FFFE +#define PORT_TRANSPORT 0x08000025 +#define PORT_RXWM 0x08000029 + +#define DCSR_SATA_ERRATA 0x20140520 +#define SERDES2_SATA_ERRATA 0x01eb1300 + +#endif diff --git a/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf b/Platform/NX= P/Drivers/SataInitDxe/SataInitDxe.inf new file mode 100644 index 0000000..d06480f --- /dev/null +++ b/Platform/NXP/Drivers/SataInitDxe/SataInitDxe.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for the Sata Controller initialization driver +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001000A + BASE_NAME =3D SataInit + FILE_GUID =3D 021722D8-522B-4079-852A-FE44C2C13F49 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeSataController + +[Sources] + SataInit.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[LibraryClasses] + BeIoLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635 + +[Protocols] + gEfiPciIoProtocolGuid diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec index f43ccf0..bf4a086 100644 --- a/Platform/NXP/NxpQoriqLs.dec +++ b/Platform/NXP/NxpQoriqLs.dec @@ -82,6 +82,8 @@ gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000|UINT64|0x0000012D gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000|UINT64|0x0000012E gNxpQoriqLsTokenSpaceGuid.PcdDramMemSize|0x0|UINT64|0x0000012F + gNxpQoriqLsTokenSpaceGuid.PcdDcsrBaseAddr|0x0|UINT64|0x00000130 + gNxpQoriqLsTokenSpaceGuid.PcdDcsrSize|0x0|UINT64|0x00000131 =20 # # DSPI Pcds @@ -155,6 +157,9 @@ gNxpQoriqLsTokenSpaceGuid.PcdErratumA008514|FALSE|BOOLEAN|0x00000275 gNxpQoriqLsTokenSpaceGuid.PcdErratumA008336|FALSE|BOOLEAN|0x00000276 gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000277 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010554|FALSE|BOOLEAN|0x00000278 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA010635|FALSE|BOOLEAN|0x00000279 + gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA008402|FALSE|BOOLEAN|0x0000027A =20 # # Test PCDs diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc index 9b450fa..6efa2a4 100644 --- a/Platform/NXP/NxpQoriqLs.dsc +++ b/Platform/NXP/NxpQoriqLs.dsc @@ -334,6 +334,12 @@ } =20 # + # ATA Driver + # + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + + # # Architectural Protocols # ArmPkg/Drivers/CpuDxe/CpuDxe.inf --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel