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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN2PR03MB2367 Subject: [edk2] [PATCH edk2-platforms v2 1/4] Platform/NXP : Add Integrated flash controller library support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On NXP Layerscape SoCs,NOR Flash device interfacing is via IFC and IfcFlashLib provides helper functions to be used by NXP NOR flash library Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Platform/NXP/Include/Library/Ifc.h | 147 +++++++++++++++++= ++++ Platform/NXP/Include/Library/IfcBase.h | 139 +++++++++++++++++= ++ .../Include/Library/IfcBoardSpecificLib.h | 50 +++++++ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 2 + Platform/NXP/Library/IfcFlashLib/IfcFlashLib.c | 70 ++++++++++ Platform/NXP/Library/IfcFlashLib/IfcFlashLib.inf | 33 +++++ Platform/NXP/NxpQoriqLs.dec | 1 + 7 files changed, 442 insertions(+) create mode 100755 Platform/NXP/Include/Library/Ifc.h create mode 100644 Platform/NXP/Include/Library/IfcBase.h create mode 100755 Platform/NXP/LS1043aRdbPkg/Include/Library/IfcBoardSpec= ificLib.h create mode 100644 Platform/NXP/Library/IfcFlashLib/IfcFlashLib.c create mode 100644 Platform/NXP/Library/IfcFlashLib/IfcFlashLib.inf diff --git a/Platform/NXP/Include/Library/Ifc.h b/Platform/NXP/Include/Libr= ary/Ifc.h new file mode 100755 index 0000000..dd36fd8 --- /dev/null +++ b/Platform/NXP/Include/Library/Ifc.h @@ -0,0 +1,147 @@ +/** @Ifc.h + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __IFC_H__ +#define __IFC_H__ + +#include +#include +#include +#include +#include +#include +#include + +#define IFC_BANK_COUNT 4 + +#define IFC_CSPR_REG_LEN 148 +#define IFC_AMASK_REG_LEN 144 +#define IFC_CSOR_REG_LEN 144 +#define IFC_FTIM_REG_LEN 576 + +#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \ + IFC_BANK_COUNT + +#define IFC_AMASK_USED_LEN sizeof (IFC_AMASK) * \ + IFC_BANK_COUNT + +#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \ + IFC_BANK_COUNT + +#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \ + IFC_BANK_COUNT + +typedef enum { + IFC_CS0 =3D 0, + IFC_CS1, + IFC_CS2, + IFC_CS3, + IFC_CS4, + IFC_CS5, + IFC_CS6, + IFC_CS7, +} IFC_CHIP_SEL; + +typedef enum { + IFC_FTIM0 =3D 0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +} IFC_FTIMS; + +typedef struct { + UINT32 CsprExt; + UINT32 Cspr; + UINT32 Res; +} IFC_CSPR; + +typedef struct { + UINT32 Amask; + UINT32 Res[0x2]; +} IFC_AMASK; + +typedef struct { + UINT32 Csor; + UINT32 CsorExt; + UINT32 Res; +} IFC_CSOR; + +typedef struct { + UINT32 Ftim[4]; + UINT32 Res[0x8]; +}IFC_FTIM ; + +/* + * IFC controller NOR Machine registers + */ +typedef struct { + UINT32 NorEvterStat; + UINT32 Res1[0x2]; + UINT32 NorEvterEn; + UINT32 Res2[0x2]; + UINT32 NorEvterIntrEn; + UINT32 Res3[0x2]; + UINT32 NorErattr0; + UINT32 NorErattr1; + UINT32 NorErattr2; + UINT32 Res4[0x4]; + UINT32 NorCr; + UINT32 Res5[0xEF]; +} IFC_NOR; + +/* + * IFC Controller Registers + */ +typedef struct { + UINT32 IfcRev; + UINT32 Res1[0x2]; + IFC_CSPR CsprCs[IFC_BANK_COUNT]; + UINT8 Res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; + IFC_AMASK AmaskCs[IFC_BANK_COUNT]; + UINT8 Res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; + IFC_CSOR CsorCs[IFC_BANK_COUNT]; + UINT8 Res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; + IFC_FTIM FtimCs[IFC_BANK_COUNT]; + UINT8 Res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; + UINT32 RbStat; + UINT32 RbMap; + UINT32 WpMap; + UINT32 IfcGcr; + UINT32 Res7[0x2]; + UINT32 CmEvter_stat; + UINT32 Res8[0x2]; + UINT32 CmEvterEn; + UINT32 Res9[0x2]; + UINT32 CmEvterIntrEn; + UINT32 Res10[0x2]; + UINT32 CmErattr0; + UINT32 CmErattr1; + UINT32 Res11[0x2]; + UINT32 IfcCcr; + UINT32 IfcCsr; + UINT32 DdrCcrLow; + UINT32 Res12[0x2EA]; + IFC_NOR IfcNor; +} IFC_REGS; + +typedef struct { + UINT32 Ftim[IFC_BANK_COUNT]; + UINT32 CsprExt; + UINT32 Cspr; + UINT32 Csor; + UINT32 Amask; +} IfcTimings; + +#endif //__IFC_H__ diff --git a/Platform/NXP/Include/Library/IfcBase.h b/Platform/NXP/Include/= Library/IfcBase.h new file mode 100644 index 0000000..7020a29 --- /dev/null +++ b/Platform/NXP/Include/Library/IfcBase.h @@ -0,0 +1,139 @@ +/** @IfcLib.h + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __IFC_COMMON_H__ +#define __IFC_COMMON_H__ + +#define NOR_FLASH_DEVICE_COUNT 1 + +#define MAX_RETRY_COUNT 150000 + +/* + * CSPR - Chip Select Property Register + */ + +#define IFC_CSPR_BA 0xFFFF0000 +#define IFC_CSPR_BA_SHIFT 16 +#define IFC_CSPR_PORT_SIZE 0x00000180 +#define IFC_CSPR_PORT_SIZE_SHIFT 7 + +// Port Size 8 bit +#define IFC_CSPR_PORT_SIZE_8 0x00000080 + +// Port Size 16 bit +#define IFC_CSPR_PORT_SIZE_16 0x00000100 + +// Port Size 32 bit +#define IFC_CSPR_PORT_SIZE_32 0x00000180 + +// Write Protect +#define IFC_CSPR_WP 0x00000040 +#define IFC_CSPR_WP_SHIFT 6 + +// Machine Select +#define IFC_CSPR_MSEL 0x00000006 +#define IFC_CSPR_MSEL_SHIFT 1 + +// NOR +#define IFC_CSPR_MSEL_NOR 0x00000000 + +// Bank Valid +#define IFC_CSPR_V 0x00000001 +#define IFC_CSPR_V_SHIFT 0 + +/* + * Chip Select Option Register - NOR Flash Mode + */ + +// Enable Address shift Mode +#define IFC_CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 + +// Page Read Enable from NOR device +#define IFC_CSOR_NOR_PGRD_EN 0x10000000 + +// AVD Toggle Enable during Burst Program +#define IFC_CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 + +// Address Data Multiplexing Shift +#define IFC_CSOR_NOR_ADM_MASK 0x0003E000 +#define IFC_CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define IFC_CSOR_NOR_ADM_SHIFT(n) ((n) << IFC_CSOR_NOR_ADM_SHIFT_SHIFT) + +// Type of the NOR device hooked +#define IFC_CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define IFC_CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 + +// Time for Read Enable High to Output High Impedance +#define IFC_CSOR_NOR_TRHZ_MASK 0x0000001C +#define IFC_CSOR_NOR_TRHZ_SHIFT 2 +#define IFC_CSOR_NOR_TRHZ_20 0x00000000 +#define IFC_CSOR_NOR_TRHZ_40 0x00000004 +#define IFC_CSOR_NOR_TRHZ_60 0x00000008 +#define IFC_CSOR_NOR_TRHZ_80 0x0000000C +#define IFC_CSOR_NOR_TRHZ_100 0x00000010 + +// Buffer control disable +#define IFC_CSOR_NOR_BCTLD 0x00000001 + +/* + * FTIM0 - NOR Flash Mode + */ +#define IFC_FTIM0_NOR 0xF03F3F3F +#define IFC_FTIM0_NOR_TACSE_SHIFT 28 +#define IFC_FTIM0_NOR_TACSE(n) ((n) << IFC_FTIM0_NOR_TACSE_SHIFT) +#define IFC_FTIM0_NOR_TEADC_SHIFT 16 +#define IFC_FTIM0_NOR_TEADC(n) ((n) << IFC_FTIM0_NOR_TEADC_SHIFT) +#define IFC_FTIM0_NOR_TAVDS_SHIFT 8 +#define IFC_FTIM0_NOR_TAVDS(n) ((n) << IFC_FTIM0_NOR_TAVDS_SHIFT) +#define IFC_FTIM0_NOR_TEAHC_SHIFT 0 +#define IFC_FTIM0_NOR_TEAHC(n) ((n) << IFC_FTIM0_NOR_TEAHC_SHIFT) + +/* + * FTIM1 - NOR Flash Mode + */ +#define IFC_FTIM1_NOR 0xFF003F3F +#define IFC_FTIM1_NOR_TACO_SHIFT 24 +#define IFC_FTIM1_NOR_TACO(n) ((n) << IFC_FTIM1_NOR_TACO_SHIFT) +#define IFC_FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define IFC_FTIM1_NOR_TRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TRAD_NOR_SHI= FT) +#define IFC_FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define IFC_FTIM1_NOR_TSEQRAD_NOR(n) ((n) << IFC_FTIM1_NOR_TSEQRAD_NOR_= SHIFT) + +/* + * FTIM2 - NOR Flash Mode + */ +#define IFC_FTIM2_NOR 0x0F3CFCFF +#define IFC_FTIM2_NOR_TCS_SHIFT 24 +#define IFC_FTIM2_NOR_TCS(n) ((n) << IFC_FTIM2_NOR_TCS_SHIFT) +#define IFC_FTIM2_NOR_TCH_SHIFT 18 +#define IFC_FTIM2_NOR_TCH(n) ((n) << IFC_FTIM2_NOR_TCH_SHIFT) +#define IFC_FTIM2_NOR_TWPH_SHIFT 10 +#define IFC_FTIM2_NOR_TWPH(n) ((n) << IFC_FTIM2_NOR_TWPH_SHIFT) +#define IFC_FTIM2_NOR_TWP_SHIFT 0 +#define IFC_FTIM2_NOR_TWP(n) ((n) << IFC_FTIM2_NOR_TWP_SHIFT) + +/* Convert an address into the right format for the CSPR Registers */ +#define IFC_CSPR_PHYS_ADDR(x) (((UINTN)x) & 0xffff0000) + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (HighBitSet32(n) - IFC_AMASK_SHIFT)) + +VOID IfcNorInit(VOID); + +#endif //__IFC_COMMON_H__ diff --git a/Platform/NXP/LS1043aRdbPkg/Include/Library/IfcBoardSpecificLib= .h b/Platform/NXP/LS1043aRdbPkg/Include/Library/IfcBoardSpecificLib.h new file mode 100755 index 0000000..aaef340 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/Include/Library/IfcBoardSpecificLib.h @@ -0,0 +1,50 @@ +/** IfcBoardSpecificLib.h + IFC Flash Board Specific library + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#ifndef __IFC__BOARD_SPECIFIC_LIB_H__ +#define __IFC__BOARD_SPECIFIC_LIB_H__ + +// On board flash support,endianness +#define NOR_SUPPORT +#define IFC_REG_BASE 0x1530000 +#define IFC_NOR_BUF_BASE 0x60000000 + +// On board Inegrated flash Controller chip select configuration +#define IFC_NOR_CS IFC_CS0 + +// board-specific NOR flash timing +#define NOR_FTIM0 (IFC_FTIM0_NOR_TACSE(0x1) | \ + IFC_FTIM0_NOR_TEADC(0x1) | \ + IFC_FTIM0_NOR_TAVDS(0x0) | \ + IFC_FTIM0_NOR_TEAHC(0xc)) +#define NOR_FTIM1 (IFC_FTIM1_NOR_TACO(0x1c) | \ + IFC_FTIM1_NOR_TRAD_NOR(0xb) |\ + IFC_FTIM1_NOR_TSEQRAD_NOR(0x9)) +#define NOR_FTIM2 (IFC_FTIM2_NOR_TCS(0x1) | \ + IFC_FTIM2_NOR_TCH(0x4) | \ + IFC_FTIM2_NOR_TWPH(0x8) | \ + IFC_FTIM2_NOR_TWP(0x10)) +#define NOR_FTIM3 0x0 + +#define NOR_CSPR (IFC_CSPR_PHYS_ADDR(IFC_NOR_BUF_BASE) \ + | IFC_CSPR_PORT_SIZE_16 \ + | IFC_CSPR_MSEL_NOR \ + | IFC_CSPR_V) + +#define NOR_CSPR_EXT 0x0 +#define NOR_AMASK IFC_AMASK(128*1024*1024) +#define NOR_CSOR (IFC_CSOR_NOR_ADM_SHIFT(4) | \ + IFC_CSOR_NOR_TRHZ_80) + +#endif //__IFC__BOARD_SPECIFIC_LIB_H__ diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index 1951e82..7a72338 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -47,12 +47,14 @@ # gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 + gNxpQoriqLsTokenSpaceGuid.PcdIfcNorEnabled|1 =20 # # Big Endian IPs # gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE =20 # # I2C controller Pcds diff --git a/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.c b/Platform/NXP/= Library/IfcFlashLib/IfcFlashLib.c new file mode 100644 index 0000000..c9e8bc4 --- /dev/null +++ b/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.c @@ -0,0 +1,70 @@ +/** @IfcFlashLib.c + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +// Include board specific file for Flash timing +#include + +#ifdef NOR_SUPPORT +VOID +GetIfcNorFlashInfo ( + IN NorFlashInfo *NorFlashInfo + ) +{ + NorFlashInfo->IfcRegs =3D (IFC_REGS*) IFC_REG_BASE; + NorFlashInfo->ChipSelect =3D IFC_NOR_CS; + return ; +} + +VOID +GetIfcNorFlashTimings ( + IN IfcTimings * NorIfcTimings + ) +{ + NorIfcTimings->Ftim[0] =3D NOR_FTIM0; + NorIfcTimings->Ftim[1] =3D NOR_FTIM1; + NorIfcTimings->Ftim[2] =3D NOR_FTIM2; + NorIfcTimings->Ftim[3] =3D NOR_FTIM3; + NorIfcTimings->Cspr =3D NOR_CSPR; + NorIfcTimings->CsprExt =3D NOR_CSPR_EXT; + NorIfcTimings->Amask =3D NOR_AMASK; + NorIfcTimings->Csor =3D NOR_CSOR; + return ; +} + +VOID IfcNorWrite32 (VOID *a, UINT32 v) { + + if (FixedPcdGetBool (PcdIfcBigEndian)) { + BeMmioWrite32 ((UINTN)a, v); + } else { + MmioWrite32 ((UINTN)a, v); + } + +} + +FLASH_DATA +IfcNorFlashData ( + FLASH_DATA Value + ) +{ + + if (FixedPcdGetBool (PcdIfcBigEndian)) { + return SwapBytes16 (Value); + } else { + return Value; + } + +} +#endif //NOR_SUPPORT diff --git a/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.inf b/Platform/NX= P/Library/IfcFlashLib/IfcFlashLib.inf new file mode 100644 index 0000000..8447c7f --- /dev/null +++ b/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.inf @@ -0,0 +1,33 @@ +#/** IfcFlashLib.inf +# +# Component description file for IFC FLASH Library +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D IfcFlashLib + FILE_GUID =3D 8ecefc8f-a2c4-4091-b80f-92da7c4ab37f + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D IfcFlashLib + +[Sources.common] + IfcFlashLib.c + +[Packages] + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec index fd07eee..e773bcd 100644 --- a/Platform/NXP/NxpQoriqLs.dec +++ b/Platform/NXP/NxpQoriqLs.dec @@ -240,6 +240,7 @@ gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|FALSE|BOOLEAN|0x0000311 gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000312 gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|FALSE|BOOLEAN|0x00000313 + gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|FALSE|BOOLEAN|0x00000314 =20 # # System ID Eeprom Pcds --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 11:53:22 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN2PR03MB2368 Subject: [edk2] [PATCH edk2-platforms v2 2/4] Platform/NXP : Add Support for NOR flash Library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Adding support for NOR flash library(NorFlashLib) to provide functions which will be used by NOR flash Driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Platform/NXP/Include/Library/NorFlashLib.h | 67 +++ Platform/NXP/Library/NorFlashLib/CfiCommand.h | 99 ++++ Platform/NXP/Library/NorFlashLib/CfiNorFlashLib.c | 184 ++++++ Platform/NXP/Library/NorFlashLib/CfiNorFlashLib.h | 54 ++ Platform/NXP/Library/NorFlashLib/IfcNorFlashLib.c | 52 ++ Platform/NXP/Library/NorFlashLib/NorFlashLib.c | 658 ++++++++++++++++++= ++++ Platform/NXP/Library/NorFlashLib/NorFlashLib.inf | 42 ++ 7 files changed, 1156 insertions(+) create mode 100644 Platform/NXP/Include/Library/NorFlashLib.h create mode 100644 Platform/NXP/Library/NorFlashLib/CfiCommand.h create mode 100644 Platform/NXP/Library/NorFlashLib/CfiNorFlashLib.c create mode 100644 Platform/NXP/Library/NorFlashLib/CfiNorFlashLib.h create mode 100644 Platform/NXP/Library/NorFlashLib/IfcNorFlashLib.c create mode 100644 Platform/NXP/Library/NorFlashLib/NorFlashLib.c create mode 100644 Platform/NXP/Library/NorFlashLib/NorFlashLib.inf diff --git a/Platform/NXP/Include/Library/NorFlashLib.h b/Platform/NXP/Incl= ude/Library/NorFlashLib.h new file mode 100644 index 0000000..8eb0f82 --- /dev/null +++ b/Platform/NXP/Include/Library/NorFlashLib.h @@ -0,0 +1,67 @@ +/** @file + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved. + Copyright (c) 2016, Freescale Semiconductor. All rights reserved. + Copyright 2017 NXP + +This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + **/ + +#ifndef _NOR_FLASH_LIB_H_ +#define _NOR_FLASH_LIB_H_ + +#include + +typedef struct { + UINTN DeviceBaseAddress; // Start address of the Device Base Address (= DBA) + UINTN RegionBaseAddress; // Start address of one single region + UINTN Size; + UINTN BlockSize; + UINTN MultiByteWordCount; // Maximum Word count that can be written to = Nor Flash in multi byte write + UINTN WordWriteTimeOut; // single byte/word timeout usec + UINTN BufferWriteTimeOut; // buffer write timeout usec + UINTN BlockEraseTimeOut; // block erase timeout usec + UINTN ChipEraseTimeOut; // chip erase timeout usec +} NorFlashDescription; + +EFI_STATUS +NorFlashPlatformGetDevices ( + OUT NorFlashDescription **NorFlashDevices, + OUT UINT32 *Count + ); + +EFI_STATUS +NorFlashPlatformFlashGetAttributes ( + OUT NorFlashDescription *NorFlashDevices, + IN UINT32 Count + ); + +typedef struct { + UINT8 ChipSelect; + IFC_REGS* IfcRegs; +} NorFlashInfo; + +VOID +GetIfcNorFlashInfo ( + IN NorFlashInfo *NorFlashInfo + ); + +VOID +GetIfcNorFlashTimings ( + IN IfcTimings * NorIfcTimings + ); + +typedef UINT16 FLASH_DATA; + +FLASH_DATA IfcNorFlashData (FLASH_DATA Val); + +VOID IfcNorWrite32 (VOID *a, UINT32 v); + +#endif /* _NOR_FLASH_LIB_H_ */ diff --git a/Platform/NXP/Library/NorFlashLib/CfiCommand.h b/Platform/NXP/L= ibrary/NorFlashLib/CfiCommand.h new file mode 100644 index 0000000..5e755be --- /dev/null +++ b/Platform/NXP/Library/NorFlashLib/CfiCommand.h @@ -0,0 +1,99 @@ +/** @CfiCommand.h + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __CFI_COMMAND_H__ +#define __CFI_COMMAND_H__ + +// CFI Data "QRY" +#define CFI_QRY_Q 0x51 +#define CFI_QRY_R 0x52 +#define CFI_QRY_Y 0x59 +#define CFI_QRY 0x515259 + +#define ENTER_CFI_QUERY_MODE_ADDR 0x0055 +#define ENTER_CFI_QUERY_MODE_CMD 0x0098 + +#define CFI_QUERY_UNIQUE_QRY_STRING 0x10 + +// Offsets for CFI queries +#define CFI_QUERY_TYP_TIMEOUT_WORD_WRITE 0x1F +#define CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE 0x20 +#define CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE 0x21 +#define CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE 0x22 +#define CFI_QUERY_MAX_TIMEOUT_WORD_WRITE 0x23 +#define CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE 0x24 +#define CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE 0x25 +#define CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE 0x26 +#define CFI_QUERY_DEVICE_SIZE 0x27 +#define CFI_QUERY_MAX_NUM_BYTES_WRITE 0x2A +#define CFI_QUERY_BLOCK_SIZE 0x2F + +// Unlock Address +#define CMD_UNLOCK_1_ADDR 0x555 +#define CMD_UNLOCK_2_ADDR 0x2AA + +// RESET Command +#define CMD_RESET_FIRST 0xAA +#define CMD_RESET_SECOND 0x55 +#define CMD_RESET 0xF0 + +// READ Command + +// Manufacturer ID +#define CMD_READ_M_ID_FIRST 0xAA +#define CMD_READ_M_ID_SECOND 0x55 +#define CMD_READ_M_ID_THIRD 0x90 +#define CMD_READ_M_ID_FOURTH 0x01 + +// Device ID +#define CMD_READ_D_ID_FIRST 0xAA +#define CMD_READ_D_ID_SECOND 0x55 +#define CMD_READ_D_ID_THIRD 0x90 +#define CMD_READ_D_ID_FOURTH 0x7E +#define CMD_READ_D_ID_FIFTH 0x13 +#define CMD_READ_D_ID_SIXTH 0x00 + +// WRITE Commands + +// PROGRAM Commands +#define CMD_PROGRAM_FIRST 0xAA +#define CMD_PROGRAM_SECOND 0x55 +#define CMD_PROGRAM_THIRD 0xA0 + +// Write Buffer Commands +#define CMD_WRITE_TO_BUFFER_FIRST 0xAA +#define CMD_WRITE_TO_BUFFER_SECOND 0x55 +#define CMD_WRITE_TO_BUFFER_THIRD 0x25 +#define CMD_WRITE_TO_BUFFER_CONFIRM 0x29 + +// ERASE Commands + +// UNLOCK COMMANDS FOR ERASE +#define CMD_ERASE_FIRST 0xAA +#define CMD_ERASE_SECOND 0x55 +#define CMD_ERASE_THIRD 0x80 +#define CMD_ERASE_FOURTH 0xAA +#define CMD_ERASE_FIFTH 0x55 + +// Chip Erase Commands +#define CMD_CHIP_ERASE_SIXTH 0x10 + +// Sector Erase Commands +#define CMD_SECTOR_ERASE_SIXTH 0x30 + +// SUSPEND Commands +#define CMD_PROGRAM_OR_ERASE_SUSPEND 0xB0 +#define CMD_PROGRAM_OR_ERASE_RESUME 0x30 + +#endif /* __CFI_FLASH_H__ */ diff --git a/Platform/NXP/Library/NorFlashLib/CfiNorFlashLib.c b/Platform/N= XP/Library/NorFlashLib/CfiNorFlashLib.c new file mode 100644 index 0000000..2683cae --- /dev/null +++ b/Platform/NXP/Library/NorFlashLib/CfiNorFlashLib.c @@ -0,0 +1,184 @@ +/** @CfiNorFlashLib.c + + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + **/ + +#include +#include +#include +#include "CfiCommand.h" +#include "CfiNorFlashLib.h" + +VOID +FlashWrite_Data ( + FLASH_DATA Val, + UINTN Addr + ) +{ + *(volatile FLASH_DATA *)(Addr) =3D (Val); +} + +VOID +FlashWrite ( + FLASH_DATA Val, + UINTN Addr + ) +{ + FLASH_DATA ShiftVal; + ShiftVal =3D IfcNorFlashData (Val); + + *(volatile FLASH_DATA *)(Addr) =3D (ShiftVal); +} + +FLASH_DATA +FlashReadData ( + UINTN Addr + ) +{ + FLASH_DATA Val; + Val =3D *(volatile FLASH_DATA *)(Addr); + + return (Val); +} + +FLASH_DATA +FlashRead ( + UINTN Addr + ) +{ + FLASH_DATA Val; + FLASH_DATA ShiftVal; + + Val =3D *(volatile FLASH_DATA *)(Addr); + ShiftVal =3D IfcNorFlashData (Val); + + return (ShiftVal); +} + +STATIC +VOID +NorFlashReadCfiData ( + IN UINTN DeviceBaseAddress, + IN UINTN CFI_Offset, + IN UINT32 NumberOfShorts, + OUT VOID *Data + ) +{ + UINT32 Count; + FLASH_DATA *TmpData =3D (FLASH_DATA *)Data; + + for (Count =3D 0; Count < NumberOfShorts; Count++, TmpData++) { + *TmpData =3D FLASH_READ ((UINTN)((FLASH_DATA*)DeviceBaseAddress + CF= I_Offset)); + CFI_Offset++; + } +} + +/* + Currently we support only CFI flash devices; Bail-out otherwise +*/ +EFI_STATUS +CfiNorFlashFlashGetAttributes ( + OUT NorFlashDescription *NorFlashDevices, + IN UINT32 Index + ) +{ + UINT32 Count; + FLASH_DATA QryData[3] =3D {0}; + FLASH_DATA BlockSize[2] =3D {0}; + UINTN DeviceBaseAddress =3D 0; + FLASH_DATA MaxNumBytes[2] =3D {0}; + FLASH_DATA Size =3D 0; + FLASH_DATA HighByteMask =3D 0xFF; // Masks High byte in a= UIN16 word + FLASH_DATA HighByteShift =3D 8; // Bitshifts needed to ma= ke a byte High Byte in a UIN16 word + FLASH_DATA Temp1 =3D 0; + FLASH_DATA Temp2 =3D 0; + + for (Count =3D 0; Count < Index; Count++) { + + NorFlashDevices[Count].DeviceBaseAddress =3D DeviceBaseAddress =3D Pcd= Get64 (PcdFlashDeviceBase64); + + // Reset flash first + NorFlashPlatformReset (DeviceBaseAddress); + + // Enter the CFI Query Mode + SEND_NOR_COMMAND (DeviceBaseAddress, ENTER_CFI_QUERY_MODE_ADDR, + ENTER_CFI_QUERY_MODE_CMD); + + ArmDataSynchronizationBarrier (); + + // Query the unique QRY + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_UNIQUE_QRY_STRING, + 3, + &QryData); + if (QryData[0] !=3D (FLASH_DATA)CFI_QRY_Q || QryData[1] !=3D + (FLASH_DATA)CFI_QRY_R || QryData[2] !=3D (FLASH_DATA)CFI_QRY_Y= ) { + DEBUG ((DEBUG_ERROR, "Not a CFI flash (QRY not recvd): " + "Got =3D 0x%04x, 0x%04x, 0x%04x\n", + QryData[0], QryData[1], QryData[2])); + return EFI_DEVICE_ERROR; + } + + NorFlashReadCfiData (DeviceBaseAddress, CFI_QUERY_DEVICE_SIZE, + 1, &Size); + // Refer CFI Specification + NorFlashDevices[Count].Size =3D 1 << Size; + + NorFlashReadCfiData (DeviceBaseAddress, CFI_QUERY_BLOCK_SIZE, + 2, &BlockSize); + // Refer CFI Specification + NorFlashDevices[Count].BlockSize =3D 256 * ((FLASH_DATA) ((BlockSize[1= ] << + HighByteShift) | (BlockSize[0] & HighByteMask))); + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_NUM_BYTES_WRITE, 2, &MaxNumBytes); + // Refer CFI Specification + /* from CFI query we get the Max. number of BYTE in multi-byte write = =3D 2^N. + But our Flash Library is able to read/write in WORD size (2 bytes) = which + is why we need to CONVERT MAX BYTES TO MAX WORDS by diving it by + width of word size */ + NorFlashDevices[Count].MultiByteWordCount =3D\ + (1 << ((FLASH_DATA)((MaxNumBytes[1] << HighByteShift) | + (MaxNumBytes[0] & HighByteMask))))/sizeof(FLASH_DA= TA); + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_TYP_TIMEOUT_WORD_WRITE, 1, &Temp1); + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_TIMEOUT_WORD_WRITE, 1, &Temp2); + NorFlashDevices[Count].WordWriteTimeOut =3D (1U << Temp1) * (1U << Tem= p2); + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_TYP_TIMEOUT_MAX_BUFFER_WRITE, 1, &Temp1); + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_TIMEOUT_MAX_BUFFER_WRITE, 1, &Temp2); + NorFlashDevices[Count].BufferWriteTimeOut =3D (1U << Temp1) * (1U << T= emp2); + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_TYP_TIMEOUT_BLOCK_ERASE, 1, &Temp1); + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_TIMEOUT_BLOCK_ERASE, 1, &Temp2); + NorFlashDevices[Count].BlockEraseTimeOut =3D + (1U << Temp1) * (1U << Temp2) * 1000; + + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_TYP_TIMEOUT_CHIP_ERASE, 1, &Temp1); + NorFlashReadCfiData (DeviceBaseAddress, + CFI_QUERY_MAX_TIMEOUT_CHIP_ERASE, 1, &Temp2); + NorFlashDevices[Count].ChipEraseTimeOut =3D + (1U << Temp1) * (1U << Temp2) * 1000; + + // Put device back into Read Array mode (via Reset) + NorFlashPlatformReset (DeviceBaseAddress); + } + + return EFI_SUCCESS; +} diff --git a/Platform/NXP/Library/NorFlashLib/CfiNorFlashLib.h b/Platform/N= XP/Library/NorFlashLib/CfiNorFlashLib.h new file mode 100644 index 0000000..0b7a7ad --- /dev/null +++ b/Platform/NXP/Library/NorFlashLib/CfiNorFlashLib.h @@ -0,0 +1,54 @@ +/** @CfiNorFlashLib.h + + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __CFI_NOR_FLASH_LIB_H__ +#define __CFI_NOR_FLASH_LIB_H__ + +#include +#include + +/* + * Values for the width of the port + */ +#define FLASH_CFI_8BIT 0x01 +#define FLASH_CFI_16BIT 0x02 +#define FLASH_CFI_32BIT 0x04 +#define FLASH_CFI_64BIT 0x08 + +#define NOR_FLASH_ERASE_RETRY 10 + +#define CREATE_BYTE_OFFSET(OffsetAddr) ((sizeof (FLASH_DATA)) * = (OffsetAddr)) +#define CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) ((BaseAddr) + (OffsetAddr= )) +#define FLASH_READ(Addr) FlashRead ((Addr)) +#define FLASH_WRITE(Addr, Val) FlashWrite ((Val), (Addr)) +#define FLASH_READ_DATA(Addr) FlashReadData ((Addr)) +#define FLASH_WRITE_DATA(Addr, Val) FlashWrite_Data ((Val), (= Addr)) + +#define SEND_NOR_COMMAND(BaseAddr,Offset,Cmd) FLASH_WRITE (CREATE_NOR_A= DDRESS (BaseAddr,CREATE_BYTE_OFFSET(Offset)), (Cmd)) + +#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize) ( BaseAddr + (UINTN)(= (Lba) * LbaSize) ) + +VOID FlashWrite (FLASH_DATA Val, UINTN Addr); +FLASH_DATA FlashRead (UINTN Addr); + +VOID FlashWrite_Data (FLASH_DATA Val, UINTN Addr); +FLASH_DATA FlashReadData (UINTN Addr); + +EFI_STATUS +CfiNorFlashFlashGetAttributes ( + OUT NorFlashDescription *NorFlashDevices, + IN UINT32 Index + ); + +#endif /* __CFI_NOR_FLASH_LIB_H__ */ diff --git a/Platform/NXP/Library/NorFlashLib/IfcNorFlashLib.c b/Platform/N= XP/Library/NorFlashLib/IfcNorFlashLib.c new file mode 100644 index 0000000..f87ebc3 --- /dev/null +++ b/Platform/NXP/Library/NorFlashLib/IfcNorFlashLib.c @@ -0,0 +1,52 @@ +/** @IfcNorLib.c + + Copyright (c) 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + **/ + +#include + +/* + Initialise Integrated flash controller(IFC) NOR flash +*/ +VOID +IfcNorInit ( + VOID + ) +{ + UINT32 NorCs; + NorFlashInfo NorFlashInfo; + IfcTimings NorIfcTimings; + + GetIfcNorFlashInfo (&NorFlashInfo); + NorCs =3D NorFlashInfo.ChipSelect; + + // Get Nor Flash Timings + GetIfcNorFlashTimings (&NorIfcTimings); + + // Tune IFC Nor Flash Timings + IfcNorWrite32 (&NorFlashInfo.IfcRegs->CsprCs[NorCs].CsprExt, + NorIfcTimings.CsprExt); + IfcNorWrite32 (&NorFlashInfo.IfcRegs->FtimCs[NorCs].Ftim[IFC_FTIM0], + NorIfcTimings.Ftim[0]); + IfcNorWrite32 (&NorFlashInfo.IfcRegs->FtimCs[NorCs].Ftim[IFC_FTIM1], + NorIfcTimings.Ftim[1]); + IfcNorWrite32 (&NorFlashInfo.IfcRegs->FtimCs[NorCs].Ftim[IFC_FTIM2], + NorIfcTimings.Ftim[2]); + IfcNorWrite32 (&NorFlashInfo.IfcRegs->FtimCs[NorCs].Ftim[IFC_FTIM3], + NorIfcTimings.Ftim[3]); + IfcNorWrite32 (&NorFlashInfo.IfcRegs->CsprCs[NorCs].Cspr, + NorIfcTimings.Cspr); + IfcNorWrite32 (&NorFlashInfo.IfcRegs->AmaskCs[NorCs].Amask, + NorIfcTimings.Amask); + IfcNorWrite32 (&NorFlashInfo.IfcRegs->CsorCs[NorCs].Csor, + NorIfcTimings.Csor); +} diff --git a/Platform/NXP/Library/NorFlashLib/NorFlashLib.c b/Platform/NXP/= Library/NorFlashLib/NorFlashLib.c new file mode 100644 index 0000000..e5e469f --- /dev/null +++ b/Platform/NXP/Library/NorFlashLib/NorFlashLib.c @@ -0,0 +1,658 @@ +/** @NorFlashLib.c + + Based on NorFlash implementation available in NorFlashDxe.c + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + Copyright (c) 2015, Freescale Semiconductor, Inc. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include + +#include "CfiCommand.h" +#include "CfiNorFlashLib.h" + +#define GET_BLOCK_OFFSET(Lba) ((Instance->RegionBaseAddress)-(Instance->De= viceBaseAddress)+((UINTN)((Lba) * Instance->Media.BlockSize))) + +NorFlashDescription mNorFlashDevices[NOR_FLASH_DEVICE_COUNT]; + +STATIC VOID +UnlockEraseAddress ( + IN UINTN DeviceBaseAddress + ) +{ // Issue the Unlock cmds + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_ERASE_FIRST); + + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_ERASE_SECOND); + + // Issue a setup command + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_ERASE_THIRD); + + // Issue the Unlock cmds + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_ERASE_FOURTH); + + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_ERASE_FIFTH); + + return; +} + +STATIC +UINT64 +ConvertMicroSecondsToTicks( + IN UINTN MicroSeconds +) +{ + UINT64 TimerTicks64; + + TimerTicks64 =3D 0; + + // Calculate counter ticks that represent requested delay: + // =3D MicroSeconds x TICKS_PER_MICRO_SEC + // =3D MicroSeconds x Timer Frequency(in Hz) x 10^-6 + // GetPerformanceCounterProperties =3D Get Arm Timer Frequency in Hz + TimerTicks64 =3D DivU64x32 ( + MultU64x64 ( + MicroSeconds, + GetPerformanceCounterProperties (NULL, NULL) + ), + 1000000U + ); + return TimerTicks64; +} + +/** + * The following function erases a NOR flash sector. + **/ +EFI_STATUS +NorFlashPlatformEraseSector ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN SectorAddress + ) +{ + FLASH_DATA EraseStatus1; + FLASH_DATA EraseStatus2; + UINT64 Timeout; + UINT64 SystemCounterVal; + + EraseStatus1 =3D 0; + EraseStatus2 =3D 0; + Timeout =3D 0; + + Timeout =3D ConvertMicroSecondsToTicks ( + mNorFlashDevices[Instance->Media.MediaId].BlockEraseTim= eOut); + // Request a sector erase by writing two unlock cycles, followed by a + // setup command and two additional unlock cycles + + UnlockEraseAddress (Instance->DeviceBaseAddress); + + // Now send the address of the sector to be erased + SEND_NOR_COMMAND (SectorAddress, 0, CMD_SECTOR_ERASE_SIXTH); + + // Wait for erase to complete + // Read Sector start address twice to detect bit toggle and to + // determine ERASE DONE (all bits are 1) + // Get the maximum timer ticks needed to complete the operation + // Check if operation is complete or not in continous loop? + // if complete, exit from loop + // if not check the ticks that have been passed from the begining of loop + // if Maximum Ticks allocated for operation has passed exit from loop + + SystemCounterVal =3D GetPerformanceCounter (); + Timeout +=3D SystemCounterVal; + while (SystemCounterVal < Timeout) { + if ((EraseStatus1 =3D FLASH_READ(SectorAddress)) =3D=3D + (EraseStatus2 =3D FLASH_READ(SectorAddress))) { + if (0xFFFF =3D=3D FLASH_READ(SectorAddress)) { + break; + } + } + SystemCounterVal =3D GetPerformanceCounter (); + } + + if(SystemCounterVal >=3D Timeout) { + DEBUG((DEBUG_ERROR, "%a :Failed to Erase @ SectorAddress 0x%p, Timeout= \n", + __FUNCTION__, SectorAddress)); + return EFI_DEVICE_ERROR; + } else { + return EFI_SUCCESS; + } +} + +EFI_STATUS NorFlashPlatformWriteWord +( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN WordOffset, + IN FLASH_DATA Word +) +{ + UINT64 Timeout; + UINTN TargetAddress; + UINT64 SystemCounterVal; + FLASH_DATA Read1; + FLASH_DATA Read2; + + Timeout =3D 0; + + Timeout =3D ConvertMicroSecondsToTicks( + mNorFlashDevices[Instance->Media.MediaId].WordWriteTimeOut); + + TargetAddress =3D CREATE_NOR_ADDRESS(Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET(WordOffset)); + + // Issue the Unlock cmds + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_PROGRAM_FIRST); + + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_PROGRAM_SECOND); + + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_PROGRAM_THIRD); + + FLASH_WRITE_DATA (TargetAddress, Word); + + // Wait for Write to Complete + // Read the last written address twice to detect bit toggle and + // to determine if date is wriiten successfully or not ? + // Get the maximum timer ticks needed to complete the operation + // Check if operation is complete or not in continous loop? + // if complete, exit from loop + // if not check the ticks that have been passed from the begining of loop + // if Maximum Ticks allocated for operation has passed, then exit from l= oop + + SystemCounterVal =3D GetPerformanceCounter (); + Timeout +=3D SystemCounterVal; + while (SystemCounterVal < Timeout) { + if ((Read1 =3D FLASH_READ_DATA(TargetAddress)) =3D=3D + (Read2 =3D FLASH_READ_DATA(TargetAddress))) { + if (Word =3D=3D FLASH_READ_DATA(TargetAddress)) { + break; + } + } + SystemCounterVal =3D GetPerformanceCounter (); + } + + if(SystemCounterVal >=3D Timeout) { + DEBUG((DEBUG_ERROR, "%a: Failed to Write @ TargetAddress 0x%p, Timeou= t\n", + __FUNCTION__, TargetAddress)); + return EFI_DEVICE_ERROR; + } else { + return EFI_SUCCESS; + } +} + +EFI_STATUS NorFlashPlatformWritePageBuffer +( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN PageBufferOffset, + IN UINTN NumWords, + IN FLASH_DATA *Buffer +) +{ + UINT64 Timeout; + UINTN LastWrittenAddress; + FLASH_DATA LastWritenData; + UINTN current_offset; + UINTN end_offset; + UINTN TargetAddress; + UINT64 SystemCounterVal; + FLASH_DATA Read1; + FLASH_DATA Read2; + + // Initialize variables + Timeout =3D 0; + LastWrittenAddress =3D 0; + LastWritenData =3D 0; + current_offset =3D PageBufferOffset; + end_offset =3D PageBufferOffset + NumWords - 1; + Timeout =3D ConvertMicroSecondsToTicks ( + mNorFlashDevices[Instance->Media.MediaId].BufferWriteTim= eOut); + TargetAddress =3D CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET (current_offset)); + + // don't try with a count of zero + if (!NumWords) { + return EFI_SUCCESS; + } + else if (NumWords =3D=3D 1) { + return NorFlashPlatformWriteWord (Instance, PageBufferOffset, *Buffer); + } + + // Issue the Unlock cmds + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_WRITE_TO_BUFFER_FIRST); + + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_WRITE_TO_BUFFER_SECOND); + + // Write the buffer load + SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_THIRD); + + // Write # of locations to program + SEND_NOR_COMMAND (TargetAddress, 0, (NumWords - 1)); + + // Load Data into Buffer + while (current_offset <=3D end_offset) { + LastWrittenAddress =3D CREATE_NOR_ADDRESS (Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET (current_offset++)); + LastWritenData =3D *Buffer++; + + // Write Data + FLASH_WRITE_DATA (LastWrittenAddress,LastWritenData); + } + + // Issue the Buffered Program Confirm command + SEND_NOR_COMMAND (TargetAddress, 0, CMD_WRITE_TO_BUFFER_CONFIRM); + + /* Wait for Write to Complete + Read the last written address twice to detect bit toggle and + to determine if date is wriiten successfully or not ? + Get the maximum timer ticks needed to complete the operation + Check if operation is complete or not in continous loop? + if complete, exit from loop + if not check the ticks that have been passed from the begining of loop + if Maximum Ticks allocated for operation has passed, then exit from l= oop **/ + SystemCounterVal =3D GetPerformanceCounter(); + Timeout +=3D SystemCounterVal; + while (SystemCounterVal < Timeout) { + if ((Read1 =3D FLASH_READ_DATA (LastWrittenAddress)) =3D=3D + (Read2 =3D FLASH_READ_DATA (LastWrittenAddress))) { + if (LastWritenData =3D=3D FLASH_READ_DATA (LastWrittenAddress)) { + break; + } + } + SystemCounterVal =3D GetPerformanceCounter (); + } + + if (SystemCounterVal >=3D Timeout) { + DEBUG((DEBUG_ERROR, "%a: Failed to Write @LastWrittenAddress 0x%p, Tim= eout\n", + __FUNCTION__, LastWrittenAddress)); + return EFI_DEVICE_ERROR; + } else { + return EFI_SUCCESS; + } +} + +EFI_STATUS NorFlashPlatformWriteWordAlignedAddressBuffer +( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN Offset, + IN UINTN NumWords, + IN FLASH_DATA *Buffer + ) +{ + UINTN MultiByteWordCount; + UINTN Mask; + UINTN IntWords; + EFI_STATUS Status; + + MultiByteWordCount =3D mNorFlashDevices[Instance->Media.MediaId].MultiBy= teWordCount; + Mask =3D MultiByteWordCount - 1; + IntWords =3D NumWords; + Status =3D EFI_SUCCESS; + + if (Offset & Mask) + { + // program only as much as necessary, so pick the lower of the two num= bers + if (NumWords < (MultiByteWordCount - (Offset & Mask))) { + IntWords =3D NumWords; + } + else { + IntWords =3D MultiByteWordCount - (Offset & Mask); + } + + // program the first few to get write buffer aligned + Status =3D NorFlashPlatformWritePageBuffer (Instance, Offset, IntWords= , Buffer); + if (EFI_ERROR (Status)) { + return Status; + } + + Offset +=3D IntWords; // adjust pointers and counter + NumWords -=3D IntWords; + Buffer +=3D IntWords; + + if (NumWords =3D=3D 0) { + return Status; + } + } + + while (NumWords >=3D MultiByteWordCount) // while big chunks to do + { + Status =3D NorFlashPlatformWritePageBuffer (Instance, Offset, + MultiByteWordCount, Buffer); + if (EFI_ERROR (Status)) { + return (Status); + } + + Offset +=3D MultiByteWordCount; // adjust pointers and counter + NumWords -=3D MultiByteWordCount; + Buffer +=3D MultiByteWordCount; + } + if (NumWords =3D=3D 0) { + return (Status); + } + + Status =3D NorFlashPlatformWritePageBuffer (Instance, Offset, NumWords, = Buffer); + return (Status); +} + +/* + * Writes data to the NOR Flash using the Buffered Programming method. + * + * Write Buffer Programming allows the system to write a maximum of 32 byt= es + * in one programming operation. Therefore this function will only handle + * buffers up to 32 bytes. + * To deal with larger buffers, call this function again. + */ +EFI_STATUS +NorFlashPlatformWriteBuffer ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + FLASH_DATA *pSrcBuffer; + UINTN TargetOffsetinBytes; + UINTN WordsToWrite; + UINTN Mask; + UINTN BufferSizeInBytes; + UINTN IntBytes; + UINT8 *CopyFrom, *CopyTo; + FLASH_DATA TempWrite =3D 0; + + pSrcBuffer =3D (FLASH_DATA *)Buffer; + TargetOffsetinBytes =3D 0; + WordsToWrite =3D 0; + Mask =3D sizeof(FLASH_DATA) - 1; + BufferSizeInBytes =3D *NumBytes; + IntBytes =3D BufferSizeInBytes; // Intermediate Bytes needed to copy for= alignment + TempWrite =3D 0; + + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=3D%ld, Offset=3D0x%x, " + "*NumBytes=3D0x%x, Buffer @ 0x%08x)\n", + __FUNCTION__, Lba, Offset, *NumBytes, Buffer)); + + TargetOffsetinBytes =3D GET_BLOCK_OFFSET (Lba) + (UINTN)(Offset); + + if (TargetOffsetinBytes & Mask) { + // Write only as much as necessary, so pick the lower of the two numbe= rs + // and call it Intermediate bytes to write to make alignment proper + if (BufferSizeInBytes < (sizeof(FLASH_DATA) - (TargetOffsetinBytes & M= ask))) { + IntBytes =3D BufferSizeInBytes; + } + else { + IntBytes =3D sizeof(FLASH_DATA) - (TargetOffsetinBytes & Mask); + } + + // Read the first few to get Read buffer aligned + NorFlashPlatformRead (Instance, Lba, (TargetOffsetinBytes & ~Mask) - + GET_BLOCK_OFFSET (Lba), sizeof(TempWrite), (UINT8*)&TempWrite); + + CopyTo =3D (UINT8*)&TempWrite; + CopyTo +=3D (TargetOffsetinBytes & Mask); + CopyFrom =3D (UINT8*)Buffer; + + InternalMemCopyMem (CopyTo, CopyFrom, IntBytes); + + Status =3D NorFlashPlatformWriteWordAlignedAddressBuffer (Instance, + (UINTN)((TargetOffsetinBytes & ~Mask)/size= of(FLASH_DATA)), + 1, &TempWrite); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "%a : Failed to Write @TargetOffset 0x%x (0x%x)\= n", + __FUNCTION__, TargetOffsetinBytes, Status)); + goto EXIT; + } + + TargetOffsetinBytes +=3D IntBytes; /* adjust pointers and counter */ + BufferSizeInBytes -=3D IntBytes; + Buffer +=3D IntBytes; + + if (BufferSizeInBytes =3D=3D 0) { + goto EXIT; + } + } + + // Write the bytes to CFI width aligned address. + // Note we can Write number of bytes=3DCFI width in one operation + WordsToWrite =3D BufferSizeInBytes/sizeof(FLASH_DATA); + pSrcBuffer =3D (FLASH_DATA*)Buffer; + + Status =3D NorFlashPlatformWriteWordAlignedAddressBuffer ( + Instance, + (UINTN)(TargetOffsetinBytes/sizeof(FLASH_DATA)), + WordsToWrite, + pSrcBuffer); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "%a : Failed to Write @ TargetOffset 0x%x (0x%x)\n= ", + __FUNCTION__, TargetOffsetinBytes, Status)); + goto EXIT; + } + + BufferSizeInBytes -=3D (WordsToWrite*sizeof(FLASH_DATA)); + Buffer +=3D (WordsToWrite*sizeof(FLASH_DATA)); + TargetOffsetinBytes +=3D (WordsToWrite*sizeof(FLASH_DATA)); + + if (BufferSizeInBytes =3D=3D 0) { + goto EXIT; + } + + // Now Write bytes that are remaining and are less than CFI width. + // Read the first few to get Read buffer aligned + NorFlashPlatformRead (Instance, + Lba, + TargetOffsetinBytes - GET_BLOCK_OFFSET (Lba), + sizeof(TempWrite), + (UINT8*)&TempWrite); + + CopyFrom =3D (UINT8*)Buffer; + CopyTo =3D (UINT8*)&TempWrite; + + InternalMemCopyMem (CopyTo, CopyFrom, BufferSizeInBytes); + + Status =3D NorFlashPlatformWriteWordAlignedAddressBuffer (Instance, + (UINTN)(TargetOffsetinBytes/sizeof(FLASH_DATA)= ), + 1, + &TempWrite); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "%a: Failed to Write @TargetOffset 0x%x Status=3D%= d\n", + __FUNCTION__, TargetOffsetinBytes, Status)); + goto EXIT; + } + +EXIT: + // Put device back into Read Array mode (via Reset) + NorFlashPlatformReset (Instance->DeviceBaseAddress); + return (Status); +} + +EFI_STATUS +NorFlashPlatformRead ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN BufferSizeInBytes, + OUT UINT8 *Buffer + ) +{ + UINTN IntBytes; + UINTN Mask; + FLASH_DATA TempRead; + UINT8 *CopyFrom, *CopyTo; + UINTN TargetOffsetinBytes; + FLASH_DATA *pReadData; + UINTN BlockSize; + + IntBytes =3D BufferSizeInBytes; // Intermediate Bytes needed to copy for= alignment + Mask =3D sizeof(FLASH_DATA) - 1; + TempRead =3D 0; + TargetOffsetinBytes =3D (UINTN)(GET_BLOCK_OFFSET (Lba) + Offset); + BlockSize =3D Instance->Media.BlockSize; + + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=3D%ld, Offset=3D0x%x," + " BufferSizeInBytes=3D0x%x, Buffer @ 0x%p)\n", + __FUNCTION__, Lba, Offset, BufferSizeInBytes, Buffer)); + + // The buffer must be valid + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // Return if we have not any byte to read + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + + if (((Lba * BlockSize) + BufferSizeInBytes) > Instance->Size) { + DEBUG ((DEBUG_ERROR, "%a : Read will exceed device size.\n", __FUNCTIO= N__)); + return EFI_INVALID_PARAMETER; + } + + // Put device back into Read Array mode (via Reset) + NorFlashPlatformReset (Instance->DeviceBaseAddress); + + // First Read bytes to make buffer aligned to CFI width + if (TargetOffsetinBytes & Mask) { + // Read only as much as necessary, so pick the lower of the two numbers + if (BufferSizeInBytes < (sizeof(FLASH_DATA) - (TargetOffsetinBytes & M= ask))) { + IntBytes =3D BufferSizeInBytes; + } + else { + IntBytes =3D sizeof(FLASH_DATA) - (TargetOffsetinBytes & Mask); + } + + // Read the first few to get Read buffer aligned + TempRead =3D FLASH_READ_DATA (CREATE_NOR_ADDRESS ( + Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET ((TargetOffsetinBytes & ~Mask)/siz= eof(FLASH_DATA)))); + + CopyFrom =3D (UINT8*)&TempRead; + CopyFrom +=3D (TargetOffsetinBytes & Mask); + CopyTo =3D (UINT8*)Buffer; + + InternalMemCopyMem (CopyTo, CopyFrom, IntBytes); + + TargetOffsetinBytes +=3D IntBytes; // adjust pointers and counter + BufferSizeInBytes -=3D IntBytes; + Buffer +=3D IntBytes; + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + } + + pReadData =3D (FLASH_DATA*)Buffer; + + // Readout the bytes from CFI width aligned address. + // Note we can read number of bytes=3DCFI width in one operation + while (BufferSizeInBytes >=3D sizeof(FLASH_DATA)) { + *pReadData =3D FLASH_READ_DATA (CREATE_NOR_ADDRESS ( + Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof(FLASH_= DATA)))); + pReadData +=3D 1; + BufferSizeInBytes -=3D sizeof(FLASH_DATA); + TargetOffsetinBytes +=3D sizeof(FLASH_DATA); + } + if (BufferSizeInBytes =3D=3D 0) { + return EFI_SUCCESS; + } + + // Now read bytes that are remaining and are less than CFI width. + CopyTo =3D (UINT8*)pReadData; + // Read the first few to get Read buffer aligned + TempRead =3D FLASH_READ_DATA (CREATE_NOR_ADDRESS ( + Instance->DeviceBaseAddress, + CREATE_BYTE_OFFSET (TargetOffsetinBytes/sizeof(FLASH_= DATA)))); + CopyFrom =3D (UINT8*)&TempRead; + + InternalMemCopyMem (CopyTo, CopyFrom, BufferSizeInBytes); + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformReset ( + IN UINTN DeviceBaseAddress + ) +{ + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_1_ADDR, + CMD_RESET_FIRST); + + SEND_NOR_COMMAND (DeviceBaseAddress, CMD_UNLOCK_2_ADDR, + CMD_RESET_SECOND); + + SEND_NOR_COMMAND (DeviceBaseAddress, 0, CMD_RESET); + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformGetDevices ( + OUT NorFlashDescription **NorFlashDevices, + OUT UINT32 *Count + ) +{ + if ((NorFlashDevices =3D=3D NULL) || (Count =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // Get the number of NOR flash devices supported + *NorFlashDevices =3D mNorFlashDevices; + *Count =3D NOR_FLASH_DEVICE_COUNT; + + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformFlashGetAttributes ( + OUT NorFlashDescription *NorFlashDevices, + IN UINT32 Count + ) +{ + EFI_STATUS Status; + UINT32 Index; + + if ((NorFlashDevices =3D=3D NULL) || (Count =3D=3D 0)) { + return EFI_INVALID_PARAMETER; + } + + // Check the attributes of the NOR flash slave we are connected to. + // Currently we support only CFI flash devices. Bail-out otherwise. + Status =3D CfiNorFlashFlashGetAttributes (NorFlashDevices, Count); + if (EFI_ERROR (Status)) { + return Status; + } + + // Limit the Size of Nor Flash that can be programmed + for (Index =3D 0; Index < Count; Index++) { + NorFlashDevices[Index].RegionBaseAddress =3D PcdGet64 (PcdFlashReserve= dRegionBase64); + NorFlashDevices[Index].Size -=3D (NorFlashDevices[Index].RegionBaseAdd= ress - + NorFlashDevices[Index].DeviceBaseAddre= ss); + if((NorFlashDevices[Index].RegionBaseAddress - NorFlashDevices[Index].= DeviceBaseAddress) % + NorFlashDevices[Index].BlockSize) { + DEBUG ((DEBUG_ERROR, "%a : Reserved Region(0x%p) doesn't start " + "from block boundry(0x%08x)\n", __FUNCTION__, + (UINTN)NorFlashDevices[Index].RegionBaseAddress, + (UINT32)NorFlashDevices[Index].BlockSize)); + return EFI_DEVICE_ERROR; + } + } + return Status; +} diff --git a/Platform/NXP/Library/NorFlashLib/NorFlashLib.inf b/Platform/NX= P/Library/NorFlashLib/NorFlashLib.inf new file mode 100644 index 0000000..14ca0ab --- /dev/null +++ b/Platform/NXP/Library/NorFlashLib/NorFlashLib.inf @@ -0,0 +1,42 @@ +#/** @NorFlashLib.inf +# +# Component description file for NorFlashLib module +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D NorFlashLib + FILE_GUID =3D f3176a49-dde1-450d-a909-8580c03b9ba8 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NorFlashLib + +[Sources.common] + NorFlashLib.c + IfcNorFlashLib.c + CfiNorFlashLib.c + +[LibraryClasses] + ArmLib + IfcFlashLib + TimerLib + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[Pcd.common] + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64 + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64 --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 11:53:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2693 Subject: [edk2] [PATCH edk2-platforms v2 3/4] Platform/NXP : Add Support for NOR Flash driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Adding support for NOR flash Driver Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- .../NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c | 254 +++++++ Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.c | 444 +++++++++++ Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf | 65 ++ Platform/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c | 814 +++++++++++++++++= ++++ Platform/NXP/Include/Library/NorFlash.h | 222 ++++++ Silicon/NXP/Chassis/Chassis.c | 15 + Silicon/NXP/Chassis/Chassis.h | 7 + Silicon/NXP/Chassis/Chassis2/Soc.c | 1 + Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 + 9 files changed, 1824 insertions(+) create mode 100644 Platform/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c create mode 100644 Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.c create mode 100755 Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf create mode 100644 Platform/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c create mode 100644 Platform/NXP/Include/Library/NorFlash.h diff --git a/Platform/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c b/Platfo= rm/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c new file mode 100644 index 0000000..bad397f --- /dev/null +++ b/Platform/NXP/Drivers/NorFlashDxe/NorFlashBlockIoDxe.c @@ -0,0 +1,254 @@ +/** @NorFlashBlockIoDxe.c + + Based on NorFlash implementation available in ArmPlatformPkg/Drivers/Nor= FlashDxe/NorFlashBlockIoDxe.c + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset +// +EFI_STATUS +EFIAPI +NorFlashBlockIoReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ) +{ + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_BLKIO_THIS (This); + + DEBUG ((DEBUG_INFO, "NorFlashBlockIoReset (MediaId=3D0x%x)\n", + This->Media->MediaId)); + + return NorFlashPlatformReset (Instance->DeviceBaseAddress); +} + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer + ) +{ + NOR_FLASH_INSTANCE *Instance; + EFI_STATUS Status; + EFI_BLOCK_IO_MEDIA *Media; + UINTN NumBlocks; + UINT8 *pReadBuffer; + UINTN BlockCount; + UINTN BlockSizeInBytes; + EFI_LBA CurrentBlock; + + Status =3D EFI_SUCCESS; + + if ((This =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + Instance =3D INSTANCE_FROM_BLKIO_THIS (This); + Media =3D This->Media; + + if (Media =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + NumBlocks =3D ((UINTN)BufferSizeInBytes) / Instance->Media.BlockSize ; + + DEBUG ((DEBUG_BLKIO, "%a : (MediaId=3D0x%x, Lba=3D%ld, " + "BufferSize=3D0x%x bytes (%d kB)" + ", BufferPtr @ 0x%p)\n", + __FUNCTION__,MediaId, Lba, + BufferSizeInBytes, Buffer)); + + if (!Media) { + Status =3D EFI_INVALID_PARAMETER; + } + else if (!Media->MediaPresent) { + Status =3D EFI_NO_MEDIA; + } + else if (Media->MediaId !=3D MediaId) { + Status =3D EFI_MEDIA_CHANGED; + } + else if ((Media->IoAlign >=3D 2) && + (((UINTN)Buffer & (Media->IoAlign - 1)) !=3D 0)) { + Status =3D EFI_INVALID_PARAMETER; + } + else if (BufferSizeInBytes =3D=3D 0) { + // Return if we have not any byte to read + Status =3D EFI_SUCCESS; + } + else if ((BufferSizeInBytes % Media->BlockSize) !=3D 0) { + // The size of the buffer must be a multiple of the block size + DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes =3D 0x%x\n",__FUNCTION__, + BufferSizeInBytes)); + Status =3D EFI_INVALID_PARAMETER; + } else if ((Lba + NumBlocks - 1) > Media->LastBlock) { + // All blocks must be within the device + DEBUG ((DEBUG_ERROR, "%a : Read will exceed last block %d, %d, %d \n", + __FUNCTION__, Lba, NumBlocks, Media->LastBlock)); + Status =3D EFI_INVALID_PARAMETER; + } else { + BlockSizeInBytes =3D Instance->Media.BlockSize; + + /* Because the target *Buffer is a pointer to VOID, + * we must put all the data into a pointer + * to a proper data type, so use *pReadBuffer */ + pReadBuffer =3D (UINT8 *)Buffer; + + CurrentBlock =3D Lba; + // Read data block by Block + for (BlockCount =3D 0; BlockCount < NumBlocks; BlockCount++, CurrentBl= ock++, + pReadBuffer =3D pReadBuffer + BlockSizeInBytes) { + DEBUG ((DEBUG_BLKIO, "%a: Reading block #%d\n", + __FUNCTION__,(UINTN)CurrentBlock)); + + Status =3D NorFlashPlatformRead (Instance, CurrentBlock, (UINTN)0 , + BlockSizeInBytes,pReadBuffer); + if (EFI_ERROR (Status)) { + break; + } + } + } + DEBUG ((DEBUG_BLKIO,"%a: Exit Status =3D \"%r\".\n",__FUNCTION__,Status)= ); + + return Status; +} + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + IN VOID *Buffer + ) +{ + NOR_FLASH_INSTANCE *Instance; + EFI_STATUS Status; + EFI_BLOCK_IO_MEDIA *Media; + UINTN NumBlocks; + EFI_LBA CurrentBlock; + UINTN BlockSizeInBytes; + UINT32 BlockCount; + UINTN SectorAddress; + UINT8 *pWriteBuffer; + + Status =3D EFI_SUCCESS; + + if ((This =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + Instance =3D INSTANCE_FROM_BLKIO_THIS (This); + Media =3D This->Media; + + if (Media =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a : Media is NULL\n", __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + NumBlocks =3D ((UINTN)BufferSizeInBytes) / Instance->Media.BlockSize ; + + DEBUG ((DEBUG_BLKIO, "%a : (MediaId=3D0x%x, Lba=3D%ld, BufferSize=3D0x%x= " + "bytes (%d kB) BufferPtr @ 0x%08x)\n", + __FUNCTION__,MediaId, Lba,BufferSizeInBytes, Buffer)); + + if (!Media->MediaPresent) { + Status =3D EFI_NO_MEDIA; + } + else if (Media->MediaId !=3D MediaId) { + Status =3D EFI_MEDIA_CHANGED; + } + else if (Media->ReadOnly) { + Status =3D EFI_WRITE_PROTECTED; + } + else if (BufferSizeInBytes =3D=3D 0) { + Status =3D EFI_BAD_BUFFER_SIZE; + } + else if ((BufferSizeInBytes % Media->BlockSize) !=3D 0) { + // The size of the buffer must be a multiple of the block size + DEBUG ((DEBUG_ERROR, "%a : BlockSize in bytes =3D 0x%x\n",__FUNCTION__, + BufferSizeInBytes)); + Status =3D EFI_INVALID_PARAMETER; + } else if ((Lba + NumBlocks - 1) > Media->LastBlock) { + // All blocks must be within the device + DEBUG ((DEBUG_ERROR, "%a: Write will exceed last block %d, %d, %d \n", + __FUNCTION__,Lba, NumBlocks, Media->LastBlock)); + Status =3D EFI_INVALID_PARAMETER; + } else { + BlockSizeInBytes =3D Instance->Media.BlockSize; + + pWriteBuffer =3D (UINT8 *)Buffer; + + CurrentBlock =3D Lba; + // Program data block by Block + for (BlockCount =3D 0; BlockCount < NumBlocks; + BlockCount++, CurrentBlock++, + pWriteBuffer =3D (pWriteBuffer + BlockSizeInBytes)) { + DEBUG ((DEBUG_BLKIO, "%a: Writing block #%d\n", + __FUNCTION__,(UINTN)CurrentBlock)); + // Erase the Block(Sector) to be written to + SectorAddress =3D GET_NOR_BLOCK_ADDRESS ( + Instance->RegionBaseAddress, + CurrentBlock, + Instance->Media.BlockSize + ); + Status =3D NorFlashPlatformEraseSector (Instance, (UINTN)SectorAddre= ss); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to erase Target 0x%x (0x%x) \n", + __FUNCTION__,SectorAddress, Status)); + break; + } + // Program Block(Sector) to be written to + Status =3D NorFlashWrite (Instance, CurrentBlock, (UINTN)0, + &BlockSizeInBytes, pWriteBuffer); + if (EFI_ERROR (Status)) { + break; + } + } + } + DEBUG ((DEBUG_BLKIO, "%a: Exit Status =3D \"%r\".\n",__FUNCTION__,Status= )); + return Status; +} + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This + ) +{ + + DEBUG ((DEBUG_BLKIO, "%a NOT IMPLEMENTED (not required)\n", __FUNCTION__= )); + + // Nothing to do so just return without error + return EFI_SUCCESS; +} diff --git a/Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.c b/Platform/NXP/= Drivers/NorFlashDxe/NorFlashDxe.c new file mode 100644 index 0000000..ca17001 --- /dev/null +++ b/Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.c @@ -0,0 +1,444 @@ +/** @file NorFlashDxe.c + + Based on NorFlash implementation available in ArmPlatformPkg/Drivers/Nor= FlashDxe/NorFlashDxe.c + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include + +STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent; + +// +// Global variable declarations +// +NOR_FLASH_INSTANCE **mNorFlashInstances; +UINT32 mNorFlashDeviceCount; + +NOR_FLASH_INSTANCE mNorFlashInstanceTemplate =3D { + .Signature =3D NOR_FLASH_SIGNATURE, + .Initialized =3D FALSE, + .Initialize =3D NULL, + .StartLba =3D 0, + .BlockIoProtocol =3D { + .Revision =3D EFI_BLOCK_IO_PROTOCOL_REVISION2, + .Reset =3D NorFlashBlockIoReset, + .ReadBlocks =3D NorFlashBlockIoReadBlocks, + .WriteBlocks =3D NorFlashBlockIoWriteBlocks, + .FlushBlocks =3D NorFlashBlockIoFlushBlocks, + }, + + .Media =3D { + .RemovableMedia =3D FALSE, + .MediaPresent =3D TRUE, + .LogicalPartition =3D FALSE, + .ReadOnly =3D FALSE, + .WriteCaching =3D FALSE, + .IoAlign =3D 4, + .LowestAlignedLba =3D 0, + .LogicalBlocksPerPhysicalBlock =3D 1, + }, + + .FvbProtocol =3D { + .GetAttributes =3D FvbGetAttributes, + .SetAttributes =3D FvbSetAttributes, + .GetPhysicalAddress =3D FvbGetPhysicalAddress, + .GetBlockSize =3D FvbGetBlockSize, + .Read =3D FvbRead, + .Write =3D FvbWrite, + .EraseBlocks =3D FvbEraseBlocks, + .ParentHandle =3D NULL, + }, + .ShadowBuffer =3D NULL, + .DevicePath =3D { + .Vendor =3D { + .Header =3D { + .Type =3D HARDWARE_DEVICE_PATH, + .SubType =3D HW_VENDOR_DP, + .Length =3D {(UINT8)sizeof (VENDOR_DEVICE_PATH), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) } + }, + .Guid =3D EFI_CALLER_ID_GUID, // GUID ... NEED TO BE FILLED + }, + .End =3D { + .Type =3D END_DEVICE_PATH_TYPE, + .SubType =3D END_ENTIRE_DEVICE_PATH_SUBTYPE, + .Length =3D { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } + } + } +}; + +EFI_STATUS +NorFlashCreateInstance ( + IN UINTN NorFlashDeviceBase, + IN UINTN NorFlashRegionBase, + IN UINTN NorFlashSize, + IN UINT32 MediaId, + IN UINT32 BlockSize, + IN BOOLEAN SupportFvb, + OUT NOR_FLASH_INSTANCE** NorFlashInstance + ) +{ + EFI_STATUS Status; + NOR_FLASH_INSTANCE* Instance; + + ASSERT(NorFlashInstance !=3D NULL); + + Instance =3D AllocateRuntimeCopyPool (sizeof (NOR_FLASH_INSTANCE), + &mNorFlashInstanceTemplate); + if (Instance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Instance->DeviceBaseAddress =3D NorFlashDeviceBase; + Instance->RegionBaseAddress =3D NorFlashRegionBase; + Instance->Size =3D NorFlashSize; + + Instance->BlockIoProtocol.Media =3D &Instance->Media; + Instance->Media.MediaId =3D MediaId; + Instance->Media.BlockSize =3D BlockSize; + Instance->Media.LastBlock =3D (NorFlashSize / BlockSize)-1; + + Instance->ShadowBuffer =3D AllocateRuntimePool (BlockSize); + if (Instance->ShadowBuffer =3D=3D NULL) { + FreePool (Instance); + return EFI_OUT_OF_RESOURCES; + } + + if (SupportFvb) { + Instance->SupportFvb =3D TRUE; + Instance->Initialize =3D NorFlashFvbInitialize; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Instance->Handle, + &gEfiDevicePathProtocolGuid, &Instance->DevicePath, + &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol, + &gEfiFirmwareVolumeBlockProtocolGuid, &Instance->FvbProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (Instance->ShadowBuffer); + FreePool (Instance); + return Status; + } + } else { + Instance->Initialized =3D TRUE; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Instance->Handle, + &gEfiDevicePathProtocolGuid, &Instance->DevicePath, + &gEfiBlockIoProtocolGuid, &Instance->BlockIoProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (Instance->ShadowBuffer); + FreePool (Instance); + return Status; + } + } + + *NorFlashInstance =3D Instance; + + return Status; +} + +/* + Write a full or portion of a block. + It must not span block boundaries; that is, + Offset + NumBytes <=3D Instance->Media.BlockSize. + */ +EFI_STATUS +NorFlashWrite ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer +) +{ + EFI_STATUS Status; + UINTN BlockSize; + BOOLEAN DoErase; + VOID *Source; + UINTN SectorAddress; + + Status =3D EFI_SUCCESS; + Source =3D NULL; + + DEBUG ((DEBUG_BLKIO, "%a(Parameters: Lba=3D%ld, Offset=3D0x%x, NumBytes= =3D0x%x, " + "Buffer @ 0x%08x)\n", __FUNCTION__, + Lba, Offset, *NumBytes, Buffer)); + + // The buffer must be valid + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // Detect WriteDisabled state + if (Instance->Media.ReadOnly =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "NorFlashWrite: ERROR - Can not write: " + "Device is in WriteDisabled state.\n")); + // It is in WriteDisabled state, return an error right away + return EFI_ACCESS_DENIED; + } + + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D Instance->Media.BlockSize; + + // We must have some bytes to write + if ((*NumBytes =3D=3D 0) || (*NumBytes > BlockSize)) { + DEBUG ((DEBUG_ERROR, "NorFlashWrite: ERROR - EFI_BAD_BUFFER_SIZE: " + "(Offset=3D0x%x + NumBytes=3D0x%x) > BlockSize=3D0x%x\n", \ + Offset, *NumBytes, BlockSize )); + return EFI_BAD_BUFFER_SIZE; + } + + if (((Lba * BlockSize) + Offset + *NumBytes) > Instance->Size) { + DEBUG ((DEBUG_ERROR, "%a: ERROR - Write will exceed device size.\n", + __FUNCTION__)); + return EFI_INVALID_PARAMETER; + } + + // Check we did get some memory. Buffer is BlockSize. + if (Instance->ShadowBuffer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n")); + return EFI_DEVICE_ERROR; + } + + SectorAddress =3D GET_NOR_BLOCK_ADDRESS ( + Instance->RegionBaseAddress, + Lba, + Instance->Media.BlockSize + ); + + // Pick 128bytes as a good start for word operations as opposed to erasi= ng the + // block and writing the data regardless if an erase is really needed. + // It looks like most individual NV variable writes are smaller than 128= bytes. + if (*NumBytes <=3D 128) { + Source =3D Instance->ShadowBuffer; + //First Read the data into shadow buffer from location where data is t= o be written + Status =3D NorFlashPlatformRead ( + Instance, + Lba, + Offset, + *NumBytes, + Source + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to " + "Read @ %p Status=3D%d\n", __FUNCTION__, + Offset + SectorAddress, Status)); + return Status; + } + // Check to see if we need to erase before programming the data into N= orFlash. + // If the destination bits are only changing from 1s to 0s we can + // just write. After a block is erased all bits in the block is set to= 1. + // If any byte requires us to erase we just give up and rewrite all of= it. + DoErase =3D TestBitSetClear (Source, Buffer, *NumBytes, TRUE); + + // if we got here then write all the data. Otherwise do the + // Erase-Write cycle. + if (!DoErase) { + Status =3D NorFlashPlatformWriteBuffer ( + Instance, + Lba, + Offset, + NumBytes, + Buffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR - Failed to " + "Write @ %p Status=3D%d\n", __FUNCTION__, + Offset + SectorAddress, Status)); + return Status; + } + return EFI_SUCCESS; + } + } + + // If we are not going to write full block, read block and then update b= ytes in it + if (*NumBytes !=3D BlockSize) { + // Read NorFlash Flash data into shadow buffer + Status =3D NorFlashBlockIoReadBlocks ( + &(Instance->BlockIoProtocol), + Instance->Media.MediaId, + Lba, + BlockSize, + Instance->ShadowBuffer + ); + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + // Put the data at the appropriate location inside the buffer area + CopyMem ((VOID *)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *Nu= mBytes); + } + //Erase Block + Status =3D NorFlashPlatformEraseSector (Instance, SectorAddress); + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + if (*NumBytes !=3D BlockSize) { + // Write the modified shadow buffer back to the NorFlash + Status =3D NorFlashPlatformWriteBuffer ( + Instance, + Lba, + 0, + &BlockSize, + Instance->ShadowBuffer + ); + } else { + // Write the Buffer to an entire block in NorFlash + Status =3D NorFlashPlatformWriteBuffer ( + Instance, + Lba, + 0, + &BlockSize, + Buffer + ); + } + if (EFI_ERROR (Status)) { + // Return one of the pre-approved error statuses + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +NorFlashVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINTN Index; + + for (Index =3D 0; Index < mNorFlashDeviceCount; Index++) { + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->DeviceBase= Address); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->RegionBase= Address); + + // Convert BlockIo protocol + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoPro= tocol.FlushBlocks); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoPro= tocol.ReadBlocks); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoPro= tocol.Reset); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->BlockIoPro= tocol.WriteBlocks); + + // Convert Fvb + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.EraseBlocks); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.GetAttributes); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.GetBlockSize); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.GetPhysicalAddress); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.Read); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.SetAttributes); + EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->FvbProtoco= l.Write); + if (mNorFlashInstances[Index]->ShadowBuffer !=3D NULL) { + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]->ShadowB= uffer); + } + } + + return; +} + +EFI_STATUS +EFIAPI +NorFlashInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 Index; + NorFlashDescription* NorFlashDevices; + BOOLEAN ContainVariableStorage; + + ContainVariableStorage =3D 0; + + Status =3D NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDevic= eCount); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR,"%a : Failed to get Nor devices (0x%x)\n", + __FUNCTION__, Status)); + return Status; + } + + Status =3D NorFlashPlatformFlashGetAttributes (NorFlashDevices, + mNorFlashDeviceCount); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR,"%a : Failed to get NOR device attributes (0x%x)\n= ", + __FUNCTION__, Status)); + ASSERT_EFI_ERROR (Status); /* System becomes unusable if NOR flash is = not detected */ + return Status; + } + + mNorFlashInstances =3D AllocateRuntimePool ( + sizeof(NOR_FLASH_INSTANCE*) * mNorFlashDeviceC= ount); + if (mNorFlashInstances =3D=3D NULL) { + DEBUG ((DEBUG_ERROR,"%a : Failed to allocate runtime memory \n")); + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < mNorFlashDeviceCount; Index++) { + // Check if this NOR Flash device contain the variable storage region + ContainVariableStorage =3D + (NorFlashDevices[Index].RegionBaseAddress <=3D PcdGet64 (PcdFlashNvS= torageVariableBase64)) && + (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvSt= orageVariableSize) <=3D + NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].S= ize); + + Status =3D NorFlashCreateInstance ( + NorFlashDevices[Index].DeviceBaseAddress, + NorFlashDevices[Index].RegionBaseAddress, + NorFlashDevices[Index].Size, + Index, + NorFlashDevices[Index].BlockSize, + ContainVariableStorage, + &mNorFlashInstances[Index] + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR,"%a : Failed to create instance for " + "NorFlash[%d] (0x%x)\n",Index, Status)); + } + + } + + // + // Register for the virtual address change event + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + NorFlashVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mNorFlashVirtualAddrChangeEvent + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR,"Failed to create VirtualAddressChange event 0x%x\= n", + Status)); + } + + return Status; +} diff --git a/Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf b/Platform/NX= P/Drivers/NorFlashDxe/NorFlashDxe.inf new file mode 100755 index 0000000..2da8a51 --- /dev/null +++ b/Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf @@ -0,0 +1,65 @@ +#/** @file +# +# Component description file for NorFlashDxe module +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D NorFlashDxe + FILE_GUID =3D 616fe8d8-f4aa-42e0-a393-b332bdb2d3c1 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D NorFlashInitialise + +[Sources.common] + NorFlashDxe.c + NorFlashFvbDxe.c + NorFlashBlockIoDxe.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + Platform/NXP/NxpQoriqLs.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + DxeServicesTableLib + HobLib + NorFlashLib + UefiDriverEntryPoint + UefiRuntimeLib + +[Guids] + gEfiSystemNvDataFvGuid + gEfiVariableGuid + gEfiAuthenticatedVariableGuid + gEfiEventVirtualAddressChangeGuid + +[Protocols] + gEfiBlockIoProtocolGuid + gEfiFirmwareVolumeBlockProtocolGuid + +[Pcd.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +[Depex] + # + # NorFlashDxe must be loaded before VariableRuntimeDxe in case empty fla= sh needs populating with default values + # + BEFORE gVariableRuntimeDxeFileGuid diff --git a/Platform/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c b/Platform/N= XP/Drivers/NorFlashDxe/NorFlashFvbDxe.c new file mode 100644 index 0000000..f74ffc9 --- /dev/null +++ b/Platform/NXP/Drivers/NorFlashDxe/NorFlashFvbDxe.c @@ -0,0 +1,814 @@ +/*@NorFlashFvbDxe.c + + Based on NorFlash implementation available in ArmPlatformPkg/Drivers/NorF= lashDxe/NorFlashFvbDxe.c + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be= found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + + --*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC EFI_EVENT mFvbVirtualAddrChangeEvent; +STATIC UINTN mFlashNvStorageVariableBase; + +/// +/// The Firmware Volume Block Protocol is the low-level interface +/// to a firmware volume. File-level access to a firmware volume +/// should not be done using the Firmware Volume Block Protocol. +/// Normal access to a firmware volume must use the Firmware +/// Volume Protocol. Typically, only the file system driver that +/// produces the Firmware Volume Protocol will bind to the +/// Firmware Volume Block Protocol. +/// + +/** + Initialises the FV Header and Variable Store Header + to support variable operations. + + @param[in] Ptr - Location to initialise the headers + +**/ +EFI_STATUS +InitializeFvAndVariableStoreHeaders ( + IN NOR_FLASH_INSTANCE *Instance + ) +{ + EFI_STATUS Status; + VOID* Headers; + UINTN HeadersLength; + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + + if (!Instance->Initialized && Instance->Initialize) { + Instance->Initialize (Instance); + } + + HeadersLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_B= LOCK_MAP_ENTRY) + sizeof (VARIABLE_STORE_HEADER); + Headers =3D AllocateZeroPool (HeadersLength); + if (Headers =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Memory allocation failed for Headers \n")); + return EFI_OUT_OF_RESOURCES; + } + + // FirmwareVolumeHeader->FvLength is declared to have the Variable area = AND the FTW working area AND the FTW Spare contiguous. + ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashN= vStorageVariableSize) =3D=3D PcdGet64 (PcdFlashNvStorageFtwWorkingBase64)); + ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + PcdGet32 (PcdFlas= hNvStorageFtwWorkingSize) =3D=3D PcdGet64 (PcdFlashNvStorageFtwSpareBase64)= ); + + // Check if the size of the area is at least one block size + ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && (PcdGet32 (Pcd= FlashNvStorageVariableSize) / Instance->Media.BlockSize > 0)); + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && (PcdGet32 (P= cdFlashNvStorageFtwWorkingSize) / Instance->Media.BlockSize > 0)); + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && (PcdGet32 (Pcd= FlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0)); + + // Ensure the Variable area Base Addresses are aligned on a block size b= oundaries + ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) % Instance->Media.Blo= ckSize =3D=3D 0); + ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.B= lockSize =3D=3D 0); + ASSERT (PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % Instance->Media.Blo= ckSize =3D=3D 0); + + // + // EFI_FIRMWARE_VOLUME_HEADER + // + FirmwareVolumeHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*)Headers; + CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid= ); + FirmwareVolumeHeader->FvLength =3D + PcdGet32 (PcdFlashNvStorageVariableSize) + + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + PcdGet32 (PcdFlashNvStorageFtwSpareSize); + FirmwareVolumeHeader->Signature =3D EFI_FVH_SIGNATURE; + FirmwareVolumeHeader->Attributes =3D (EFI_FVB_ATTRIBUTES_2) ( + EFI_FVB2_READ_ENABLED_CAP | //= Reads may be enabled + EFI_FVB2_READ_STATUS | //= Reads are currently enabled + EFI_FVB2_STICKY_WRITE | //= A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY + EFI_FVB2_MEMORY_MAPPED | //= It is memory mapped + EFI_FVB2_ERASE_POLARITY | //= After erasure all bits take this value (i.e. '1') + EFI_FVB2_WRITE_STATUS | //= Writes are currently enabled + EFI_FVB2_WRITE_ENABLED_CAP //= Writes may be enabled + ); + FirmwareVolumeHeader->HeaderLength =3D sizeof (EFI_FIRMWARE_VOLUME_HEADE= R) + sizeof (EFI_FV_BLOCK_MAP_ENTRY); + FirmwareVolumeHeader->Revision =3D EFI_FVH_REVISION; + //i.e. if blocks are 0-5 then last block =3D 5, total blocks =3D 6 + FirmwareVolumeHeader->BlockMap[0].NumBlocks =3D Instance->Media.LastBloc= k + 1; + FirmwareVolumeHeader->BlockMap[0].Length =3D Instance->Media.BlockS= ize; + FirmwareVolumeHeader->BlockMap[1].NumBlocks =3D 0; + FirmwareVolumeHeader->BlockMap[1].Length =3D 0; + FirmwareVolumeHeader->Checksum =3D CalculateCheckSum16 ((UINT16*)Firmwar= eVolumeHeader,FirmwareVolumeHeader->HeaderLength); + + // + // VARIABLE_STORE_HEADER + // + VariableStoreHeader =3D (VARIABLE_STORE_HEADER*)((UINTN)Headers + Firmwa= reVolumeHeader->HeaderLength); + CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGui= d); + VariableStoreHeader->Size =3D PcdGet32(PcdFlashNvStorageVariableSize) - = FirmwareVolumeHeader->HeaderLength; + VariableStoreHeader->Format =3D VARIABLE_STORE_FORMATTED; + VariableStoreHeader->State =3D VARIABLE_STORE_HEALTHY; + + // Install the combined super-header in the NorFlash + Status =3D FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Heade= rs); + + FreePool (Headers); + return Status; +} + +/** + Check the integrity of firmware volume header. + + @param[in] FwVolHeader - A pointer to a firmware volume header + + @retval EFI_SUCCESS - The firmware volume is consistent + @retval EFI_NOT_FOUND - The firmware volume has been corrupted. + +**/ +EFI_STATUS +ValidateFvHeader ( + IN NOR_FLASH_INSTANCE *Instance + ) +{ + UINT16 Checksum; + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + UINTN VariableStoreLength; + UINTN FvLength; + + FwVolHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*)mFlashNvStorageVariableBase; + + FvLength =3D PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (PcdFla= shNvStorageFtwWorkingSize) + + PcdGet32 (PcdFlashNvStorageFtwSpareSize); + + // + // Verify the header revision, header signature, length + // Length of FvBlock cannot be 2**64-1 + // HeaderLength cannot be an odd number + // + if ( (FwVolHeader->Revision !=3D EFI_FVH_REVISION) + || (FwVolHeader->Signature !=3D EFI_FVH_SIGNATURE) + || (FwVolHeader->FvLength !=3D FvLength) + ) + { + DEBUG ((DEBUG_ERROR, "%a: No Firmware Volume header present\n", + __FUNCTION__)); + return EFI_NOT_FOUND; + } + + // Check the Firmware Volume Guid + if( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) = =3D=3D FALSE ) { + DEBUG ((DEBUG_ERROR, "%a: Firmware Volume Guid non-compatible\n", + __FUNCTION__)); + return EFI_NOT_FOUND; + } + + // Verify the header checksum + Checksum =3D CalculateSum16 ((UINT16*)FwVolHeader, FwVolHeader->HeaderLe= ngth); + if (Checksum !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: FV checksum is invalid (Checksum:0x%X)\n", + __FUNCTION__, Checksum)); + return EFI_NOT_FOUND; + } + + VariableStoreHeader =3D (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader + + FwVolHeader->HeaderLength); + + // Check the Variable Store Guid + if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) && + !CompareGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVar= iableGuid)) { + DEBUG ((DEBUG_ERROR, "%a: Variable Store Guid non-compatible\n", + __FUNCTION__)); + return EFI_NOT_FOUND; + } + + VariableStoreLength =3D PcdGet32 (PcdFlashNvStorageVariableSize) - FwVol= Header->HeaderLength; + if (VariableStoreHeader->Size !=3D VariableStoreLength) { + DEBUG ((DEBUG_ERROR, "%a: Variable Store Length does not match\n", + __FUNCTION__)); + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + The GetAttributes() function retrieves the attributes and + current settings of the block. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL ins= tance. + + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attribut= es and + current settings are returned. + Type EFI_FVB_ATTRIBUTES_2 is defined in EFI_FIRMWARE_= VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were returned. + + **/ +EFI_STATUS +EFIAPI +FvbGetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + FlashFvbAttributes =3D (EFI_FVB_ATTRIBUTES_2) ( + + EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled + EFI_FVB2_READ_STATUS | // Reads are currently enabled + EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bit= s into EFI_FVB2_ERASE_POLARITY + EFI_FVB2_MEMORY_MAPPED | // It is memory mapped + EFI_FVB2_ERASE_POLARITY // After erasure all bits take this valu= e (i.e. '1') + + ); + + // Check if it is write protected + if (Instance->Media.ReadOnly !=3D TRUE) { + + FlashFvbAttributes =3D FlashFvbAttributes | + EFI_FVB2_WRITE_STATUS | // Writes are curren= tly enabled + EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be ena= bled + } + + *Attributes =3D FlashFvbAttributes; + + DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes)); + + return EFI_SUCCESS; +} + +/** + The SetAttributes() function sets configurable firmware volume attributes + and returns the new settings of the firmware volume. + + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_= PROTOCOL instance. + + @param Attributes On input, Attributes is a pointer to EFI_= FVB_ATTRIBUTES_2 + that contains the desired firmware volume= settings. + On successful return, it contains the new= settings of + the firmware volume. + Type EFI_FVB_ATTRIBUTES_2 is defined in E= FI_FIRMWARE_VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were retur= ned. + + @retval EFI_INVALID_PARAMETER The attributes requested are in conflict = with the capabilities + as declared in the firmware volume header. + + **/ +EFI_STATUS +EFIAPI +FvbSetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",*Attrib= utes)); + return EFI_UNSUPPORTED; +} + +/** + The GetPhysicalAddress() function retrieves the base address of + a memory-mapped firmware volume. This function should be called + only for memory-mapped firmware volumes. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOC= OL instance. + + @param Address Pointer to a caller-allocated + EFI_PHYSICAL_ADDRESS that, on successful + return from GetPhysicalAddress(), contains the + base address of the firmware volume. + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped. + + **/ +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + *Address =3D mFlashNvStorageVariableBase; + return EFI_SUCCESS; +} + +/** + The GetBlockSize() function retrieves the size of the requested + block. It also returns the number of additional blocks with + the identical size. The GetBlockSize() function is used to + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER). + + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_= PROTOCOL instance. + + @param Lba Indicates the block for which to return t= he size. + + @param BlockSize Pointer to a caller-allocated UINTN in wh= ich + the size of the block is returned. + + @param NumberOfBlocks Pointer to a caller-allocated UINTN in + which the number of consecutive blocks, + starting with Lba, is returned. All + blocks in this range have a size of + BlockSize. + + + @retval EFI_SUCCESS The firmware volume base address was retu= rned. + + @retval EFI_INVALID_PARAMETER The requested LBA is out of range. + + **/ +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ) +{ + EFI_STATUS Status; + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS(This); + + DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=3D%ld, BlockSize=3D0x%x, LastB= lock=3D%ld)\n", + Lba, Instance->Media.BlockSize, Instance->Media.LastBlock)); + + if (Lba > Instance->Media.LastBlock) { + DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%= ld)\n", + __FUNCTION__, Lba, Instance->Media.LastBlock)); + Status =3D EFI_INVALID_PARAMETER; + } else { + // In this platform each NorFlash device has equal sized blocks. + *BlockSize =3D (UINTN) Instance->Media.BlockSize; + *NumberOfBlocks =3D (UINTN) (Instance->Media.LastBlock - Lba + 1); + + DEBUG ((DEBUG_BLKIO, "%a : *BlockSize=3D0x%x, *NumberOfBlocks=3D0x%x.\= n", + __FUNCTION__, *BlockSize, *NumberOfBlocks)); + + Status =3D EFI_SUCCESS; + } + + return Status; +} + +/** + Reads the specified number of bytes into a buffer from the specified bloc= k. + + The Read() function reads the requested number of bytes from the + requested block and stores them in the provided buffer. + Implementations should be mindful that the firmware volume + might be in the ReadDisabled state. If it is in this state, + the Read() function must return the status code + EFI_ACCESS_DENIED without modifying the contents of the + buffer. The Read() function must also prevent spanning block + boundaries. If a read is requested that would span a block + boundary, the read must read up to the boundary but not + beyond. The output parameter NumBytes must be set to correctly + indicate the number of bytes actually read. The caller must be + aware that a read may be partially completed. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROT= OCOL instance. + + @param Lba The starting logical block index from which t= o read. + + @param Offset Offset into the block at which to begin readi= ng. + + @param NumBytes Pointer to a UINTN. + At entry, *NumBytes contains the total size o= f the buffer. + At exit, *NumBytes contains the total number = of bytes read. + + @param Buffer Pointer to a caller-allocated buffer that wil= l be used + to hold the data that is read. + + @retval EFI_SUCCESS The firmware volume was read successfully, a= nd contents are + in Buffer. + + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. + On output, NumBytes contains the total number= of bytes + returned in Buffer. + + @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled st= ate. + + @retval EFI_DEVICE_ERROR The block device is not functioning correctly= and could not be read. + + **/ +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ) +{ + UINTN BlockSize; + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=3D%ld, Offset=3D0x%x, " + "*NumBytes=3D0x%x, Buffer @ 0x%08x)\n", + Instance->StartLba + Lba, Offset, *NumBytes, Buffer)); + + if (!Instance->Initialized && Instance->Initialize) { + Instance->Initialize(Instance); + } + + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D Instance->Media.BlockSize; + + DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=3D0x%x + NumBytes=3D0x%x= ) <=3D " + "BlockSize=3D0x%x\n", Offset, *NumBytes, BlockSize )); + + // The read must not span block boundaries. + while (Offset >=3D BlockSize) { + Offset -=3D BlockSize; + Lba++; + } + + if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) { + DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%= ld)\n", + __FUNCTION__, Lba, Instance->Media.LastBlock)); + return EFI_INVALID_PARAMETER; + } + + if ((Offset + *NumBytes) > BlockSize) { + *NumBytes =3D BlockSize-Offset; + } + + return NorFlashPlatformRead (Instance, Instance->StartLba + Lba, + Offset, *NumBytes, Buffer); +} + +/** + Writes the specified number of bytes from the input buffer to the block. + + The Write() function writes the specified number of bytes from + the provided buffer to the specified block and offset. If the + firmware volume is sticky write, the caller must ensure that + all the bits of the specified range to write are in the + EFI_FVB_ERASE_POLARITY state before calling the Write() + function, or else the result will be unpredictable. This + unpredictability arises because, for a sticky-write firmware + volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY + state but cannot flip it back again. Before calling the + Write() function, it is recommended for the caller to first call + the EraseBlocks() function to erase the specified block to + write. A block erase cycle will transition bits from the + (NOT)EFI_FVB_ERASE_POLARITY state back to the + EFI_FVB_ERASE_POLARITY state. Implementations should be + mindful that the firmware volume might be in the WriteDisabled + state. If it is in this state, the Write() function must + return the status code EFI_ACCESS_DENIED without modifying the + contents of the firmware volume. The Write() function must + also prevent spanning block boundaries. If a write is + requested that spans a block boundary, the write must store up + to the boundary but not beyond. The output parameter NumBytes + must be set to correctly indicate the number of bytes actually + written. The caller must be aware that a write may be + partially completed. All writes, partial or otherwise, must be + fully flushed to the hardware before the Write() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROT= OCOL instance. + + @param Lba The starting logical block index to write to. + + @param Offset Offset into the block at which to begin writi= ng. + + @param NumBytes The pointer to a UINTN. + At entry, *NumBytes contains the total size o= f the buffer. + At exit, *NumBytes contains the total number = of bytes actually written. + + @param Buffer The pointer to a caller-allocated buffer that= contains the source for the write. + + @retval EFI_SUCCESS The firmware volume was written successfully. + + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundar= y. + On output, NumBytes contains the total number= of bytes + actually written. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled s= tate. + + @retval EFI_DEVICE_ERROR The block device is malfunctioning and could = not be written. + + + **/ +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + NOR_FLASH_INSTANCE *Instance; + UINTN BlockSize; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + // Cache the block size to avoid de-referencing pointers all the time + BlockSize =3D Instance->Media.BlockSize; + + if (!Instance->Initialized && Instance->Initialize) { + Instance->Initialize(Instance); + } + + // The write must not span block boundaries. + while(Offset >=3D BlockSize) { + Offset -=3D BlockSize; + Lba++; + } + + if ((Instance->StartLba + Lba) > Instance->Media.LastBlock) { + DEBUG ((DEBUG_ERROR, "%a : Parameter LBA %ld is beyond the last Lba (%= ld)\n", + __FUNCTION__, Lba, Instance->Media.LastBlock)); + return EFI_INVALID_PARAMETER; + } + + if ((Offset + *NumBytes) > BlockSize) { + *NumBytes =3D BlockSize-Offset; + } + + return NorFlashWrite (Instance, Instance->StartLba + Lba, + Offset, NumBytes, Buffer); +} + +/** + Erases and initialises a firmware volume block. + + The EraseBlocks() function erases one or more blocks as denoted + by the variable argument list. The entire parameter list of + blocks must be verified before erasing any blocks. If a block is + requested that does not exist within the associated firmware + volume (it has a larger index than the last block of the + firmware volume), the EraseBlocks() function must return the + status code EFI_INVALID_PARAMETER without modifying the contents + of the firmware volume. Implementations should be mindful that + the firmware volume might be in the WriteDisabled state. If it + is in this state, the EraseBlocks() function must return the + status code EFI_ACCESS_DENIED without modifying the contents of + the firmware volume. All calls to EraseBlocks() must be fully + flushed to the hardware before the EraseBlocks() service + returns. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_= PROTOCOL + instance. + + @param ... The variable argument list is a list of t= uples. + Each tuple describes a range of LBAs to e= rase + and consists of the following: + - An EFI_LBA that indicates the starting = LBA + - A UINTN that indicates the number of bl= ocks to erase. + + The list is terminated with an EFI_LBA_LI= ST_TERMINATOR. + For example, the following indicates that= two ranges of blocks + (5-7 and 10-11) are to be erased: + EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_L= IST_TERMINATOR); + + @retval EFI_SUCCESS The erase request successfully completed. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabl= ed state. + + @retval EFI_DEVICE_ERROR The block device is not functioning corre= ctly and could not be written. + The firmware device may have been partial= ly erased. + + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the var= iable argument list do + not exist in the firmware volume. + + **/ +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ) +{ + EFI_STATUS Status; + VA_LIST Args; + UINTN BlockAddress; // Physical address of Lba to erase + EFI_LBA StartingLba; // Lba from which we start erasing + UINTN NumOfLba; // Number of Lba blocks to erase + NOR_FLASH_INSTANCE *Instance; + + Instance =3D INSTANCE_FROM_FVB_THIS (This); + + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n")); + + Status =3D EFI_SUCCESS; + + // Detect WriteDisabled state + if (Instance->Media.ReadOnly =3D=3D TRUE) { + // Firmware volume is in WriteDisabled state + DEBUG ((DEBUG_ERROR, "%a : Device is in WriteDisabled state\n")); + return EFI_ACCESS_DENIED; + } + + // Before erasing, check the entire list of parameters to + // ensure all specified blocks are valid + + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba =3D VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + //Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba =3D VA_ARG (Args, UINT32); + + // All blocks must be within range + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Check if: ( StartingLba=3D%ld + " + "NumOfLba=3D%d - 1 ) > LastBlock=3D%ld.\n", + Instance->StartLba + StartingLba, NumOfLba, + Instance->Media.LastBlock)); + if ((NumOfLba =3D=3D 0) || + ((Instance->StartLba + StartingLba + NumOfLba - 1) > + Instance->Media.LastBlock)) { + VA_END (Args); + DEBUG ((DEBUG_ERROR, "%a : Lba range goes past the last Lba\n")); + Status =3D EFI_INVALID_PARAMETER; + goto EXIT; + } + } while (TRUE); + VA_END (Args); + + // + // To get here, all must be ok, so start erasing + // + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba =3D VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + // Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba =3D VA_ARG (Args, UINT32); + + // Go through each one and erase it + while (NumOfLba > 0) { + + // Get the physical address of Lba to erase + BlockAddress =3D GET_NOR_BLOCK_ADDRESS ( + Instance->RegionBaseAddress, + Instance->StartLba + StartingLba, + Instance->Media.BlockSize + ); + + // Erase it + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=3D%ld @ 0x%08x.\n", + Instance->StartLba + StartingLba, BlockAddress)); + Status =3D NorFlashPlatformEraseSector(Instance, BlockAddress); + if (EFI_ERROR (Status)) { + VA_END (Args); + Status =3D EFI_DEVICE_ERROR; + goto EXIT; + } + + // Move to the next Lba + StartingLba++; + NumOfLba--; + } + } while (TRUE); + VA_END (Args); + +EXIT: + return Status; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +FvbVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase); + return; +} + +EFI_STATUS +EFIAPI +NorFlashFvbInitialize ( + IN NOR_FLASH_INSTANCE* Instance + ) +{ + EFI_STATUS Status; + UINT32 FvbNumLba; + EFI_BOOT_MODE BootMode; + UINTN RuntimeMmioRegionSize; + + DEBUG ((DEBUG_BLKIO,"NorFlashFvbInitialize\n")); + + Instance->Initialized =3D TRUE; + mFlashNvStorageVariableBase =3D FixedPcdGet64 (PcdFlashNvStorageVariable= Base64); + + // Set the index of the first LBA for the FVB + Instance->StartLba =3D (PcdGet64 (PcdFlashNvStorageVariableBase64) - Ins= tance->RegionBaseAddress) / Instance->Media.BlockSize; + + BootMode =3D GetBootModeHob (); + if (BootMode =3D=3D BOOT_WITH_DEFAULT_SETTINGS) { + Status =3D EFI_INVALID_PARAMETER; + } + else { + // Determine if there is a valid header at the beginning of the NorFla= sh + Status =3D ValidateFvHeader (Instance); + } + + // Install the Default FVB header if required + if (EFI_ERROR (Status)) { + // There is no valid header, so time to install one. + DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__= )); + DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n", + __FUNCTION__)); + + // Erase all the NorFlash that is reserved for variable storage + FvbNumLba =3D (PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32 (Pc= dFlashNvStorageFtwWorkingSize) + PcdGet32 (PcdFlashNvStorageFtwSpareSize)) = / Instance->Media.BlockSize; + + Status =3D FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumL= ba, EFI_LBA_LIST_TERMINATOR); + if (EFI_ERROR (Status)) + return Status; + + // Install all appropriate headers + Status =3D InitializeFvAndVariableStoreHeaders (Instance); + if (EFI_ERROR (Status)) { + return Status; + } + } + + // + // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME + // + + // Note: all the NOR Flash region needs to be reserved into the UEFI Run= time memory; + // even if we only use the small block region at the top of the NO= R Flash. + // The reason is when the NOR Flash memory is set into program mod= e, the command + // is written as the base of the flash region (ie: Instance->Devic= eBaseAddress) + RuntimeMmioRegionSize =3D (Instance->RegionBaseAddress - Instance->Devic= eBaseAddress) + Instance->Size; + + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + Instance->DeviceBaseAddress, RuntimeMmioRegionSize, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gDS->SetMemorySpaceAttributes ( + Instance->DeviceBaseAddress, RuntimeMmioRegionSize, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); + ASSERT_EFI_ERROR (Status); + + // + // Register for the virtual address change event + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + FvbVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mFvbVirtualAddrChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/NXP/Include/Library/NorFlash.h b/Platform/NXP/Include= /Library/NorFlash.h new file mode 100644 index 0000000..37099ff --- /dev/null +++ b/Platform/NXP/Include/Library/NorFlash.h @@ -0,0 +1,222 @@ +/** @NorFlash.h + + Based on NOR flash access APIs used in ArmPlatformPkg/Drivers/NorFlashDx= e/NorFlashDxe.h + + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef __NOR_FLASH_H__ +#define __NOR_FLASH_H__ + +#include +#include + +#define NOR_FLASH_ERASE_RETRY 10 + +#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize) ( BaseAddr + (UINTN)((= Lba) * LbaSize) ) + +#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', '= r', '0') +#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE= , FvbProtocol, NOR_FLASH_SIGNATURE) +#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE= , BlockIoProtocol, NOR_FLASH_SIGNATURE) + +typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE; + +typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Ins= tance); + +typedef struct { + VENDOR_DEVICE_PATH Vendor; + EFI_DEVICE_PATH_PROTOCOL End; +} NOR_FLASH_DEVICE_PATH; + +struct _NOR_FLASH_INSTANCE { + UINT32 Signature; + EFI_HANDLE Handle; + BOOLEAN Initialized; + NOR_FLASH_INITIALIZE Initialize; + UINTN DeviceBaseAddress; + UINTN RegionBaseAddress; + UINTN Size; + EFI_LBA StartLba; + EFI_BLOCK_IO_PROTOCOL BlockIoProtocol; + EFI_BLOCK_IO_MEDIA Media; + BOOLEAN SupportFvb; + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; + VOID* ShadowBuffer; + NOR_FLASH_DEVICE_PATH DevicePath; +}; + +// +// NorFlashLib.c related +// + +EFI_STATUS +NorFlashPlatformWriteBuffer ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +NorFlashPlatformEraseSector ( + IN NOR_FLASH_INSTANCE *Instance, + IN UINTN SectorAddress + ); + +EFI_STATUS +NorFlashPlatformControllerInitialization ( + VOID + ); + +EFI_STATUS +NorFlashPlatformRead ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN BufferSizeInBytes, + OUT UINT8 *Buffer + ); + +EFI_STATUS +NorFlashPlatformReset ( + IN UINTN Instance + ); + +extern CONST EFI_GUID* CONST mNorFlashVariableGuid; + +// +// NorFlashFvbDxe.c +// + +EFI_STATUS +EFIAPI +NorFlashFvbInitialize ( + IN NOR_FLASH_INSTANCE* Instance + ); + +EFI_STATUS +EFIAPI +FvbGetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbSetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ); + +EFI_STATUS +EFIAPI +FvbGetBlockSize( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ); + +EFI_STATUS +EFIAPI +FvbRead( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbWrite( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbEraseBlocks( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ); +// +// NorFlashBlockIoDxe.c +// + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset +// +EFI_STATUS +EFIAPI +NorFlashBlockIoReset ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN BOOLEAN ExtendedVerification + ); + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoReadBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + OUT VOID *Buffer +); + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoWriteBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This, + IN UINT32 MediaId, + IN EFI_LBA Lba, + IN UINTN BufferSizeInBytes, + IN VOID *Buffer +); + +// +// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks +// +EFI_STATUS +EFIAPI +NorFlashBlockIoFlushBlocks ( + IN EFI_BLOCK_IO_PROTOCOL *This +); + +EFI_STATUS +NorFlashWrite ( + IN NOR_FLASH_INSTANCE *Instance, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer +); + +#endif /* __NOR_FLASH_DXE_H__ */ diff --git a/Silicon/NXP/Chassis/Chassis.c b/Silicon/NXP/Chassis/Chassis.c index a6a77c2..ab0076f 100644 --- a/Silicon/NXP/Chassis/Chassis.c +++ b/Silicon/NXP/Chassis/Chassis.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -411,3 +412,17 @@ CalculateI2cClockRate ( =20 return SocSysInfo.FreqSystemBus; } + +/** + Initialize IFC device timings +**/ +VOID +IfcInit ( + VOID + ) +{ + // NOR Init + if (FixedPcdGet64 (PcdIfcNorEnabled)) { + IfcNorInit (); + } +} diff --git a/Silicon/NXP/Chassis/Chassis.h b/Silicon/NXP/Chassis/Chassis.h index 4bdb4d0..c8057f0 100644 --- a/Silicon/NXP/Chassis/Chassis.h +++ b/Silicon/NXP/Chassis/Chassis.h @@ -141,4 +141,11 @@ CpuNumCores ( VOID ); =20 +/** + Initialize IFC Device timings + **/ +VOID +IfcInit ( + VOID + ); #endif /* __CHASSIS_H__ */ diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chass= is2/Soc.c index 2f57929..847bbc2 100644 --- a/Silicon/NXP/Chassis/Chassis2/Soc.c +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c @@ -140,6 +140,7 @@ SocInit ( =20 PrintCpuInfo (); PrintRCW (); + IfcInit (); =20 return; } diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS= 1043aSocLib.inf index e6e7ac4..b11fdc2 100644 --- a/Silicon/NXP/Chassis/LS1043aSocLib.inf +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf @@ -32,6 +32,7 @@ BeIoLib DebugLib SerialPortLib + NorFlashLib =20 [Sources.common] Chassis.c @@ -45,3 +46,4 @@ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcNorEnabled --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 11:53:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1513744936445747.7361226529504; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2696 Subject: [edk2] [PATCH edk2-platforms v2 4/4] Compilation:Modify dsc, fdf files and add inc file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Enabling support for compilation of IfcFlashLib, NorFlashLib,Nor flash Driver and include runtime variable support Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 22 +++++++ Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf | 9 ++- Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc | 98 ++++++++++++++++++++++++= ++++ Platform/NXP/NxpQoriqLs.dsc | 5 ++ 4 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index 7a72338..e0c02b1 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -39,6 +39,16 @@ SocLib|edk2-platforms/Silicon/NXP/Chassis/LS1043aSocLib.inf RealTimeClockLib|edk2-platforms/Silicon/Maxim/Library/Ds1307RtcLib/Ds130= 7RtcLib.inf =20 + # + # Nor Lib + # + NorFlashLib|edk2-platforms/Platform/NXP/Library/NorFlashLib/NorFlashLib.= inf + + # + # IFC FLASH Lib + # + IfcFlashLib|edk2-platforms/Platform/NXP/Library/IfcFlashLib/IfcFlashLib.= inf + [PcdsFixedAtBuild.common] gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"LS1043a RDB board" =20 @@ -57,6 +67,13 @@ gNxpQoriqLsTokenSpaceGuid.PcdIfcBigEndian|TRUE =20 # + # NV Storage PCDs. + # + gArmTokenSpaceGuid.PcdVFPEnabled|1 + gNxpQoriqLsTokenSpaceGuid.PcdFlashDeviceBase64|0x060000000 + gNxpQoriqLsTokenSpaceGuid.PcdFlashReservedRegionBase64|0x60300000 + + # # I2C controller Pcds # gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0 @@ -76,4 +93,9 @@ edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf =20 + # + # NOR + # + edk2-platforms/Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf + ## diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.fdf index 44f452a..7d69624 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.fdf @@ -54,6 +54,7 @@ NumBlocks =3D 0xEC890 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV =3D FVMAIN_COMPACT =20 +!include VarStore.fdf.inc =20 ##########################################################################= ###### # @@ -103,7 +104,8 @@ READ_LOCK_STATUS =3D TRUE INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf - INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.= inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf =20 @@ -120,6 +122,11 @@ READ_LOCK_STATUS =3D TRUE INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf =20 # + # NOR Driver + # + INF edk2-platforms/Platform/NXP/Drivers/NorFlashDxe/NorFlashDxe.inf + + # # Network modules # INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc b/Platform/NXP/LS1= 043aRdbPkg/VarStore.fdf.inc new file mode 100644 index 0000000..8fb8e42 --- /dev/null +++ b/Platform/NXP/LS1043aRdbPkg/VarStore.fdf.inc @@ -0,0 +1,98 @@ +## @file +# FDF include file with FD definition that defines an empty variable stor= e. +# +# Copyright (c) 2016, Freescale Semiconductor. All rights reserved. +# Copyright (c) 2016, Linaro, Ltd. All rights reserved. +# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved. +# +# This program and the accompanying materials are licensed and made avail= able +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[FD.LS1043aRdbNv_EFI] + +BaseAddress =3D 0x60300000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdBase #The base= address of the FLASH device +Size =3D 0x000C0000|gNxpQoriqLsTokenSpaceGuid.PcdNvFdSize #The size in by= tes of the FLASH device +ErasePolarity =3D 1 +BlockSize =3D 0x1 +NumBlocks =3D 0xC0000 + +# +# Place NV Storage just above Platform Data Base +# +DEFINE NVRAM_AREA_VARIABLE_BASE =3D 0x00000000 +DEFINE NVRAM_AREA_VARIABLE_SIZE =3D 0x00040000 +DEFINE FTW_WORKING_BASE =3D $(NVRAM_AREA_VARIABLE_B= ASE) + $(NVRAM_AREA_VARIABLE_SIZE) +DEFINE FTW_WORKING_SIZE =3D 0x00040000 +DEFINE FTW_SPARE_BASE =3D $(FTW_WORKING_BASE) + $= (FTW_WORKING_SIZE) +DEFINE FTW_SPARE_SIZE =3D 0x00040000 + +##########################################################################= ### +# LS1043ARDB NVRAM Area +# LS1043ARDB NVRAM Area contains: Variable + FTW Working + FTW Spare +##########################################################################= ### + + +$(NVRAM_AREA_VARIABLE_BASE)|$(NVRAM_AREA_VARIABLE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0xC0000 + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0x36, 0x0E, 0x00, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0xC2, 0xF9, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block + 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER + # It is compatible with SECURE_BOOT_ENABLE =3D=3D FALSE as well. + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, + # Size: 0x40000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariabl= eSize) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x3ffb8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xFF, 0x03, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_WORKING_BASE)|$(FTW_WORKING_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +$(FTW_SPARE_BASE)|$(FTW_SPARE_SIZE) +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE diff --git a/Platform/NXP/NxpQoriqLs.dsc b/Platform/NXP/NxpQoriqLs.dsc index 768a9e8..30f1c29 100644 --- a/Platform/NXP/NxpQoriqLs.dsc +++ b/Platform/NXP/NxpQoriqLs.dsc @@ -350,6 +350,11 @@ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf{ + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel