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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR03MB2689 Subject: [edk2] [PATCH 1/4] Silicon/NXP:SocLib support for initialization of peripherals X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds SocInit function to initialize peripherals and print board,soc information. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Silicon/NXP/Chassis/Chassis2/Soc.c | 47 ++++++++++++++++++++++++++++ Silicon/NXP/Chassis/LS1043aSocLib.inf | 2 ++ Silicon/NXP/Chassis/LS1046aSocLib.inf | 49 +++++++++++++++++++++++++++++ Silicon/NXP/LS1046A/Include/SocSerDes.h | 55 +++++++++++++++++++++++++++++= ++++ 4 files changed, 153 insertions(+) create mode 100644 Silicon/NXP/Chassis/LS1046aSocLib.inf create mode 100644 Silicon/NXP/LS1046A/Include/SocSerDes.h diff --git a/Silicon/NXP/Chassis/Chassis2/Soc.c b/Silicon/NXP/Chassis/Chass= is2/Soc.c index ff9575a..36ac886 100644 --- a/Silicon/NXP/Chassis/Chassis2/Soc.c +++ b/Silicon/NXP/Chassis/Chassis2/Soc.c @@ -116,6 +116,43 @@ GetSysInfo ( } =20 /** + Function to select pins depending upon pcd using supplemental + configuration unit(SCFG) extended RCW controlled pinmux control + register which contains the bits to provide pin multiplexing control. + This register is reset on HRESET. + **/ +VOID +ConfigScfgMux (VOID) +{ + CCSR_SCFG *Scfg; + UINT32 UsbPwrFault; + + Scfg =3D (VOID *)PcdGet64 (PcdScfgBaseAddr); + // Configures functionality of the IIC3_SCL to USB2_DRVVBUS + // Configures functionality of the IIC3_SDA to USB2_PWRFAULT + + // LS1043A + // Configures functionality of the IIC4_SCL to USB3_DRVVBUS + // Configures functionality of the IIC4_SDA to USB3_PWRFAULT + + // LS1046A + // USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA + if (PcdGetBool(PcdMuxToUsb3)) + MmioWriteBe32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_SELCR_US= B); + else + MmioWriteBe32 ((UINTN)&Scfg->RcwPMuxCr0, CCSR_SCFG_RCWPMUXCRO_NOT_SELC= R_USB); + MmioWriteBe32 ((UINTN)&Scfg->UsbDrvVBusSelCr, CCSR_SCFG_USBDRVVBUS_SELCR= _USB1); + UsbPwrFault =3D (CCSR_SCFG_USBPWRFAULT_DEDICATED << + CCSR_SCFG_USBPWRFAULT_USB3_SHIFT) | + (CCSR_SCFG_USBPWRFAULT_DEDICATED << + CCSR_SCFG_USBPWRFAULT_USB2_SHIFT) | + (CCSR_SCFG_USBPWRFAULT_SHARED << + CCSR_SCFG_USBPWRFAULT_USB1_SHIFT); + MmioWriteBe32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); + MmioWriteBe32 ((UINTN)&Scfg->UsbPwrFaultSelCr, UsbPwrFault); +} + +/** Function to initialize SoC specific constructs // CPU Info // SoC Personality @@ -141,5 +178,15 @@ SocInit ( PrintCpuInfo (); PrintRCW (); =20 + // + // Due to the extensive functionality present on the chip and the limite= d number of external + // signals available, several functional blocks share signal resources t= hrough multiplexing. + // In this case when there is alternate functionality between multiple f= unctional blocks, + // the signal's function is determined at the chip level (rather than at= the block level) + // typically by a reset configuration word (RCW) option. Some of the sig= nals' function are + // determined externel to RCW at Power-on Reset Sequence. + // + ConfigScfgMux(); + return; } diff --git a/Silicon/NXP/Chassis/LS1043aSocLib.inf b/Silicon/NXP/Chassis/LS= 1043aSocLib.inf index a7c6ee5..e12a705 100644 --- a/Silicon/NXP/Chassis/LS1043aSocLib.inf +++ b/Silicon/NXP/Chassis/LS1043aSocLib.inf @@ -45,3 +45,5 @@ gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3 + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr diff --git a/Silicon/NXP/Chassis/LS1046aSocLib.inf b/Silicon/NXP/Chassis/LS= 1046aSocLib.inf new file mode 100644 index 0000000..9422a2a --- /dev/null +++ b/Silicon/NXP/Chassis/LS1046aSocLib.inf @@ -0,0 +1,49 @@ +# @file +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D SocLib + FILE_GUID =3D 5e9a2b48-a92a-4d55-87ec-e5e14a292f35 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SocLib + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + Silicon/NXP/Chassis/Chassis2/Chassis2.dec + Silicon/NXP/LS1046A/LS1046A.dec + +[LibraryClasses] + BaseLib + BeIoLib + DebugLib + SerialPortLib + +[Sources.common] + Chassis.c + Chassis2/Soc.c + SerDes.c + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3 + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr diff --git a/Silicon/NXP/LS1046A/Include/SocSerDes.h b/Silicon/NXP/LS1046A/= Include/SocSerDes.h new file mode 100644 index 0000000..a0b5576 --- /dev/null +++ b/Silicon/NXP/LS1046A/Include/SocSerDes.h @@ -0,0 +1,55 @@ +/** @file + The Header file of SerDes Module + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD= License + which accompanies this distribution. The full text of the license may be = found + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPL= IED. + +**/ + +#ifndef __LS1046A_SERDES_H__ +#define __LS1046A_SERDES_H__ + +#include + +SERDES_CONFIG SerDes1ConfigTbl[] =3D { + /* SerDes 1 */ + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, S= GMII_FM1_DTSEC6 } }, + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, SGMII_FM1= _DTSEC6 } }, + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, SGMII= _FM1_DTSEC6 } }, + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSE= C5, SGMII_FM1_DTSEC6 } }, + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_FM1= _DTSEC5, SGMII_FM1_DTSEC6 } }, + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE } }, + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE } }, + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6 } }, + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, SG= MII_FM1_DTSEC6 } }, + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, SGMII_FM1_DTS= EC6 } }, + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, SGMII_250= 0_FM1_DTSEC5, SGMII_FM1_DTSEC6 } }, + {} +}; + +SERDES_CONFIG SerDes2ConfigTbl[] =3D { + /* SerDes 2 */ + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1 } }, + {0x5559, {PCIE1, PCIE2, PCIE3, SATA } }, + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3 } }, + {0x5506, {PCIE1, PCIE2, NONE, PCIE3 } }, + {0x0506, {NONE, PCIE2, NONE, PCIE3 } }, + {0x0559, {NONE, PCIE2, PCIE3, SATA } }, + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA } }, + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3 } }, + {} +}; + +SERDES_CONFIG *SerDesConfigTbl[] =3D { + SerDes1ConfigTbl, + SerDes2ConfigTbl +}; + +#endif /* __LS1046A_SERDES_H */ --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 03:46:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1512144967529839.4502769954754; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR03MB2699 Subject: [edk2] [PATCH 2/4] Silicon/NXP:Add support for PCF2129 Real Time Clock Library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch add support for NXP pcf2129 real time clock library Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Platform/NXP/Drivers/I2cDxe/I2cDxe.c | 17 +- Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h | 43 +++ Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c | 375 +++++++++++++++++= ++++ .../NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf | 47 +++ 4 files changed, 474 insertions(+), 8 deletions(-) create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c create mode 100644 Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf diff --git a/Platform/NXP/Drivers/I2cDxe/I2cDxe.c b/Platform/NXP/Drivers/I2= cDxe/I2cDxe.c index 30eb6f4..ffbee74 100644 --- a/Platform/NXP/Drivers/I2cDxe/I2cDxe.c +++ b/Platform/NXP/Drivers/I2cDxe/I2cDxe.c @@ -538,7 +538,8 @@ StartRequest ( UINT32 Length; UINT8 *Buffer; UINT32 Flag; - UINT8 RegAddress; + UINT32 RegAddress; + UINT32 OffsetLength; =20 RegAddress =3D 0; =20 @@ -548,7 +549,10 @@ StartRequest ( return EFI_INVALID_PARAMETER; } =20 - for (Count =3D 0; Count < RequestPacket->OperationCount; Count++) { + OffsetLength =3D RequestPacket->Operation[0].LengthInBytes; + RegAddress =3D *RequestPacket->Operation[0].Buffer; + + for (Count =3D 1; Count < RequestPacket->OperationCount; Count++) { Flag =3D RequestPacket->Operation[Count].Flags; Length =3D RequestPacket->Operation[Count].LengthInBytes; Buffer =3D RequestPacket->Operation[Count].Buffer; @@ -559,12 +563,9 @@ StartRequest ( return EFI_INVALID_PARAMETER; } =20 - if (Flag =3D=3D I2C_FLAG_WRITE && Count =3D=3D 0) { - RegAddress =3D *Buffer; - continue; - } else if (Flag =3D=3D I2C_FLAG_READ) { + if (Flag =3D=3D I2C_FLAG_READ) { Ret =3D I2cDataRead (PcdGet32 (PcdI2cBus), SlaveAddress, - RegAddress, sizeof(SlaveAddress)/8, Buffer, Length); + RegAddress, OffsetLength, Buffer, Length); if (Ret !=3D EFI_SUCCESS) { DEBUG ((DEBUG_ERROR,"%a: I2c read operation failed (error %d)\n", __FUNCTION__, Ret)); @@ -572,7 +573,7 @@ StartRequest ( } } else if (Flag =3D=3D I2C_FLAG_WRITE) { Ret =3D I2cDataWrite (PcdGet32 (PcdI2cBus), SlaveAddress, - RegAddress, sizeof(SlaveAddress)/8, Buffer, Length); + RegAddress, OffsetLength, Buffer, Length); if (Ret !=3D EFI_SUCCESS) { DEBUG ((DEBUG_ERROR,"%a: I2c write operation failed (error %d)\n", __FUNCTION__, Ret)); diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h b/Silicon/NXP/L= ibrary/Pcf2129RtcLib/Pcf2129Rtc.h new file mode 100644 index 0000000..735f697 --- /dev/null +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129Rtc.h @@ -0,0 +1,43 @@ +/** Pcf2129Rtc.h +* +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#ifndef __PCF2129RTC_H__ +#define __PCF2129RTC_H__ + +/* + * RTC register addresses + */ +#define PCF2129_CTRL1_REG_ADDR 0x00 // Control Register 1 +#define PCF2129_CTRL2_REG_ADDR 0x01 // Control Register 2 +#define PCF2129_CTRL3_REG_ADDR 0x02 // Control Register 3 +#define PCF2129_SEC_REG_ADDR 0x03 +#define PCF2129_MIN_REG_ADDR 0x04 +#define PCF2129_HR_REG_ADDR 0x05 +#define PCF2129_DAY_REG_ADDR 0x06 +#define PCF2129_WEEKDAY_REG_ADDR 0x07 +#define PCF2129_MON_REG_ADDR 0x08 +#define PCF2129_YR_REG_ADDR 0x09 + +#define PCF2129_CTRL3_BIT_BLF BIT2 /* Battery Low Flag*/ + +// Define EPOCH (1998-JANUARY-01) in the Julian Date representation +#define EPOCH_JULIAN_DATE 2450815 + +typedef struct { + UINTN OperationCount; + EFI_I2C_OPERATION SetAddressOp; + EFI_I2C_OPERATION GetSetDateTimeOp; +} RTC_I2C_REQUEST; + +#endif // __PCF2129RTC_H__ diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c b/Silicon/NX= P/Library/Pcf2129RtcLib/Pcf2129RtcLib.c new file mode 100644 index 0000000..b4ee61f --- /dev/null +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.c @@ -0,0 +1,375 @@ +/** @PCF2129RtcLib.c + Implement EFI RealTimeClock with runtime services via RTC Lib for PCF212= 9 RTC. + + Based on RTC implementation available in + EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
+ Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Pcf2129Rtc.h" + +STATIC VOID *mDriverEventRegistration; +STATIC EFI_I2C_MASTER_PROTOCOL *mI2cMaster; + +/** + returns Day of the week [0-6] 0=3DSunday + Don't try to provide a Year that's before 1998, please ! + **/ +UINTN +EfiTimeToWday ( + IN EFI_TIME *Time + ) +{ + UINTN a; + UINTN y; + UINTN m; + UINTN JulianDate; // Absolute Julian Date representation of the supplie= d Time + UINTN EpochDays; // Number of days elapsed since EPOCH_JULIAN_DAY + + a =3D (14 - Time->Month) / 12 ; + y =3D Time->Year + 4800 - a; + m =3D Time->Month + (12*a) - 3; + + JulianDate =3D Time->Day + ((153*m + 2)/5) + (365*y) + (y/4) - (y/100) += (y/400) - 32045; + + ASSERT (JulianDate >=3D EPOCH_JULIAN_DATE); + EpochDays =3D JulianDate - EPOCH_JULIAN_DATE; + + // 4=3D1/1/1998 was a Thursday + + return (EpochDays + 4) % 7; +} + +/** + Write RTC register. + + @param RtcRegAddr Register offset of RTC to write. + @param Val Value to be written + +**/ + +STATIC +VOID +RtcWrite ( + IN UINT8 RtcRegAddr, + IN UINT8 Val + ) +{ + RTC_I2C_REQUEST Req; + EFI_STATUS Status; + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D 0; + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D 0; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Val); + Req.GetSetDateTimeOp.Buffer =3D &Val; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr)); + } + +} + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot= of the current time. + @param Capabilities An optional pointer to a buffer to receive= the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to har= dware error. + +**/ + +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status; + UINT8 Buffer[10]; + RTC_I2C_REQUEST Req; + UINT8 RtcRegAddr; + + Status =3D EFI_SUCCESS; + RtcRegAddr =3D PCF2129_CTRL1_REG_ADDR; + Buffer[0] =3D 0; + + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + RtcWrite (PCF2129_CTRL1_REG_ADDR, Buffer[0]); + + if (Time =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Req.OperationCount =3D 2; + + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D 0; + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D I2C_FLAG_READ; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Buffer); + Req.GetSetDateTimeOp.Buffer =3D Buffer; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC read error at Addr:0x%x\n", RtcRegAddr)); + } + + if (Buffer[PCF2129_CTRL3_REG_ADDR] & PCF2129_CTRL3_BIT_BLF) { + DEBUG((DEBUG_INFO, "### Warning: RTC battery status low, check/replace= RTC battery.\n")); + } + + Time->Nanosecond =3D 0; + Time->Second =3D BcdToDecimal8 (Buffer[PCF2129_SEC_REG_ADDR] & 0x7F); + Time->Minute =3D BcdToDecimal8 (Buffer[PCF2129_MIN_REG_ADDR] & 0x7F); + Time->Hour =3D BcdToDecimal8 (Buffer[PCF2129_HR_REG_ADDR] & 0x3F); + Time->Day =3D BcdToDecimal8 (Buffer[PCF2129_DAY_REG_ADDR] & 0x3F); + Time->Month =3D BcdToDecimal8 (Buffer[PCF2129_MON_REG_ADDR] & 0x1F); + Time->Year =3D BcdToDecimal8 (Buffer[PCF2129_YR_REG_ADDR]) + ( BcdToDeci= mal8 (Buffer[PCF2129_YR_REG_ADDR]) >=3D 98 ? 1900 : 2000); + + return Status; +} + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardw= are error. + +**/ + +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + UINT8 Buffer[8]; + UINT8 Index; + EFI_STATUS Status; + RTC_I2C_REQUEST Req; + UINT8 RtcRegAddr; + + Index =3D 0; + Status =3D EFI_SUCCESS; + RtcRegAddr =3D PCF2129_CTRL1_REG_ADDR; + + if (mI2cMaster =3D=3D NULL) { + return EFI_DEVICE_ERROR; + } + + // start register address + Buffer[Index++] =3D PCF2129_SEC_REG_ADDR; + + // hours, minutes and seconds + Buffer[Index++] =3D DecimalToBcd8 (Time->Second); + Buffer[Index++] =3D DecimalToBcd8 (Time->Minute); + Buffer[Index++] =3D DecimalToBcd8 (Time->Hour); + Buffer[Index++] =3D DecimalToBcd8 (Time->Day); + Buffer[Index++] =3D EfiTimeToWday (Time) & 0x07; + Buffer[Index++] =3D DecimalToBcd8 (Time->Month); + Buffer[Index++] =3D DecimalToBcd8 (Time->Year % 100); + + Req.OperationCount =3D 2; + Req.SetAddressOp.Flags =3D 0; + Req.SetAddressOp.LengthInBytes =3D 0; + Req.SetAddressOp.Buffer =3D &RtcRegAddr; + + Req.GetSetDateTimeOp.Flags =3D 0; + Req.GetSetDateTimeOp.LengthInBytes =3D sizeof (Buffer); + Req.GetSetDateTimeOp.Buffer =3D Buffer; + + Status =3D mI2cMaster->StartRequest (mI2cMaster, FixedPcdGet8 (PcdI2cSla= veAddress), + (VOID *)&Req, + NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC write error at Addr:0x%x\n", RtcRegAddr)); + return Status; + } + + return Status; +} + + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enable= d or disabled. + @param Pending Indicates if the alarm signal is pending a= nd requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due= to a hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wak= eup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm w= as enabled. If + Enable is FALSE, then the wakeup alarm was= disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a = hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // + // Only needed if you are going to support the OS calling RTC functions = in virtual mode. + // You will need to call EfiConvertPointer (). To convert any stored phy= sical addresses + // to virtual address. After the OS transistions to calling in virtual m= ode, all future + // runtime calls will be made in virtual mode. + // +// EfiConvertPointer (0x0, (VOID**)&mI2cBaseAddress); + return; +} + +STATIC +VOID +I2cDriverRegistrationEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_I2C_MASTER_PROTOCOL *I2cMaster; + UINTN BusFrequency; + + Status =3D gBS->LocateProtocol (&gEfiI2cMasterProtocolGuid, NULL, (VOID = **)&I2cMaster); + + gBS->CloseEvent (Event); + + ASSERT_EFI_ERROR (Status); + + Status =3D I2cMaster->Reset (I2cMaster); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->Reset () failed - %r\n", + __FUNCTION__, Status)); + return; + } + + BusFrequency =3D FixedPcdGet16 (PcdI2cSpeed); + Status =3D I2cMaster->SetBusFrequency (I2cMaster, &BusFrequency); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: I2CMaster->SetBusFrequency () failed - %r\n", + __FUNCTION__, Status)); + return; + } + + mI2cMaster =3D I2cMaster; +} + +/** + This is the declaration of an EFI image entry point. This can be the ent= ry point to an application + written to this specification, an EFI boot service driver, or an EFI run= time driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + // + // Register a protocol registration notification callback on the driver + // binding protocol so we can attempt to connect our I2C master to it + // as soon as it appears. + // + EfiCreateProtocolNotifyEvent ( + &gEfiI2cMasterProtocolGuid, + TPL_CALLBACK, + I2cDriverRegistrationEvent, + NULL, + &mDriverEventRegistration); + + return EFI_SUCCESS; +} diff --git a/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf b/Silicon/= NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf new file mode 100644 index 0000000..8edcc73 --- /dev/null +++ b/Silicon/NXP/Library/Pcf2129RtcLib/Pcf2129RtcLib.inf @@ -0,0 +1,47 @@ +#/** @Pcf2129RtcLib.inf +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# +#**/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Pcf2129RtcLib + FILE_GUID =3D B661E02D-A90B-42AB-A5F9-CF841AAA43D9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RealTimeClockLib + + +[Sources.common] + Pcf2129RtcLib.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + UefiLib + +[Protocols] + gEfiDriverBindingProtocolGuid ## CONSUMES + gEfiI2cMasterProtocolGuid ## CONSUMES + +[Pcd] + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress + +[Depex] + gEfiI2cMasterProtocolGuid --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 03:46:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2694 Subject: [edk2] [PATCH 3/4] Platform/NXP: Add support for ArmPlatformLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============1189107970882970158==" Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 --===============1189107970882970158== Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds support of adding ArmPlatformLib for NXP LS1046ARDB board Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- .../Library/PlatformLib/ArmPlatformLib.c | 106 ++++++++++++ .../Library/PlatformLib/ArmPlatformLib.inf | 70 ++++++++ .../Library/PlatformLib/NxpQoriqLsHelper.S | 39 +++++ .../Library/PlatformLib/NxpQoriqLsMem.c | 181 +++++++++++++++++= ++++ 4 files changed, 396 insertions(+) create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.c create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatf= ormLib.inf create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriq= LsHelper.S create mode 100644 Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriq= LsMem.c diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.= c b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c new file mode 100644 index 0000000..e2b645f --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.c @@ -0,0 +1,106 @@ +/** ArmPlatformLib.c +* +* Contains board initialization functions. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c +* +* Copyright (c) 2011-2012, ARM Limited. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include +#include + +extern VOID SocInit(VOID); + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Placeholder for Platform Initialization +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + SocInit(); + return RETURN_SUCCESS; +} + +ARM_CORE_INFO LS1046aMpCoreInfoCTA72x4[] =3D { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (EFI_PHYSICAL_ADDRESS)0, + (UINT64)0xFFFFFFFF + }, +}; + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount =3D sizeof(LS1046aMpCoreInfoCTA72x4) / sizeof(ARM_CORE_INF= O); + *ArmCoreTable =3D LS1046aMpCoreInfoCTA72x4; + + return EFI_SUCCESS; +} + +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize =3D sizeof(gPlatformPpiTable); + *PpiList =3D gPlatformPpiTable; +} + + +UINTN +ArmPlatformGetCorePosition ( + IN UINTN MpId + ) +{ + return 1; +} diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.= inf b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf new file mode 100644 index 0000000..033f77a --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/ArmPlatformLib.inf @@ -0,0 +1,70 @@ +#/* @file +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D ArmPlatformLib + FILE_GUID =3D 177a95a8-27c2-4582-8ba9-c87aa3e0ba75 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D ArmPlatformLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Platform/NXP/NxpQoriqLs.dec + +[LibraryClasses] + ArmLib + SocLib + +[Sources.common] + NxpQoriqLsHelper.S | GCC + ArmPlatformLib.c + NxpQoriqLsMem.c + +[Ppis] + gArmMpCoreInfoPpiGuid + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCore + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionBaseAddr + gNxpQoriqLsTokenSpaceGuid.PcdQspiRegionSize diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelpe= r.S b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S new file mode 100644 index 0000000..55e750f --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsHelper.S @@ -0,0 +1,39 @@ +# @file +# +# Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardHelper.S +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +#include +#include + +.text +.align 2 + +GCC_ASM_IMPORT(ArmReadMpidr) + +ASM_FUNC(ArmPlatformIsPrimaryCore) + tst x0, #3 + cset x0, eq + ret + +ASM_FUNC(ArmPlatformPeiBootAction) +EL1_OR_EL2(x0) +1: +2: + ret + +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (x0, FixedPcdGet32(PcdArmPrimaryCore)) + ldrh w0, [x0] + ret diff --git a/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c= b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c new file mode 100644 index 0000000..613ff04 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/Library/PlatformLib/NxpQoriqLsMem.c @@ -0,0 +1,181 @@ +/** NxpQoriqLsMem.c +* +* Board memory specific Library. +* +* Based on BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoardMem.c +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* Copyright (c) 2016, Freescale Semiconductor, Inc. All rights reserved. +* Copyright 2017 NXP +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may b= e found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include +#include +#include +#include + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 25 + +#define CCSR_BASE_ADDR FixedPcdGet64 (PcdCcsrBaseAddr) +#define CCSR_SIZE FixedPcdGet64 (PcdCcsrSize) +#define IFC_REGION1_BASE_ADDR FixedPcdGet64 (PcdIfcRegion1BaseAddr) +#define IFC_REGION1_SIZE FixedPcdGet64 (PcdIfcRegion1Size) +#define IFC_REGION2_BASE_ADDR FixedPcdGet64 (PcdIfcRegion2BaseAddr) +#define IFC_REGION2_SIZE FixedPcdGet64 (PcdIfcRegion2Size) +#define QMAN_SWP_BASE_ADDR FixedPcdGet64 (PcdQmanSwpBaseAddr) +#define QMAN_SWP_SIZE FixedPcdGet64 (PcdQmanSwpSize) +#define BMAN_SWP_BASE_ADDR FixedPcdGet64 (PcdBmanSwpBaseAddr) +#define BMAN_SWP_SIZE FixedPcdGet64 (PcdBmanSwpSize) +#define PCI_EXP1_BASE_ADDR FixedPcdGet64 (PcdPciExp1BaseAddr) +#define PCI_EXP1_BASE_SIZE FixedPcdGet64 (PcdPciExp1BaseSize) +#define PCI_EXP2_BASE_ADDR FixedPcdGet64 (PcdPciExp2BaseAddr) +#define PCI_EXP2_BASE_SIZE FixedPcdGet64 (PcdPciExp2BaseSize) +#define PCI_EXP3_BASE_ADDR FixedPcdGet64 (PcdPciExp3BaseAddr) +#define PCI_EXP3_BASE_SIZE FixedPcdGet64 (PcdPciExp3BaseSize) +#define DRAM1_BASE_ADDR FixedPcdGet64 (PcdDram1BaseAddr) +#define DRAM1_SIZE FixedPcdGet64 (PcdDram1Size) +#define DRAM2_BASE_ADDR FixedPcdGet64 (PcdDram2BaseAddr) +#define DRAM2_SIZE FixedPcdGet64 (PcdDram2Size) +#define DRAM3_BASE_ADDR FixedPcdGet64 (PcdDram3BaseAddr) +#define DRAM3_SIZE FixedPcdGet64 (PcdDram3Size) +#define QSPI_REGION_BASE_ADDR FixedPcdGet64 (PcdQspiRegionBaseAddr) +#define QSPI_REGION_SIZE FixedPcdGet64 (PcdQspiRegionSize) + + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize th= e MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR = describing a Physical-to- + Virtual Memory mapping. This array mus= t be ended by a zero-filled + entry + +**/ + +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index =3D 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap !=3D NULL); + + VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_= SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MA= P_DESCRIPTORS)); + if (VirtualMemoryTable =3D=3D NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) =3D=3D TRUE) { + CacheAttributes =3D ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + } else { + CacheAttributes =3D ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + } + + // DRAM1 (Must be 1st entry) + VirtualMemoryTable[Index].PhysicalBase =3D DRAM1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D DRAM1_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D DRAM1_SIZE; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // CCSR Space + VirtualMemoryTable[++Index].PhysicalBase =3D CCSR_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D CCSR_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D CCSR_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // IFC region 1 + // + // A-009241 : Unaligned write transactions to IFC may result in corrup= tion of data + // Affects : IFC + // Description: 16 byte unaligned write from system bus to IFC may resul= t in extra unintended + // writes on external IFC interface that can corrupt data o= n external flash. + // Impact : Data corruption on external flash may happen in case of = unaligned writes to + // IFC memory space. + // Workaround: Following are the workarounds: + // =EF=BF=BD For write transactions from core, IFC interface= memories (including IFC SRAM) + // should be configured as =EF=BF=BDdevice type" memory i= n MMU. + // =EF=BF=BD For write transactions from non-core masters (l= ike system DMA), the address + // should be 16 byte aligned and the data size should be = multiple of 16 bytes. + // + VirtualMemoryTable[++Index].PhysicalBase =3D IFC_REGION1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D IFC_REGION1_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D IFC_REGION1_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // QMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D QMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D QMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D QMAN_SWP_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // BMAN SWP + VirtualMemoryTable[++Index].PhysicalBase =3D BMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D BMAN_SWP_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D BMAN_SWP_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // IFC region 2 + VirtualMemoryTable[++Index].PhysicalBase =3D IFC_REGION2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D IFC_REGION2_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D IFC_REGION2_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM2 + VirtualMemoryTable[++Index].PhysicalBase =3D DRAM2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D DRAM2_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D DRAM2_SIZE; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // PCIe1 + VirtualMemoryTable[++Index].PhysicalBase =3D PCI_EXP1_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D PCI_EXP1_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D PCI_EXP1_BASE_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe2 + VirtualMemoryTable[++Index].PhysicalBase =3D PCI_EXP2_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D PCI_EXP2_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D PCI_EXP2_BASE_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // PCIe3 + VirtualMemoryTable[++Index].PhysicalBase =3D PCI_EXP3_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D PCI_EXP3_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D PCI_EXP3_BASE_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_D= EVICE; + + // DRAM3 + VirtualMemoryTable[++Index].PhysicalBase =3D DRAM3_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D DRAM3_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D DRAM3_SIZE; + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; + + // QSPI region + VirtualMemoryTable[++Index].PhysicalBase =3D QSPI_REGION_BASE_ADDR; + VirtualMemoryTable[Index].VirtualBase =3D QSPI_REGION_BASE_ADDR; + VirtualMemoryTable[Index].Length =3D QSPI_REGION_SIZE; + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUTE_U= NCACHED_UNBUFFERED; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase =3D 0; + VirtualMemoryTable[Index].VirtualBase =3D 0; + VirtualMemoryTable[Index].Length =3D 0; + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUTES= )0; + + ASSERT((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap =3D VirtualMemoryTable; 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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR03MB2693 Subject: [edk2] [PATCH 4/4] Compilation:Add the fdf,dsc and dec files X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds firmware device,description and declaration files to enable compilation for NXP LS1046ARDB board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Vabhav --- Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc | 1 + Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec | 30 +++ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc | 75 +++++++ Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf | 297 +++++++++++++++++++++++= ++++ Platform/NXP/NxpQoriqLs.dec | 1 + Platform/NXP/Readme.md | 2 +- Silicon/NXP/LS1046A/LS1046A.dec | 22 ++ Silicon/NXP/LS1046A/LS1046A.dsc | 79 +++++++ 8 files changed, 506 insertions(+), 1 deletion(-) create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc create mode 100644 Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf create mode 100644 Silicon/NXP/LS1046A/LS1046A.dec create mode 100644 Silicon/NXP/LS1046A/LS1046A.dsc diff --git a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc b/Platform/NXP/LS= 1043aRdbPkg/LS1043aRdbPkg.dsc index 19d4d30..3aa3407 100644 --- a/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc +++ b/Platform/NXP/LS1043aRdbPkg/LS1043aRdbPkg.dsc @@ -47,6 +47,7 @@ # gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|FALSE gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x1 + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|TRUE =20 # # Big Endian IPs diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec b/Platform/NXP/LS= 1046aRdbPkg/LS1046aRdbPkg.dec new file mode 100644 index 0000000..bdede59 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dec @@ -0,0 +1,30 @@ +#/** LS1046a board package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made ava= ilable under +# the terms and conditions of the BSD License which accompanies this di= stribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. +# +#**/ + +[Defines] + PACKAGE_NAME =3D LS1046aRdbPkg + PACKAGE_GUID =3D 6eba6648-d853-4eb3-9761-528b82d5ab04 + +##########################################################################= ###### +# +# Include Section - list of Include Paths that are provided by this packag= e. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_D= RIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +##########################################################################= ###### +[Includes.common] + Include # Root include for the package + diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc b/Platform/NXP/LS= 1046aRdbPkg/LS1046aRdbPkg.dsc new file mode 100644 index 0000000..ec9037b --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.dsc @@ -0,0 +1,75 @@ +#/** LS1046ARDB Board package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the= BSD License +# which accompanies this distribution. The full text of the license may= be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. +# +#**/ + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + PLATFORM_NAME =3D LS1046aRdbPkg + PLATFORM_GUID =3D 60169ec4-d2b4-44f8-825e-f8684fd42e4f + OUTPUT_DIRECTORY =3D Build/LS1046aRdbPkg + FLASH_DEFINITION =3D edk2-platforms/Platform/NXP/LS1046aRd= bPkg/LS1046aRdbPkg.fdf + +!include ../NxpQoriqLs.dsc +!include ../../../Silicon/NXP/LS1046A/LS1046A.dsc + +[LibraryClasses.common] + ArmPlatformLib|edk2-platforms/Platform/NXP/LS1046aRdbPkg/Library/Platfor= mLib/ArmPlatformLib.inf + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSy= stemLib.inf + SerialPortLib|edk2-platforms/Platform/NXP/Library/DUartPortLib/DUartPort= Lib.inf + BeIoLib|edk2-platforms/Platform/NXP/Library/BeIoLib/BeIoLib.inf + SocLib|edk2-platforms/Silicon/NXP/Chassis/LS1046aSocLib.inf + RealTimeClockLib|edk2-platforms/Silicon/NXP/Library/Pcf2129RtcLib/Pcf212= 9RtcLib.inf + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"LS1046a RDB board" + + # + # Board Specific Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdSerdes2Enabled|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdPlatformFreqDiv|0x2 + gNxpQoriqLsTokenSpaceGuid.PcdMuxToUsb3|FALSE + + # + # Big Endian IPs + # + gNxpQoriqLsTokenSpaceGuid.PcdGurBigEndian|TRUE + gNxpQoriqLsTokenSpaceGuid.PcdWdogBigEndian|TRUE + + # + # I2C controller Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|3 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|100000 + + # + # RTC Pcds + # + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform +# +##########################################################################= ###### +[Components.common] + edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf + edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf diff --git a/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf b/Platform/NXP/LS= 1046aRdbPkg/LS1046aRdbPkg.fdf new file mode 100644 index 0000000..169cef0 --- /dev/null +++ b/Platform/NXP/LS1046aRdbPkg/LS1046aRdbPkg.fdf @@ -0,0 +1,297 @@ +# LS1046aRdbPkg.fdf +# +# FLASH layout file for LS1046a board. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### + +[FD.LS1046aRdb_EFI] +BaseAddress =3D 0x82000000|gArmTokenSpaceGuid.PcdFdBaseAddress #The bas= e address of the FLASH Device. +Size =3D 0x000ED850|gArmTokenSpaceGuid.PcdFdSize #The siz= e in bytes of the FLASH Device +ErasePolarity =3D 1 +BlockSize =3D 0x1 +NumBlocks =3D 0xED850 + +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +##########################################################################= ###### +0x00000000|0x000ED850 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV =3D FVMAIN_COMPACT + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvMain] +FvNameGuid =3D 1037c42b-8452-4c41-aac7-41e6c31468da +BlockSize =3D 0x1 +NumBlocks =3D 0 # This FV gets compressed so make it just= big enough +FvAlignment =3D 8 # FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF edk2-platforms/Platform/NXP/Drivers/WatchDog/WatchDogDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.i= nf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # + # Network modules + # + INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf + INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf + INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf + INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf + INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf + INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf + INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf + INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf + INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf + INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf +!if $(NETWORK_IP6_ENABLE) =3D=3D TRUE + INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf + INF NetworkPkg/TcpDxe/TcpDxe.inf + INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf + INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf + INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf + INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf +!else + INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf +!endif + + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.= inf + + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/FatPei/FatPei.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + + INF edk2-platforms/Platform/NXP/Drivers/I2cDxe/I2cDxe.inf + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 8 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf + + FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FVMAIN + } + } + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + + +##########################################################################= ## +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section = # +##########################################################################= ## +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER =3D $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_= NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING=3D"$(MODULE_NAME)" Optional +# VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_N= UMBER) +# } +# } +# } +# +##########################################################################= ## + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align =3D 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM =3D $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED =3D TR= UE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NA= ME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + UI STRING =3D"$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } diff --git a/Platform/NXP/NxpQoriqLs.dec b/Platform/NXP/NxpQoriqLs.dec index 4af35a1..f26595c 100644 --- a/Platform/NXP/NxpQoriqLs.dec +++ b/Platform/NXP/NxpQoriqLs.dec @@ -30,6 +30,7 @@ gNxpQoriqLsTokenSpaceGuid.PcdI2cBus|0|UINT32|0x00000001 gNxpQoriqLsTokenSpaceGuid.PcdI2cSpeed|0|UINT32|0x00000002 gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|0|UINT32|0x00000003 + gNxpQoriqLsTokenSpaceGuid.PcdI2cSlaveAddress|0|UINT32|0x00000004 =20 # # Pcds for base address and size diff --git a/Platform/NXP/Readme.md b/Platform/NXP/Readme.md index a11b90c..f1f273f 100644 --- a/Platform/NXP/Readme.md +++ b/Platform/NXP/Readme.md @@ -12,4 +12,4 @@ user need to run only build command. board-name : LS1043 / LS1046 / LS2088 build-candidate : DEBUG / RELEASE =20 -Currently, support for LS1043 is provided. +Currently, support for LS1043 and LS1046 is provided. diff --git a/Silicon/NXP/LS1046A/LS1046A.dec b/Silicon/NXP/LS1046A/LS1046A.= dec new file mode 100644 index 0000000..5f41319 --- /dev/null +++ b/Silicon/NXP/LS1046A/LS1046A.dec @@ -0,0 +1,22 @@ +# LS1046A.dec +# +# Copyright 2017 NXP +# +# This program and the accompanying materials are licensed and made ava= ilable under +# the terms and conditions of the BSD License which accompanies this di= stribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + +[Guids.common] + gNxpLs1046ATokenSpaceGuid =3D {0x1edb40ad, 0x1178, 0x407f, {0x8f, 0= x1a, 0x64, 0x20, 0x8a, 0x16, 0x33, 0xd1}} + +[Includes] + Include diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc b/Silicon/NXP/LS1046A/LS1046A.= dsc new file mode 100644 index 0000000..65fc192 --- /dev/null +++ b/Silicon/NXP/LS1046A/LS1046A.dsc @@ -0,0 +1,79 @@ +# LS1046A board package. +# +# Copyright 2017 NXP +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +# + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### + +[PcdsDynamicDefault.common] + + gArmTokenSpaceGuid.PcdGicDistributorBase|0x1410000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x1420000 + +[PcdsFixedAtBuild.common] + + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"LS1046a" + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x21c0500 + + # + # LS1046a board Specific PCDs + # XX (DRAM - Region 1 2GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000 + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x02000000 + + # + # CCSR Address Space and other attached Memories + # + gNxpQoriqLsTokenSpaceGuid.PcdCcsrBaseAddr|0x01000000 + gNxpQoriqLsTokenSpaceGuid.PcdCcsrSize|0x0F000000 + gNxpQoriqLsTokenSpaceGuid.PcdClkBaseAddr|0x01EE1000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1BaseAddr|0x60000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion1Size|0x20000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2BaseAddr|0x0620000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcRegion2Size|0x00E0000000 + gNxpQoriqLsTokenSpaceGuid.PcdIfcNandReservedSize|0x2EA + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpBaseAddr|0x0500000000 + gNxpQoriqLsTokenSpaceGuid.PcdQmanSwpSize|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpBaseAddr|0x0508000000 + gNxpQoriqLsTokenSpaceGuid.PcdBmanSwpSize|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr|0x4000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr|0x4800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr|0x5000000000 + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseSize|0x800000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram1BaseAddr|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram1Size|0x0080000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram2BaseAddr|0x0880000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram2Size|0x0780000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram3BaseAddr|0x8800000000 + gNxpQoriqLsTokenSpaceGuid.PcdDram3Size|0x7800000000 + gNxpQoriqLsTokenSpaceGuid.PcdScfgBaseAddr|0x1570000 + gNxpQoriqLsTokenSpaceGuid.PcdGutsBaseAddr|0x01EE0000 + gNxpQoriqLsTokenSpaceGuid.PcdWdog1BaseAddr|0x02AD0000 + gNxpQoriqLsTokenSpaceGuid.PcdWdog2BaseAddr|0x02AE0000 + gNxpQoriqLsTokenSpaceGuid.PcdWdog3BaseAddr|0x02A70000 + gNxpQoriqLsTokenSpaceGuid.PcdWdog4BaseAddr|0x02A80000 + gNxpQoriqLsTokenSpaceGuid.PcdWdog5BaseAddr|0x02A90000 + gNxpQoriqLsTokenSpaceGuid.PcdSdxcBaseAddr|0x01560000 + gNxpQoriqLsTokenSpaceGuid.PcdI2c0BaseAddr|0x02180000 + gNxpQoriqLsTokenSpaceGuid.PcdI2c1BaseAddr|0x02190000 + gNxpQoriqLsTokenSpaceGuid.PcdI2c2BaseAddr|0x021A0000 + gNxpQoriqLsTokenSpaceGuid.PcdI2c3BaseAddr|0x021B0000 + gNxpQoriqLsTokenSpaceGuid.PcdNumI2cController|4 + +## --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel