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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id g29sm1120441lfh.3.2017.11.03.10.57.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 10:57:26 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B56zvCwqQmW3c7thsNGineHa5ImOvhdhQOyO+Rh20Y0=; b=qgMTz1uFJZ6S6msuqtrBLKEZMkYIKhvNY2SgUrBmvmOW3QsmwtJKV2YVmiXkdlVUxK SAeLUD6/FFjLFc6/M5Nkj2plXt2P481siEqNcUnp5nAmBkTj+jpN+tHhJi9uh5Cu0CDG N1D/AyZTxyLa0WJYErM98N6GxDEyZgh75WvbEICOWO5xwmQXbvM/s0eyQtU1l29wKZxF Rk4ejReUfdLlNkkvjyg1YeJJFCNlLC/pA1pG8fO6AJ8bIzEnYhnSGcgTPxHO8RmApbZC rbDACZI8oxhNRy0d6OFsb6W3MscNQBBWl/C0dPBUSmovN0yuSnT6yjRMX60kSTxJeqhS ltUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B56zvCwqQmW3c7thsNGineHa5ImOvhdhQOyO+Rh20Y0=; b=jQTC+zR/medqI3hjEZhDWtL4Cet0TRP89v2iL6pVUAiYenUeXX78QofwJT1O+zWx08 h9bpUNklJYNRjZySQROZdBT7UoI+DK6/symCkKLicwhy8qJETm/Z96oza0z0L+BHS/WL nWokHCWcsUUON+VfWgZy3pa2J12a0+InuAGiOBpSBbBiGDXfTeeQA7BAwdiYMGGwy4Yn FtR6jKzbDUfZlegQsjAor26uizmGKnknGBelM/+NtAst+R9EAzVtQ381G1M9xLiHVFvC tJ4o/ZnOM8XcPDs+s4XPY2TWRCwv30uOR9brjZtZ8uCfpoxIgSVLHXDPy4jTlwFb+zWt W2gQ== X-Gm-Message-State: AMCzsaXmZ7yhTaVHz13uZb/N9Hexqc5gP9TGMFovYcOQWYXAUPltsHMn Qhd+OHAQblCEZbrVeg1AWaeFZpdTFG8= X-Google-Smtp-Source: ABhQp+SCsb3DReHMtzwVdxUnSgUU+o7kAs2Cj5N1QKsqMkSdVdiQAiPnAz2gIBbNP8sK+yWzRc5XAg== X-Received: by 10.46.56.14 with SMTP id f14mr3659107lja.46.1509731846863; Fri, 03 Nov 2017 10:57:26 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 3 Nov 2017 18:57:10 +0100 Message-Id: <1509731835-5664-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509731835-5664-1-git-send-email-mw@semihalf.com> References: <1509731835-5664-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 1/6] Marvell/Drivers: MvSpiFlash: Improve ReadId X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Fix the ReadId routine by using master's ReadWrite callback instead of the raw Transfer - no longer swapping and byte shifting is needed. Simplify code by using local array instead of dynamic allocation. Moreover store the FlashId in an UINT8 array PCD instead of the concatenated UINT32 format - this way less overhead in the driver is needed for comparing the buffers. The new handling allowed for cleaning Fupdate and Sf shell commands FlashProbe routines. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 24 ++++-------- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 39 +++++++-------= ----- Platform/Marvell/Armada/Armada70x0.dsc | 2 +- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 41 ++++++++++++--= ------ Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 2 + Platform/Marvell/Include/Protocol/SpiFlash.h | 2 + Platform/Marvell/Marvell.dec | 2 +- 7 files changed, 51 insertions(+), 61 deletions(-) diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c b/Platf= orm/Marvell/Applications/FirmwareUpdate/FUpdate.c index 664411a..8a2ad3f 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c @@ -94,28 +94,18 @@ SpiFlashProbe ( ) { EFI_STATUS Status; - UINT32 IdBuffer, Id, RefId; + UINT32 FlashIdLen; + UINT8 *FlashId; =20 - Id =3D PcdGet32 (PcdSpiFlashId); - - IdBuffer =3D CMD_READ_ID & 0xff; + FlashId =3D (UINT8 *)PcdGetPtr (PcdSpiFlashId); + FlashIdLen =3D PcdGetSize (PcdSpiFlashId); =20 // Read SPI flash ID - SpiFlashProtocol->ReadId (Slave, sizeof (UINT32), (UINT8 *)&IdBuffer); - - // Swap and extract 3 bytes of the ID - RefId =3D SwapBytes32 (IdBuffer) >> 8; - - if (RefId =3D=3D 0) { - Print (L"%s: No SPI flash detected"); - return EFI_DEVICE_ERROR; - } else if (RefId !=3D Id) { - Print (L"%s: Unsupported SPI flash detected with ID=3D%2x\n", CMD_NAME= _STRING, RefId); - return EFI_DEVICE_ERROR; + Status =3D SpiFlashProtocol->ReadId (Slave, FlashIdLen, FlashId); + if (EFI_ERROR (Status)) { + return SHELL_ABORTED; } =20 - Print (L"%s: Detected supported SPI flash with ID=3D%3x\n", CMD_NAME_STR= ING, RefId); - Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, Slave); if (EFI_ERROR(Status)) { Print (L"%s: Cannot initialize flash device\n", CMD_NAME_STRING); diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index 9321f6b..7c81bfc 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -166,37 +166,26 @@ FlashProbe ( ) { EFI_STATUS Status; - UINT8 IdBuffer[4]; - UINT32 Id, RefId; + UINT32 FlashIdLen; + UINT8 *FlashId; =20 - Id =3D PcdGet32 (PcdSpiFlashId); + FlashId =3D (UINT8 *)PcdGetPtr (PcdSpiFlashId); + FlashIdLen =3D PcdGetSize (PcdSpiFlashId); =20 - IdBuffer[0] =3D CMD_READ_ID; - - SpiFlashProtocol->ReadId ( - Slave, - 4, - IdBuffer - ); - - RefId =3D (IdBuffer[0] << 16) + (IdBuffer[1] << 8) + IdBuffer[2]; + Status =3D SpiFlashProtocol->ReadId (Slave, FlashIdLen, FlashId); + if (EFI_ERROR (Status)) { + return SHELL_ABORTED; + } =20 - if (RefId =3D=3D Id) { - Print (L"sf: Detected supported SPI flash with ID=3D%3x\n", RefId); - Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, Slave); - if (EFI_ERROR(Status)) { - Print (L"sf: Cannot initialize flash device\n"); - return SHELL_ABORTED; - } - InitFlag =3D 0; - return EFI_SUCCESS; - } else if (RefId !=3D 0) { - Print (L"sf: Unsupported SPI flash detected with ID=3D%2x\n", RefId); + Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, Slave); + if (EFI_ERROR (Status)) { + Print (L"sf: Cannot initialize flash device\n"); return SHELL_ABORTED; } =20 - Print (L"sf: No SPI flash detected"); - return SHELL_ABORTED; + InitFlag =3D 0; + + return SHELL_SUCCESS; } =20 SHELL_STATUS diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 0396e8e..4d5f55f 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -94,7 +94,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|3 gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256 - gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18 + gMarvellTokenSpaceGuid.PcdSpiFlashId|{ 0x20, 0xBA, 0x18 } gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index 6f7d9c7..ab3ed6a 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -409,28 +409,35 @@ MvSpiFlashReadId ( ) { EFI_STATUS Status; - UINT8 *DataOut; + UINT8 Id[NOR_FLASH_MAX_ID_LEN]; + UINT8 Cmd; + + Cmd =3D CMD_READ_ID; + Status =3D SpiMasterProtocol->ReadWrite (SpiMasterProtocol, + SpiDev, + &Cmd, + SPI_CMD_LEN, + NULL, + Id, + NOR_FLASH_MAX_ID_LEN); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ReadId: Spi transfer error\n")); + return Status; + } =20 - DataOut =3D (UINT8 *) AllocateZeroPool (DataByteCount); - if (DataOut =3D=3D NULL) { - DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); - return EFI_OUT_OF_RESOURCES; + if (CompareMem (Id, Buffer, DataByteCount) !=3D 0) { + Status =3D EFI_NOT_FOUND; } - Status =3D SpiMasterProtocol->Transfer (SpiMasterProtocol, SpiDev, - DataByteCount, Buffer, DataOut, SPI_TRANSFER_BEGIN | SPI_TRANSFER_END); - if (EFI_ERROR(Status)) { - FreePool (DataOut); - DEBUG((DEBUG_ERROR, "SpiFlash: Spi transfer error\n")); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Unrecognized JEDEC Id bytes: 0x%02x%02x%02x\n", + __FUNCTION__, + Id[0], + Id[1], + Id[2])); return Status; } =20 - // Bytes 1,2 and 3 contain SPI flash ID - Buffer[0] =3D DataOut[1]; - Buffer[1] =3D DataOut[2]; - Buffer[2] =3D DataOut[3]; - - FreePool (DataOut); - return EFI_SUCCESS; } =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.h index f90abb7..2583484 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h @@ -62,6 +62,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 +#define SPI_CMD_LEN 1 + #define STATUS_REG_POLL_WIP (1 << 0) #define STATUS_REG_POLL_PEC (1 << 7) =20 diff --git a/Platform/Marvell/Include/Protocol/SpiFlash.h b/Platform/Marvel= l/Include/Protocol/SpiFlash.h index 743bb87..f65a12d 100644 --- a/Platform/Marvell/Include/Protocol/SpiFlash.h +++ b/Platform/Marvell/Include/Protocol/SpiFlash.h @@ -47,6 +47,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 +#define NOR_FLASH_MAX_ID_LEN 6 + extern EFI_GUID gMarvellSpiFlashProtocolGuid; =20 typedef struct _MARVELL_SPI_FLASH_PROTOCOL MARVELL_SPI_FLASH_PROTOCOL; diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index cd800c8..679a9d0 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -133,7 +133,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize|65536|UINT64|0x3000059 - gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 + gMarvellTokenSpaceGuid.PcdSpiFlashId|{ 0x0 }|VOID*|0x3000056 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 22:57:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509731854536283.67653540874926; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id g29sm1120441lfh.3.2017.11.03.10.57.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 10:57:27 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hTW7LZUOBB16HeeLGA85/9EB9DuJGp0kJkiaD5Px/jM=; b=MxtNRKnrnzQnlV2YUlpH2YFUJTWWqrjgEBIMLppcTarDvu40mZI4Zr8AGuSIRWRyZZ nGgw00Pars1IHqQ/JATkvFlskoBaUPQ0BkbXxCtJiq5mvS/Ty/Fp2m9Co9fjhBdAJq3U y7bDLQM31QYBsVrnuGpWCPZY6YCxZm1tHUryD9/gNHaJuv0RY7QQ4+3mNH5QhB5094U7 PSAoYmDr+Q3VO0+Ovtfrk17sV+mM34I7OsQDUt0m68FP2iZvDjuMNBNHnwQEOTdm5YVn qMq4EGK6WIYKn0urRimkofUzpMARkbiB/rg9M+Brk9YWwg9WYXu1MWxHLQ4Gem52U4f/ F2fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hTW7LZUOBB16HeeLGA85/9EB9DuJGp0kJkiaD5Px/jM=; b=LbbyAo22m79ztoebhG1F6WIe503/g1+sKhS0g4vhLs8CRsD37+nVHOSWT7nz6QtTVJ 5tmuA1r84hMdRYeZ1bXkc1Nk9HNuhX/Rf/tJCUYT1ry5PyblNYfeGa2DCE5UxAZizEi1 ktyQXg7TX/hrXfLiSvBYAMGKRfMacca0aloxxuKB/b3BSy0F0V/dVZqqelC/KKYE0gpK 8JFM3E/TT0oynZgAnE55ca6K3kolVXy5RjX+w53r2ZS3TkwGjpR0ypedTqgtRjECkKj4 ToMsqbZ1tA62p0L64ITrl7clBFEeVHspFxJ+dYt7oOfkCe5jMukfyOno6tZa8Ac4ci9n OiPA== X-Gm-Message-State: AMCzsaXTU9FGFBwiT4PPSfkicTddmc5JyReIJ6tUD6Zj8X/074TwFbSB C1HigKRim9RsBDiCwaQ79MTo/VfMLkM= X-Google-Smtp-Source: ABhQp+RovzO2oKUP/Ykaeabv/VgwJomGktOt36cb9OVpTHRiS6RRD/XGJephHW9g8zczaSdyQ6dIrg== X-Received: by 10.46.83.67 with SMTP id t3mr3275649ljd.135.1509731848350; Fri, 03 Nov 2017 10:57:28 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 3 Nov 2017 18:57:11 +0100 Message-Id: <1509731835-5664-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509731835-5664-1-git-send-email-mw@semihalf.com> References: <1509731835-5664-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 2/6] Marvell/Drivers: MvSpiFlash: Enable dynamic SPI Flash detection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hitherto mechanism of fixing SPI flash model in the PCDs, occured to be very inefficient and problematic. Enable dynamic detection by reworking MvSpiFlashReadId() command, which now uses newly added NorFlashInfoLib, that helps to obtain description of the JEDEC compliant devices. This patch updates the MvSpiFlashProtocol ReadId() protocol callback on both producer's (MvFlashDxe) and consumers' sides (FirmwareUpdate and SpiTool applications). Because all information about detected SPI NOR flash is now stored in the obtained NorFlashInfo structure fields, use them instead of the PCDs. Enable compilation of the NorFlashInfoLib and update PortingGuide documentation accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 7 +- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf | 4 +- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 7 +- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf | 2 +- Platform/Marvell/Armada/Armada.dsc.inc | 1 + Platform/Marvell/Armada/Armada70x0.dsc | 5 -- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 76 +++++++++---= -------- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf | 9 +-- Platform/Marvell/Drivers/Spi/MvSpiDxe.inf | 2 + Platform/Marvell/Include/Protocol/Spi.h | 4 ++ Platform/Marvell/Include/Protocol/SpiFlash.h | 5 +- Platform/Marvell/Marvell.dec | 6 -- Silicon/Marvell/Documentation/PortingGuide.txt | 18 ----- 13 files changed, 48 insertions(+), 98 deletions(-) diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c b/Platf= orm/Marvell/Applications/FirmwareUpdate/FUpdate.c index 8a2ad3f..750e52a 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c @@ -94,14 +94,9 @@ SpiFlashProbe ( ) { EFI_STATUS Status; - UINT32 FlashIdLen; - UINT8 *FlashId; - - FlashId =3D (UINT8 *)PcdGetPtr (PcdSpiFlashId); - FlashIdLen =3D PcdGetSize (PcdSpiFlashId); =20 // Read SPI flash ID - Status =3D SpiFlashProtocol->ReadId (Slave, FlashIdLen, FlashId); + Status =3D SpiFlashProtocol->ReadId (Slave, FALSE); if (EFI_ERROR (Status)) { return SHELL_ABORTED; } diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf b/Pla= tform/Marvell/Applications/FirmwareUpdate/FUpdate.inf index 92c3333..53ea491 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf @@ -44,6 +44,7 @@ FUpdate.uni =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec Platform/Marvell/Marvell.dec @@ -64,9 +65,6 @@ UefiLib UefiRuntimeServicesTableLib =20 -[Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashId - [Protocols] gMarvellSpiFlashProtocolGuid gMarvellSpiMasterProtocolGuid diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index 7c81bfc..68a6cf7 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -166,13 +166,8 @@ FlashProbe ( ) { EFI_STATUS Status; - UINT32 FlashIdLen; - UINT8 *FlashId; =20 - FlashId =3D (UINT8 *)PcdGetPtr (PcdSpiFlashId); - FlashIdLen =3D PcdGetSize (PcdSpiFlashId); - - Status =3D SpiFlashProtocol->ReadId (Slave, FlashIdLen, FlashId); + Status =3D SpiFlashProtocol->ReadId (Slave, FALSE); if (EFI_ERROR (Status)) { return SHELL_ABORTED; } diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf b/Platfo= rm/Marvell/Applications/SpiTool/SpiFlashCmd.inf index 887b9a5..a52906b 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf @@ -44,6 +44,7 @@ SpiFlashCmd.uni =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec ShellPkg/ShellPkg.dec MdeModulePkg/MdeModulePkg.dec @@ -66,7 +67,6 @@ =20 [Pcd] gMarvellTokenSpaceGuid.PcdSpiFlashCs - gMarvellTokenSpaceGuid.PcdSpiFlashId gMarvellTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index b9fc384..2cd96e6 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -33,6 +33,7 @@ ArmPlatformLib|Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0L= ib.inf ComPhyLib|Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf MppLib|Platform/Marvell/Library/MppLib/MppLib.inf + NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf UtmiPhyLib|Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf =20 DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 4d5f55f..8e4cdb2 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -90,11 +90,6 @@ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0x70 - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|3 - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536 - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256 - gMarvellTokenSpaceGuid.PcdSpiFlashId|{ 0x20, 0xBA, 0x18 } gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index ab3ed6a..4a97ba9 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -107,10 +107,10 @@ MvSpiFlashWriteCommon ( UINT8 PollBit =3D STATUS_REG_POLL_WIP; UINT8 CheckStatus =3D 0x0; =20 - CmdStatus =3D (UINT8)PcdGet32 (PcdSpiFlashPollCmd); - if (CmdStatus =3D=3D CMD_FLAG_STATUS) { + if (Slave->Info->Flags & NOR_FLASH_WRITE_FSR) { + CmdStatus =3D CMD_FLAG_STATUS; PollBit =3D STATUS_REG_POLL_PEC; - CheckStatus =3D PollBit; + CheckStatus =3D STATUS_REG_POLL_PEC; } =20 // Send command @@ -177,12 +177,20 @@ MvSpiFlashErase ( ) { EFI_STATUS Status; - UINT32 AddrSize, EraseAddr; + UINT32 EraseAddr; UINTN EraseSize; UINT8 Cmd[5]; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); - EraseSize =3D PcdGet64 (PcdSpiFlashEraseSize); + if (Slave->Info->Flags & NOR_FLASH_ERASE_4K) { + Cmd[0] =3D CMD_ERASE_4K; + EraseSize =3D SIZE_4KB; + } else if (Slave->Info->Flags & NOR_FLASH_ERASE_32K) { + Cmd[0] =3D CMD_ERASE_32K; + EraseSize =3D SIZE_32KB; + } else { + Cmd[0] =3D CMD_ERASE_64K; + EraseSize =3D Slave->Info->SectorSize; + } =20 // Check input parameters if (Offset % EraseSize || Length % EraseSize) { @@ -191,30 +199,15 @@ MvSpiFlashErase ( return EFI_DEVICE_ERROR; } =20 - switch (EraseSize) { - case SIZE_4KB: - Cmd[0] =3D CMD_ERASE_4K; - break; - case SIZE_32KB: - Cmd[0] =3D CMD_ERASE_32K; - break; - case SIZE_64KB: - Cmd[0] =3D CMD_ERASE_64K; - break; - default: - DEBUG ((DEBUG_ERROR, "MvSpiFlash: Invalid EraseSize parameter\n")); - return EFI_INVALID_PARAMETER; - } - while (Length) { EraseAddr =3D Offset; =20 SpiFlashBank (Slave, EraseAddr); =20 - SpiFlashFormatAddress (EraseAddr, AddrSize, Cmd); + SpiFlashFormatAddress (EraseAddr, Slave->AddrSize, Cmd); =20 // Programm proper erase address - Status =3D MvSpiFlashWriteCommon (Slave, Cmd, AddrSize + 1, NULL, 0); + Status =3D MvSpiFlashWriteCommon (Slave, Cmd, Slave->AddrSize + 1, NUL= L, 0); if (EFI_ERROR (Status)) { DEBUG((DEBUG_ERROR, "SpiFlash: Error while programming target addr= ess\n")); return Status; @@ -236,11 +229,9 @@ MvSpiFlashRead ( { EFI_STATUS Status =3D EFI_SUCCESS; UINT8 Cmd[6]; - UINT32 AddrSize, ReadAddr, ReadLength, RemainLength; + UINT32 ReadAddr, ReadLength, RemainLength; UINTN BankSel =3D 0; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); - Cmd[0] =3D CMD_READ_ARRAY_FAST; =20 // Sign end of address with 0 byte @@ -257,9 +248,9 @@ MvSpiFlashRead ( } else { ReadLength =3D RemainLength; } - SpiFlashFormatAddress (ReadAddr, AddrSize, Cmd); + SpiFlashFormatAddress (ReadAddr, Slave->AddrSize, Cmd); // Program proper read address and read data - Status =3D MvSpiFlashReadCmd (Slave, Cmd, AddrSize + 2, Buf, Length); + Status =3D MvSpiFlashReadCmd (Slave, Cmd, Slave->AddrSize + 2, Buf, Le= ngth); =20 Offset +=3D ReadLength; Length -=3D ReadLength; @@ -280,10 +271,9 @@ MvSpiFlashWrite ( EFI_STATUS Status; UINTN ByteAddr, ChunkLength, ActualIndex, PageSize; UINT32 WriteAddr; - UINT8 Cmd[5], AddrSize; + UINT8 Cmd[5]; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); - PageSize =3D PcdGet32 (PcdSpiFlashPageSize); + PageSize =3D Slave->Info->PageSize; =20 Cmd[0] =3D CMD_PAGE_PROGRAM; =20 @@ -296,10 +286,10 @@ MvSpiFlashWrite ( =20 ChunkLength =3D MIN(Length - ActualIndex, (UINT64) (PageSize - ByteAdd= r)); =20 - SpiFlashFormatAddress (WriteAddr, AddrSize, Cmd); + SpiFlashFormatAddress (WriteAddr, Slave->AddrSize, Cmd); =20 // Program proper write address and write data - Status =3D MvSpiFlashWriteCommon (Slave, Cmd, AddrSize + 1, Buf + Actu= alIndex, + Status =3D MvSpiFlashWriteCommon (Slave, Cmd, Slave->AddrSize + 1, Buf= + ActualIndex, ChunkLength); if (EFI_ERROR (Status)) { DEBUG((DEBUG_ERROR, "SpiFlash: Error while programming write address= \n")); @@ -370,7 +360,7 @@ MvSpiFlashUpdate ( UINT64 SectorSize, ToUpdate, Scale =3D 1; UINT8 *TmpBuf, *End; =20 - SectorSize =3D PcdGet64 (PcdSpiFlashSectorSize); + SectorSize =3D Slave->Info->SectorSize; =20 End =3D Buf + ByteCount; =20 @@ -404,8 +394,7 @@ EFI_STATUS EFIAPI MvSpiFlashReadId ( IN SPI_DEVICE *SpiDev, - IN UINT32 DataByteCount, - IN OUT UINT8 *Buffer + IN BOOLEAN UseInRuntime ) { EFI_STATUS Status; @@ -425,9 +414,7 @@ MvSpiFlashReadId ( return Status; } =20 - if (CompareMem (Id, Buffer, DataByteCount) !=3D 0) { - Status =3D EFI_NOT_FOUND; - } + Status =3D NorFlashGetInfo (Id, &SpiDev->Info, UseInRuntime); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "%a: Unrecognized JEDEC Id bytes: 0x%02x%02x%02x\n", @@ -438,6 +425,8 @@ MvSpiFlashReadId ( return Status; } =20 + NorFlashPrintInfo (SpiDev->Info); + return EFI_SUCCESS; } =20 @@ -450,11 +439,14 @@ MvSpiFlashInit ( { EFI_STATUS Status; UINT8 Cmd, StatusRegister; - UINT32 AddrSize; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); + if (Slave->Info->Flags & NOR_FLASH_4B_ADDR) { + Slave->AddrSize =3D 4; + } else { + Slave->AddrSize =3D 3; + } =20 - if (AddrSize =3D=3D 4) { + if (Slave->AddrSize =3D=3D 4) { // Set 4 byte address mode Status =3D MvSpiFlashWriteEnableCmd (Slave); if (EFI_ERROR (Status)) { diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf b/Platform= /Marvell/Drivers/Spi/Devices/MvSpiFlash.inf index 4519b02..6587f69 100644 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf @@ -42,10 +42,12 @@ MvSpiFlash.h =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec Platform/Marvell/Marvell.dec =20 [LibraryClasses] + NorFlashInfoLib UefiBootServicesTableLib UefiDriverEntryPoint TimerLib @@ -53,13 +55,6 @@ DebugLib MemoryAllocationLib =20 -[FixedPcd] - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize - [Protocols] gMarvellSpiMasterProtocolGuid gMarvellSpiFlashProtocolGuid diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf b/Platform/Marvell/D= rivers/Spi/MvSpiDxe.inf index d38d331..08c6c04 100644 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.inf @@ -42,10 +42,12 @@ MvSpiDxe.h =20 [Packages] + EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec Platform/Marvell/Marvell.dec =20 [LibraryClasses] + NorFlashInfoLib UefiBootServicesTableLib UefiDriverEntryPoint TimerLib diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index ae78a31..6f26a36 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -34,6 +34,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MARVELL_SPI_MASTER_PROTOCOL_H__ #define __MARVELL_SPI_MASTER_PROTOCOL_H__ =20 +#include + extern EFI_GUID gMarvellSpiMasterProtocolGuid; =20 typedef struct _MARVELL_SPI_MASTER_PROTOCOL MARVELL_SPI_MASTER_PROTOCOL; @@ -49,6 +51,8 @@ typedef struct { INTN Cs; INTN MaxFreq; SPI_MODE Mode; + UINT32 AddrSize; + NOR_FLASH_INFO *Info; } SPI_DEVICE; =20 typedef diff --git a/Platform/Marvell/Include/Protocol/SpiFlash.h b/Platform/Marvel= l/Include/Protocol/SpiFlash.h index f65a12d..4a3053e 100644 --- a/Platform/Marvell/Include/Protocol/SpiFlash.h +++ b/Platform/Marvell/Include/Protocol/SpiFlash.h @@ -47,8 +47,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 -#define NOR_FLASH_MAX_ID_LEN 6 - extern EFI_GUID gMarvellSpiFlashProtocolGuid; =20 typedef struct _MARVELL_SPI_FLASH_PROTOCOL MARVELL_SPI_FLASH_PROTOCOL; @@ -64,8 +62,7 @@ typedef EFI_STATUS (EFIAPI *MV_SPI_FLASH_READ_ID) ( IN SPI_DEVICE *SpiDev, - IN UINT32 DataByteCount, - IN OUT UINT8 *Buffer + IN BOOLEAN UseInRuntime ); =20 typedef diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 679a9d0..8255895 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -128,12 +128,6 @@ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0|UINT32|0x3000052 - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|0|UINT32|0x3000053 - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize|65536|UINT64|0x3000059 - gMarvellTokenSpaceGuid.PcdSpiFlashId|{ 0x0 }|VOID*|0x3000056 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 =20 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index cbe3bed..d5deed5 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -312,24 +312,6 @@ SpiFlash configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Folowing PCDs for spi flash driver configuration must be set properly: =20 - - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - (Size of SPI flash address in bytes (3 or 4) ) - - - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - (Size of minimal erase block in bytes) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - (Size of SPI flash page) - - - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize - (Size of SPI flash sector, 65536 bytes by default) - - - gMarvellTokenSpaceGuid.PcdSpiFlashId - (Id of SPI flash) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - (Spi flash polling flag) - - gMarvellTokenSpaceGuid.PcdSpiFlashMode (Default SCLK mode (see SPI_MODE enum in file edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h)) --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 22:57:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id g29sm1120441lfh.3.2017.11.03.10.57.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 10:57:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/eN0JXl5eop+D4WwvX7De5/EiqVFIH2kzHc25yvAPr0=; b=sfgxCO97VJYrc85DhcKOFQ6YEUBrcjiNgqF9fcNQmErHsyHZlg2ml4KzFmTa7eDHZI sebJP2zNQqG/QheMvJg/2LaZLqH093GOynVXqA2oywRDwRCZBuTIyODq8LynvJ/Tfm9A 2Dc0jJT9HpvpIWOoT1YiXdtuHn9/Q9nj/NplIRHGHId36GTUFoy9EnYLy3/T+VPAhk9e 5PA2wbpioV+TINz7WKHoltth4AZXgxyKcn/GPEnRFCEUB24JfUls9It/A/8+HdgClM5S 7R35HWjOvFKWHKTAdDtrlTe4/AiqRJOA9GNNHPRQHm8nKEg9efnJTy5ZjHdXXNd9iQSu ZARw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/eN0JXl5eop+D4WwvX7De5/EiqVFIH2kzHc25yvAPr0=; b=AL9xeCQZgS5/2mbtoMdk+PC2QYoKQU3V/bPsP4AtmnQ2qxwkl1XGggEQhDjPdrPKEI ENtFlnJE1SvzK7Aog/Zevqr1PhZQJ7HV41d+sXgaF6oeqmZ/CBGYTfEMQZ9tyUumqhss Ii1kecwe/OVz9l2qj90LqxwZcMcfg9Wst5jj1edhzEIdCH1FG+hLKN82L27fGJsK5XLD dtrzGNr1AZzaUWWKkldzUhaJnh1LtoMEjneUv+r5iMNgH3EKIJXAbCGDBZ8U2w1mLHSu Jf6BGsV1J9OdloUxU51HycnRan8V+mj9fkditxA+bjyWh0IrvplMtjY3HXwVCkKz/9qS dhzA== X-Gm-Message-State: AMCzsaVeO/+d8ta1wxa12q72Qbz8g1+hVXaA4rMGCUaOqBmg66fRf4sQ fcjJEwpEdPDqLXS6y7d3JwohS0Nk734= X-Google-Smtp-Source: ABhQp+TSMife77LeZ+gJWMPgHDcQuC0X14mvruS8Dw466xuxmnOyXAttXAM/QtI/cskqXRhbuIun6A== X-Received: by 10.46.17.87 with SMTP id f84mr3218596lje.167.1509731849691; Fri, 03 Nov 2017 10:57:29 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 3 Nov 2017 18:57:12 +0100 Message-Id: <1509731835-5664-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509731835-5664-1-git-send-email-mw@semihalf.com> References: <1509731835-5664-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 3/6] Marvell/Drivers: MvSpiFlash: Remove duplicated macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Flash commands macros are already defined in MvSpiFlash.h, so remove them from the protocol header. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Include/Protocol/SpiFlash.h | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/Platform/Marvell/Include/Protocol/SpiFlash.h b/Platform/Marvel= l/Include/Protocol/SpiFlash.h index 4a3053e..4ba29ba 100644 --- a/Platform/Marvell/Include/Protocol/SpiFlash.h +++ b/Platform/Marvell/Include/Protocol/SpiFlash.h @@ -36,17 +36,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. =20 #include =20 -#define CMD_READ_ID 0x9f -#define READ_STATUS_REG_CMD 0x0b -#define CMD_WRITE_ENABLE 0x06 -#define CMD_FLAG_STATUS 0x70 -#define CMD_WRITE_STATUS_REG 0x01 -#define CMD_READ_ARRAY_FAST 0x0b -#define CMD_PAGE_PROGRAM 0x02 -#define CMD_BANK_WRITE 0xc5 -#define CMD_ERASE_64K 0xd8 -#define CMD_4B_ADDR_ENABLE 0xb7 - extern EFI_GUID gMarvellSpiFlashProtocolGuid; =20 typedef struct _MARVELL_SPI_FLASH_PROTOCOL MARVELL_SPI_FLASH_PROTOCOL; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 22:57:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509731860993546.0636557594026; Fri, 3 Nov 2017 10:57:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F1A26202E5E6B; Fri, 3 Nov 2017 10:53:38 -0700 (PDT) Received: from mail-lf0-x22c.google.com (mail-lf0-x22c.google.com [IPv6:2a00:1450:4010:c07::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CC634202E5E6B for ; Fri, 3 Nov 2017 10:53:37 -0700 (PDT) Received: by mail-lf0-x22c.google.com with SMTP id r129so4062431lff.8 for ; Fri, 03 Nov 2017 10:57:33 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id g29sm1120441lfh.3.2017.11.03.10.57.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 10:57:30 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22c; helo=mail-lf0-x22c.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wDcC4mmdpxdpBgO0Nh4rpPK1WBPB2S5isAhf8doiBII=; b=zuyF4ZwdWnhaYQhy0q8Nzz8EszI8cz5B/ZFU75A22etx2YTFT4EItg2hktJLOrmnQS 7Ne9GgWODvarMnOY+I12X6IQbhIZYkh+gwgSBk174hJXHcmM/N2qORQTzfukeJZBi0yY auRSerCVwRAjj8uPZ9MI9VcCa88WW0+hSJaVHVgRR3I6g5o5cJPdVMJ3F9uNqXt54pAO scz4SRaJ4zHGh8oS+WbYgtxelIMR5HUfMNBnMzcv66h8ApskPfXCfzIb9kW3G92Dicpa L2BTyBV0em2s+p+N9gragXPqFtF0LuP1MIhht3z2IBXlFcjMZnoFPVQUQ/IeosR+hn/G xPiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wDcC4mmdpxdpBgO0Nh4rpPK1WBPB2S5isAhf8doiBII=; b=fDZQqBbiaHBiXVzFdTtIX1mpFkszHOTfETDTE1mNCi6yWcRRokY8x6VFDfnlXLzs3D 30NevNTlhTTtVz8NV/214JH/qccaH1utN3t0ShtZOSEAT7tlnKWVyvO3rwL1P/8CHvf1 8nodV1iz6vb/u6ZankfjMfJjx6kOQVKfdEU8m5vWtSPQ0HSjSHQ2EsAQ1vwjCvGHr0JE 0Pz3M4fTU/87FHk33ZWTlEHsggBFbO6htHPJJQe1Xtv29AHU9qzB2Kem8ceSek04TGUv ip5klRi7DepigIjWsYV1fAiZNN4nowYwYkmn+wmkjBVtbV5TZe3qaae5OHUGByIiY9iT 2Xjw== X-Gm-Message-State: AMCzsaWad9Az6xHV74ikJkca8802zxCGNu0yL5kmvReIXjGWYw9g5Gy5 iN3w0VpM54TDayKe0ipc/pSoS5mezs0= X-Google-Smtp-Source: ABhQp+TsD86WJk1ZLXG3zCh4wUrPnrHpy4jbKI8Z3HY20XSaTcwhe5yKNXXnf00xzqBdMcnmn4VKZA== X-Received: by 10.46.93.137 with SMTP id v9mr3263264lje.39.1509731851118; Fri, 03 Nov 2017 10:57:31 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 3 Nov 2017 18:57:13 +0100 Message-Id: <1509731835-5664-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509731835-5664-1-git-send-email-mw@semihalf.com> References: <1509731835-5664-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 4/6] Marvell/Applications: SpiTool: Do not override existing slave device X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Current usage of sf command requires running 'sf probe' prior to executing any other option. Because it is done in two separate steps, it turned out that SpiMasterProtocol->SetupDevice could easily overwrite valid Slave pointer when performing second operation. Fix the issue by allocating Slave device only once and keep it as global variable in the SpiTool application. This patch also updates FirmwareUpdate command to follow the modified SetupDevice operation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 4 ++-- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 21 ++++++++++----= ------ Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 17 ++++++++------= -- Platform/Marvell/Drivers/Spi/MvSpiDxe.h | 1 + Platform/Marvell/Include/Protocol/Spi.h | 1 + 5 files changed, 24 insertions(+), 20 deletions(-) diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c b/Platf= orm/Marvell/Applications/FirmwareUpdate/FUpdate.c index 750e52a..9ccb1c7 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c @@ -240,7 +240,7 @@ ShellCommandRunFUpdate ( ) { IN SHELL_FILE_HANDLE FileHandle; - SPI_DEVICE *Slave; + SPI_DEVICE *Slave =3D NULL; UINT64 FileSize; UINTN *FileBuffer =3D NULL; CHAR16 *ProblemParam; @@ -302,7 +302,7 @@ ShellCommandRunFUpdate ( } =20 // Setup and probe SPI flash - Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, 0, 0); + Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Slave, 0, 0= ); if (Slave =3D=3D NULL) { Print(L"%s: Cannot allocate SPI device!\n", CMD_NAME_STRING); goto HeaderError; diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index 68a6cf7..cf91581 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -58,6 +58,8 @@ EFI_HANDLE gShellSfHiiHandle =3D NULL; =20 BOOLEAN InitFlag =3D 1; =20 +STATIC SPI_DEVICE *mSlave; + STATIC CONST SHELL_PARAM_ITEM ParamList[] =3D { {L"read", TypeFlag}, {L"readfile", TypeFlag}, @@ -191,7 +193,6 @@ ShellCommandRunSpiFlash ( ) { EFI_STATUS Status; - SPI_DEVICE *Slave; LIST_ENTRY *CheckPackage; EFI_PHYSICAL_ADDRESS Address =3D 0, Offset =3D 0; SHELL_FILE_HANDLE FileHandle =3D NULL; @@ -273,8 +274,8 @@ EFI_STATUS Status; Cs =3D PcdGet32 (PcdSpiFlashCs); =20 // Setup new spi device - Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Cs, Mode); - if (Slave =3D=3D NULL) { + mSlave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, mSlave, Cs= , Mode); + if (mSlave =3D=3D NULL) { Print(L"sf: Cannot allocate SPI device!\n"); return SHELL_ABORTED; } @@ -282,9 +283,11 @@ EFI_STATUS Status; switch (Flag) { case PROBE: // Probe spi bus - Status =3D FlashProbe (Slave); + Status =3D FlashProbe (mSlave); if (EFI_ERROR(Status)) { // No supported spi flash detected + SpiMasterProtocol->FreeDevice(mSlave); + mSlave =3D NULL; return SHELL_ABORTED; } else { return Status; @@ -411,23 +414,21 @@ EFI_STATUS Status; switch (Flag) { case READ: case READ_FILE: - Status =3D SpiFlashProtocol->Read (Slave, Offset, ByteCount, Buffer); + Status =3D SpiFlashProtocol->Read (mSlave, Offset, ByteCount, Buffer); break; case ERASE: - Status =3D SpiFlashProtocol->Erase (Slave, Offset, ByteCount); + Status =3D SpiFlashProtocol->Erase (mSlave, Offset, ByteCount); break; case WRITE: case WRITE_FILE: - Status =3D SpiFlashProtocol->Write (Slave, Offset, ByteCount, Buffer); + Status =3D SpiFlashProtocol->Write (mSlave, Offset, ByteCount, Buffer); break; case UPDATE: case UPDATE_FILE: - Status =3D SpiFlashProtocol->Update (Slave, Offset, ByteCount, Buffer); + Status =3D SpiFlashProtocol->Update (mSlave, Offset, ByteCount, Buffer= ); break; } =20 - SpiMasterProtocol->FreeDevice(Slave); - if (EFI_ERROR (Status)) { Print (L"sf: Error while performing spi transfer\n"); return SHELL_ABORTED; diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index 3b49147..a7db5f2 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -296,21 +296,22 @@ SPI_DEVICE * EFIAPI MvSpiSetupSlave ( IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE *Slave, IN UINTN Cs, IN SPI_MODE Mode ) { - SPI_DEVICE *Slave; + if (!Slave) { + Slave =3D AllocateZeroPool (sizeof(SPI_DEVICE)); + if (Slave =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Cannot allocate memory\n")); + return NULL; + } =20 - Slave =3D AllocateZeroPool (sizeof(SPI_DEVICE)); - if (Slave =3D=3D NULL) { - DEBUG((DEBUG_ERROR, "Cannot allocate memory\n")); - return NULL; + Slave->Cs =3D Cs; + Slave->Mode =3D Mode; } =20 - Slave->Cs =3D Cs; - Slave->Mode =3D Mode; - SpiSetupTransfer (This, Slave); =20 return Slave; diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.h index 1401f62..e7e280a 100644 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.h +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.h @@ -125,6 +125,7 @@ SPI_DEVICE * EFIAPI MvSpiSetupSlave ( IN MARVELL_SPI_MASTER_PROTOCOL * This, + IN SPI_DEVICE *Slave, IN UINTN Cs, IN SPI_MODE Mode ); diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index 6f26a36..98fcc07 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -88,6 +88,7 @@ typedef SPI_DEVICE * (EFIAPI *MV_SPI_SETUP_DEVICE) ( IN MARVELL_SPI_MASTER_PROTOCOL *This, + IN SPI_DEVICE *Slave, IN UINTN Cs, IN SPI_MODE Mode ); --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 22:57:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id g29sm1120441lfh.3.2017.11.03.10.57.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 10:57:31 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WBAZ7p8GvIMHhYUJbATgoQurxwgGRZPPImZqi0oww+Q=; b=oE3zpOCrdVJio2ePyaKlHBShHL/978hYDr3q/Vm+X+I5y1yj5KuAA2z6+WZq7Mipgl IlQOPJeoKoB2CupFbqvtYvpb+gX1rDMxkyVCzCf+GxqEFEJtNovKprwecCPh23GF2Gat aZkyRf6yJYZ468gtzR5K8cssomCs1VmDAUbQzszI36tfw07XUPg7c2dqsUOrBMLqxgZd XydOuuHNQz8VSgxdMH5QsnE7vIqC8AHWH29m2WT7TQ54SOODvCLzgkOtZBnYElOWmA48 rUbFg/JeNLWBp+Wxc5WXYsiJ1HHJig/yJ6unVAbL0GNWMkaonnyvwgPTqLeWtGJncm10 QXuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WBAZ7p8GvIMHhYUJbATgoQurxwgGRZPPImZqi0oww+Q=; b=qFiASNA9A3nd45YuNak1uNtpIiQ8xaAT9LA70K+gOlFaPWQk7F7PxLIJdhz5wty3er ew1Yy/eQ3xarnaKusBBryvoyH7LZQzc8JvkM3DRwwi+QaWSFT8evRPDsrrNXzlE18isi gddBaBX6gw1dePSoMuSB8W7sk2HulejHD/c/q/O+KT59uc+mhvugtd+Ga5rMsEOL7yri aGqZS1MiFaqiasckt4mQj1RlrN/XvQu/S1er/eefdQtqJWunD17/DD2xfX+jrrlS0cxg 02ITmN9XjNRBhbOe+tWbSj/s0uzEXXCP3DvwBRRD6vL2VE5xCpZO2SGpf4SLSoDRghuS 73hA== X-Gm-Message-State: AMCzsaUxBNofA82BrVVBzlM18Npcp6kauAbXVzJWWmAul5El6++2bOeE hN5RJW47QUSupS3pFdq7VaqmKh+xVkw= X-Google-Smtp-Source: ABhQp+RRWaMYrqIXPNjkVydhWKNBllQcTWzBO7NjbqM1ixhappcJfX01a+t0+JRsoygAZ4RKWjvHBQ== X-Received: by 10.46.4.85 with SMTP id 82mr3392478lje.4.1509731852479; Fri, 03 Nov 2017 10:57:32 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 3 Nov 2017 18:57:14 +0100 Message-Id: <1509731835-5664-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509731835-5664-1-git-send-email-mw@semihalf.com> References: <1509731835-5664-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 5/6] Marvell/Drivers: MvSpiFlash: Fix bank selection for Spansion X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Spansion SPI flash devices use different command for bank selection. Update it, basing on the first byte of flash ID. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 5 +++++ Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 1 + 2 files changed, 6 insertions(+) diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index 4a97ba9..456d9f9 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -150,6 +150,11 @@ SpiFlashCmdBankaddrWrite ( { UINT8 Cmd =3D CMD_BANK_WRITE; =20 + /* Update bank selection command for Spansion */ + if (Slave->Info->Id[0] =3D=3D NOR_FLASH_ID_SPANSION) { + Cmd =3D CMD_BANKADDR_BRWR; + } + MvSpiFlashWriteCommon (Slave, &Cmd, 1, &BankSel, 1); } =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.h index 2583484..f09ff50 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h @@ -57,6 +57,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_READ_ARRAY_FAST 0x0b #define CMD_PAGE_PROGRAM 0x02 #define CMD_BANK_WRITE 0xc5 +#define CMD_BANKADDR_BRWR 0x17 #define CMD_ERASE_4K 0x20 #define CMD_ERASE_32K 0x52 #define CMD_ERASE_64K 0xd8 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue Apr 30 22:57:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509731867701597.9099106148988; Fri, 3 Nov 2017 10:57:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 79A62202E5E61; Fri, 3 Nov 2017 10:53:43 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 66F77203555FE for ; Fri, 3 Nov 2017 10:53:40 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id a16so4086447lfk.0 for ; Fri, 03 Nov 2017 10:57:35 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id g29sm1120441lfh.3.2017.11.03.10.57.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 03 Nov 2017 10:57:33 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jkTvaKcMBFd591AN5YKAflZwiCaHHwVusugTfpkIOM4=; b=VKTjyTo9QXFOEwvqfDQMaeBzIcAuSXQPKUY7eim0ZsY/phz7YAo60GjqIlYdb2fPf2 Wz1B5bf8Nv3H/t2SKdmUVc0FrcW8vvhqMHC/vvu+gAE3W0/fWcKeVbUH4MBySuknOY+s bemMi80ZnTgQ8c0BaMK1/MhTCW0m8sn6xCI2p8UzSWitalSMsRJ+bNy+Aq+QqQRMn6aC u9YQtmFmLg5qZgsPJT2zAInoqPjeNIrJdrXZOJSCF9GO5tREmKRpJTCcFeV/ECvGgkrz fUXDh1aWe2m07/Pi5hVGtCKZs6yydFhYwOl68j72bWj5ViuOJYVDT8MbnqxYm347/Jtm m2Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jkTvaKcMBFd591AN5YKAflZwiCaHHwVusugTfpkIOM4=; b=ZnV0Bsrj8liu5xFUd5BES4u1o4vvmJbXJhvW++lj7g6Pawk91cdfd3R7mqDbAS15Yu OlwH8L0c+nPxemXuSkZVkdOTcK/+cOJxMxEaNMQIi4m+qLcjUMYH4FKGfgoISwlc8QpO glGUMclAOC4DJpBNF1bccMcsilvO8iTgtznIEZqXibxM4mYjRPvCLJ+xK/GwkzB0281C Li/JzgcQb+/y+YXhSgtehtXFxYrYsRUgFNbgGtMTpP2De1FLmWwo9ErtWYwSXakcmAsM 4Ku+bObdXw5/0oXqkRUFZ0JBXGKmk2qYmpnU02i2R1sYjpqrfaAYHa7uI2nI7/AsTqlE ZjTg== X-Gm-Message-State: AJaThX6yhTagzLCc3BNb1/wNTAoMsOJ5L1dqOmoco8t83twQDb3F227w DlwFsqxGiViY1ZFLy/T8YZI5G7tgZdQ= X-Google-Smtp-Source: ABhQp+Qvlc9jDgPGBPsL0fKia1bkrkI6l9GhjPYOPX84AkOG4bg4PmAMp1s3QWQN2JGmcVeDrmX/MQ== X-Received: by 10.25.151.17 with SMTP id z17mr2878925lfd.153.1509731853673; Fri, 03 Nov 2017 10:57:33 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 3 Nov 2017 18:57:15 +0100 Message-Id: <1509731835-5664-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509731835-5664-1-git-send-email-mw@semihalf.com> References: <1509731835-5664-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 6/6] Marvell/Drivers: MvSpiDxe: Keep data in SPI_DEVICE structure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In the MvSpiDxe driver obtaining host register base address, controller clock and device maximum frequency directly from PCDs was done all over the code. This patch cleans up the parameters' handling and enables accessing them from SPI_DEVICE structure fields. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 48 ++++++++++++-------- Platform/Marvell/Include/Protocol/Spi.h | 2 + 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index a7db5f2..c60a520 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -38,12 +38,13 @@ SPI_MASTER *mSpiMasterInstance; STATIC EFI_STATUS SpiSetBaudRate ( + IN SPI_DEVICE *Slave, IN UINT32 CpuClock, IN UINT32 MaxFreq ) { UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDi= ff; - UINTN SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 MinBaudDiff =3D 0xFFFFFFFF; BestSppr =3D 0; @@ -93,26 +94,28 @@ SpiSetBaudRate ( STATIC VOID SpiSetCs ( - UINT8 CsId + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg &=3D ~SPI_CS_NUM_MASK; - Reg |=3D (CsId << SPI_CS_NUM_OFFSET); + Reg |=3D (Slave->Cs << SPI_CS_NUM_OFFSET); MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg); } =20 STATIC VOID SpiActivateCs ( - UINT8 IN CsId + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 - SpiSetCs(CsId); + SpiSetCs(Slave); Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg |=3D SPI_CS_EN_MASK; MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg); @@ -121,10 +124,11 @@ SpiActivateCs ( STATIC VOID SpiDeactivateCs ( - VOID + IN SPI_DEVICE *Slave ) { - UINT32 Reg, SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + UINT32 Reg; + UINTN SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CTRL_REG); Reg &=3D ~SPI_CS_EN_MASK; @@ -139,14 +143,15 @@ SpiSetupTransfer ( ) { SPI_MASTER *SpiMaster; - UINT32 Reg, SpiRegBase, CoreClock, SpiMaxFreq; + UINT32 Reg, CoreClock, SpiMaxFreq; + UINTN SpiRegBase; =20 SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); =20 // Initialize values from PCDs - SpiRegBase =3D PcdGet32 (PcdSpiRegBase); - CoreClock =3D PcdGet32 (PcdSpiClockFrequency); - SpiMaxFreq =3D PcdGet32 (PcdSpiMaxFrequency); + SpiRegBase =3D Slave->HostRegisterBaseAddress; + CoreClock =3D Slave->CoreClock; + SpiMaxFreq =3D Slave->MaxFreq; =20 EfiAcquireLock (&SpiMaster->Lock); =20 @@ -154,9 +159,9 @@ SpiSetupTransfer ( Reg |=3D SPI_BYTE_LENGTH; MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg); =20 - SpiSetCs(Slave->Cs); + SpiSetCs(Slave); =20 - SpiSetBaudRate (CoreClock, SpiMaxFreq); + SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq); =20 Reg =3D MmioRead32 (SpiRegBase + SPI_CONF_REG); Reg &=3D ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_= MASK); @@ -194,21 +199,22 @@ MvSpiTransfer ( { SPI_MASTER *SpiMaster; UINT64 Length; - UINT32 Iterator, Reg, SpiRegBase; + UINT32 Iterator, Reg; UINT8 *DataOutPtr =3D (UINT8 *)DataOut; UINT8 *DataInPtr =3D (UINT8 *)DataIn; UINT8 DataToSend =3D 0; + UINTN SpiRegBase; =20 SpiMaster =3D SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This); =20 - SpiRegBase =3D PcdGet32 (PcdSpiRegBase); + SpiRegBase =3D Slave->HostRegisterBaseAddress; =20 Length =3D 8 * DataByteCount; =20 EfiAcquireLock (&SpiMaster->Lock); =20 if (Flag & SPI_TRANSFER_BEGIN) { - SpiActivateCs (Slave->Cs); + SpiActivateCs (Slave); } =20 // Set 8-bit mode @@ -245,7 +251,7 @@ MvSpiTransfer ( } =20 if (Flag & SPI_TRANSFER_END) { - SpiDeactivateCs (); + SpiDeactivateCs (Slave); } =20 EfiReleaseLock (&SpiMaster->Lock); @@ -312,6 +318,10 @@ MvSpiSetupSlave ( Slave->Mode =3D Mode; } =20 + Slave->HostRegisterBaseAddress =3D PcdGet32 (PcdSpiRegBase); + Slave->CoreClock =3D PcdGet32 (PcdSpiClockFrequency); + Slave->MaxFreq =3D PcdGet32 (PcdSpiMaxFrequency); + SpiSetupTransfer (This, Slave); =20 return Slave; diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index 98fcc07..d993021 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -53,6 +53,8 @@ typedef struct { SPI_MODE Mode; UINT32 AddrSize; NOR_FLASH_INFO *Info; + UINTN HostRegisterBaseAddress; + UINTN CoreClock; } SPI_DEVICE; =20 typedef --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel