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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:27 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pXZDa8JIbpsNYk32B/nngHSyy2diq8o7iUTlMRNNjY4=; b=hllEdROiVWskoBpCVbT97ZOPfNJmgZR+q2F0ThpXkdIlrLjvyq5tW1DxlB8eQ9yOWT FpB4Ph8qVqpXB6wOiyMS8PDIzrhSvFEZblAhj5Xy3M1BEsZ001uANPaKDX+d1tEkXXcH G89BF0b0HJ+co5Na47ajg+eAEwu56VvQ25u5msvquhaT0Vj75NQXar5wf5LlVZeLkec0 wXmyVgRpdW819AqNiw/w2b1Htpf/bhIqp1v0RuAThiN36ojeHGkr40oSMLlWCca4E7l2 RMFv5+siAO1lfOu42WdEUj2PvcZS7mjiR10XleZtmugVIb5ughthT1ekANG1kv+wdy8s 1qZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pXZDa8JIbpsNYk32B/nngHSyy2diq8o7iUTlMRNNjY4=; b=biF7E2Ccs5PP5F6uz6/aqMDIw5Z6Zk8z+5ZUj+QkNTyfgERB1dfA5YSlN09wsb+Tr/ gLrzq13RfMyrUPhJsbOe4/lM1hEwV+cEOY5CUz5pPhkdhRIO0ssyoqGgebUttD54FNnL /GymERxsizOtxOJxNIW7Y+qo22WnCKes5Mu2OX3+98YnqAXD6SaX+WN7/dvCnZRqG95i FQE4U3nzliboo11QpBIY5h2vNLUmRS8uo86R8FLBQkHlnLaSOt55LZfHbhFiLldMS5nu FAUb11EHSOdwrFvouKm1bgxY42h9p/U7ZWXxoR9ykOD25JggCLX6qEVj+M6a4P115vcS IhFw== X-Gm-Message-State: AMCzsaX1xipB7QIc6U/uTC6qZVEvcstQORc2If7DNOi3/99mUd4kG8Nm JHLsLHD1qKLql8zTVEvF0wuEbAAMJsA= X-Google-Smtp-Source: ABhQp+T066dkn/ybBbIR0BOJTxej7g0t8/KcwBQHt4SDCpkmhErEgebNKctxJ7mHFpzNROfC9S3xlw== X-Received: by 10.25.115.14 with SMTP id o14mr7181939lfc.79.1509066868842; Thu, 26 Oct 2017 18:14:28 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:43 +0200 Message-Id: <1509066832-5285-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 01/10] Marvell/Drivers: MvI2cDxe: Abort transaction immediately upon fail X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, David Greeson , neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: David Greeson Although the I2C transaction routines were prepared to return their status, they were never used. This could cause bus lock-up e.g. in case of failing to send a slave address, the data transfer was attempted to be continued anyway. This patch fixes faulty behavior by checking transaction status and stopping it immediately, once the fail is detected. On the occasion fix style around modified functions calls. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: David Greeson [Style adjustment and cleanup] Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 62 +++++++++++++------- 1 file changed, 41 insertions(+), 21 deletions(-) diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index d85ee0b..b4599d2 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -565,6 +565,7 @@ MvI2cStartRequest ( UINTN Transmitted; I2C_MASTER_CONTEXT *I2cMasterContext =3D I2C_SC_FROM_MASTER(This); EFI_I2C_OPERATION *Operation; + EFI_STATUS Status =3D EFI_SUCCESS; =20 ASSERT (RequestPacket !=3D NULL); ASSERT (I2cMasterContext !=3D NULL); @@ -574,33 +575,52 @@ MvI2cStartRequest ( ReadMode =3D Operation->Flags & I2C_FLAG_READ; =20 if (Count =3D=3D 0) { - MvI2cStart ( I2cMasterContext, - (SlaveAddress << 1) | ReadMode, - I2C_TRANSFER_TIMEOUT - ); + Status =3D MvI2cStart (I2cMasterContext, + (SlaveAddress << 1) | ReadMode, + I2C_TRANSFER_TIMEOUT); } else if (!(Operation->Flags & I2C_FLAG_NORESTART)) { - MvI2cRepeatedStart ( I2cMasterContext, - (SlaveAddress << 1) | ReadMode, - I2C_TRANSFER_TIMEOUT - ); + Status =3D MvI2cRepeatedStart (I2cMasterContext, + (SlaveAddress << 1) | ReadMode, + I2C_TRANSFER_TIMEOUT); } =20 + /* I2C transaction was aborted, so stop further transactions */ + if (EFI_ERROR (Status)) { + MvI2cStop (I2cMasterContext); + break; + } + + /* + * If sending the slave address was successful, + * proceed to read or write section. + */ if (ReadMode) { - MvI2cRead ( I2cMasterContext, - Operation->Buffer, - Operation->LengthInBytes, - &Transmitted, - Count =3D=3D 1, - I2C_TRANSFER_TIMEOUT - ); + Status =3D MvI2cRead (I2cMasterContext, + Operation->Buffer, + Operation->LengthInBytes, + &Transmitted, + Count =3D=3D 1, + I2C_TRANSFER_TIMEOUT); + Operation->LengthInBytes =3D Transmitted; } else { - MvI2cWrite ( I2cMasterContext, - Operation->Buffer, - Operation->LengthInBytes, - &Transmitted, - I2C_TRANSFER_TIMEOUT - ); + Status =3D MvI2cWrite (I2cMasterContext, + Operation->Buffer, + Operation->LengthInBytes, + &Transmitted, + I2C_TRANSFER_TIMEOUT); + Operation->LengthInBytes =3D Transmitted; } + + /* + * The I2C read or write transaction failed. + * Stop the I2C transaction. + */ + if (EFI_ERROR (Status)) { + MvI2cStop (I2cMasterContext); + break; + } + + /* Check if there is any more data to be sent */ if (Count =3D=3D RequestPacket->OperationCount - 1) { MvI2cStop ( I2cMasterContext ); } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 01:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509066877755521.7957106086754; Thu, 26 Oct 2017 18:14:37 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 552642034A87F; Thu, 26 Oct 2017 18:10:47 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9A7832034A874 for ; Thu, 26 Oct 2017 18:10:45 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id p184so5645502lfe.12 for ; Thu, 26 Oct 2017 18:14:32 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:29 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RRJgYfDtYb8TQZ9IqyWVnPnAW5ONCPT20mwBdE+HwO0=; b=mwOwzIiDnbqAkeCztw9LQW6ox4NDDWtCbtH0ZMt+DsVFkOWLlupJOpxOSbMEHtKqBT aPlUuto1XnOvmwCEmBXo38YiGvtdOetawlRJrIOF7VIZOEd0NvmzPDVk0iqCemMsm63g A4pX8XqwewzCNR3lzxp2m41vsKdKEfFz0lAN1dEvlG0tZc7LQJYA1Bny/VGR1BKi64uW D+QprNX6UOo6v+TGc2hHlK1KCzmfOewkc5f8myuoV7jdOq6wZqqyKepWRC/j9NNmo0h9 0fOwCSM9cmUN9Wob30VU6RlhnEaSHQ2kzl8GRI/taYBzyZsU4xOH1SGy1HBkQR5O05Ht nQXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RRJgYfDtYb8TQZ9IqyWVnPnAW5ONCPT20mwBdE+HwO0=; b=lcje86n6eHseOpk41j1JVnizcotv99euON63HXotVKHGBW52qJZ4s6dUwbt3nuysIo JcLnuEp6/E7bkXvHc+YqOleohn2cDJI9f+eySoYiY7E/PynLLEkjFzKXccU994fROIbu TrDxguvwTwI2rTzNQYFu2cptUtLcaE2biEs9en5lrsodmQYnbZb44FEM2SjFjkM7+ahE KI0GYW2RNwTZiMQPaHqcnTeMI0ZdCZGwu+3quuHCsWI0ASsWG/nAK9/ZXXlPf6xers4T nAVtTXMJnLxb40T036f1LgGigDeA4pVlvCkfghK+qYP4grrXO5qK9kN+foRAWfqdItvW BtIw== X-Gm-Message-State: AMCzsaWcXYnEMk7WIlkjXzbRaTsqNkPr84xpLGnP+jnfntLEGM03nsdw IJ5OVfH5lAmUgNF8A5NmEPOeDq8FBfc= X-Google-Smtp-Source: ABhQp+RIgkInnGiG7I5/qkW4Qrv2QY5t3bmT50RAL2SDHgtnKnGsl9OeVM3uMF0J8WFoPN8Ima5wFg== X-Received: by 10.46.43.69 with SMTP id q66mr9917195lje.104.1509066870457; Thu, 26 Oct 2017 18:14:30 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:44 +0200 Message-Id: <1509066832-5285-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 02/10] Marvell/Drivers: MvI2cDxe: Fix returning status in MvI2cStartRequest X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In MvI2cStartRequest the status was assigned to the variable without dereferencing a pointer. Fix it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index b4599d2..a62383f 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -627,7 +627,7 @@ MvI2cStartRequest ( } =20 if (I2cStatus !=3D NULL) - I2cStatus =3D EFI_SUCCESS; + *I2cStatus =3D EFI_SUCCESS; if (Event !=3D NULL) gBS->SignalEvent(Event); return EFI_SUCCESS; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 01:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509066880237622.4426390711291; Thu, 26 Oct 2017 18:14:40 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 96BAF2034A87B; Thu, 26 Oct 2017 18:10:50 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1514D2034A87A for ; Thu, 26 Oct 2017 18:10:47 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id a69so5682191lfe.5 for ; Thu, 26 Oct 2017 18:14:33 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:31 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XOFO9TtAZ3RTSamL64u3tOj918MQw0Favl3owH37cuk=; b=WFJeS/XUgjzkisIevf/sqAHZ/1kf4xhs4hhpOvlYChz8SsmJ0woDu4VrUP0i4c2fzD K+qs7hnzuH9X8kIdZkcEFfbJFGINzJ4VSaWpQi8qwaEMyvWd1IzA/30UFKUBu0t2ZWZp KawlCzovTNHrPPrQZrcJMQDiRIogf0NjvyWiDLVYLBpqyGj+bKQs2epJgGDaNvmLWKBh 7HXHwZvw65k9Gyf4TYRHCNVrfyfVn6JyJIcPi1d4EKMy7/rlIxON4rKnOeHj3U4x+wpj orwX8hPZOsH3zxlrwC3E0OvjaRP/nz9nofC4kHTF0GJz4Xf1TSHaVAD7JLj96Ta2846A miOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XOFO9TtAZ3RTSamL64u3tOj918MQw0Favl3owH37cuk=; b=mq3tqPLer6gc1RdYH73pGwsJ5qv+bXF8CoCRUJSCYL/TWHz/UXbaXt3G/FNhGw6FPr SxGE/T4uAwIU+D6But/m0uTX/Td1gmR2rP4lfiLX6X3MAWlfVh6XHwcm2wS92IGoCOyj I4cpN+o5wE42AhhwJHDqopJb4jd0YmWmIrw54krLoIPMAR+ThCcEcvnB0BnYSuazM0Z6 C6X4iDYmswtpwtf/LXyaPwZTSWpkPxbe3ecPMDDLoYhJZ0vSVYqVOIBzeSlfr0k/8QGD 9trWk4CLJ8N97hrKG2hTB9a6NbKnVFipd+35uPZUDxV47y9TxEXgcbpFj5xWADmgPp7P ElGQ== X-Gm-Message-State: AMCzsaVYsZeQqY0Tmv+/EjpJHRZQeKDv0t3AKppCQdC1h22mx4nRlcjU tKeM67JIKnema/hDV91ZDjs1Myk56R8= X-Google-Smtp-Source: ABhQp+QGuqdnEpugSV2RBrcmQJEXPs2SmYhEfX6+4B91HrFdUt8odBlnSMAvL7HY4Ae2ldUler0ttg== X-Received: by 10.46.82.14 with SMTP id g14mr10082183ljb.118.1509066871761; Thu, 26 Oct 2017 18:14:31 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:45 +0200 Message-Id: <1509066832-5285-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 03/10] Marvell/Drivers: MvI2cDxe: Reduce bus occupation time X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, David Greeson , neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: David Greeson During each transaction start, clearing the I2C_CONTROL_FLAG was surrounded by 3 uncoditional stalls. This was not necessary, so replace them with one busy-wait loop, whose polling count could be also safely reduced. Above improvements result in faster transfer initialization and allow to reduce the I2C bus occupation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: David Greeson Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 6 +----- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h | 2 +- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index a62383f..d6f590d 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -243,9 +243,8 @@ MvI2cClearIflg ( IN I2C_MASTER_CONTEXT *I2cMasterContext ) { - gBS->Stall(I2C_OPERATION_TIMEOUT); + MvI2cPollCtrl (I2cMasterContext, I2C_OPERATION_TIMEOUT, I2C_CONTROL_IFLG= ); MvI2cControlClear(I2cMasterContext, I2C_CONTROL_IFLG); - gBS->Stall(I2C_OPERATION_TIMEOUT); } =20 /* Timeout is given in us */ @@ -295,9 +294,6 @@ MvI2cLockedStart ( MvI2cClearIflg(I2cMasterContext); } =20 - /* Without this delay we Timeout checking IFLG if the Timeout is 0 */ - gBS->Stall(I2C_OPERATION_TIMEOUT); - if (MvI2cPollCtrl(I2cMasterContext, Timeout, I2C_CONTROL_IFLG)) { DEBUG((DEBUG_ERROR, "MvI2cDxe: Timeout sending %sSTART condition\n", Mask =3D=3D I2C_STATUS_START ? "" : "repeated ")); diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h index 028fd54..3c9beaf 100644 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.h @@ -68,7 +68,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #define I2C_SOFT_RESET 0x1c #define I2C_TRANSFER_TIMEOUT 10000 -#define I2C_OPERATION_TIMEOUT 1000 +#define I2C_OPERATION_TIMEOUT 100 =20 #define I2C_UNKNOWN 0x0 #define I2C_SLOW 0x1 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 01:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509066883249722.6219149979922; Thu, 26 Oct 2017 18:14:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D72232034A884; Thu, 26 Oct 2017 18:10:50 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2625F21CEB122 for ; Thu, 26 Oct 2017 18:10:48 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id a132so5674930lfa.7 for ; Thu, 26 Oct 2017 18:14:34 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:32 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TUMONFAKMpiQWShizYJCsesNltdW4p7QVVldO0pf3Wo=; b=0Sub8FhikZV7d9ivuWrzAqwpQgS0DHbxpr89p+SLCO73RRIa2crRHY6DdobwLza3UH p2MHRmLx7IqbXGV0XIoMBcJngEmZEF2IL7nEavXM9z0RLBsED3eefdQYVBwgeDVsLJ1O E+YUXrwAyFLoN0a9H5OV6OIp0Np5pymxnnPBSUo5Gd52mtTxJENE9dgfz+vE0NdfdYFx qFdrRuQNqflxN0AezebNYsdDfsc1PsFXLPV49ZHUCcS+6UXhQRxPA3vIW5NOfR+PUWIL fQZ3q2YXWNkXmPhdfRee9MnOnpEReqgJjcroWKli6AyXDDd3CneMZhnlWJ2r7mLC94Jl bjdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TUMONFAKMpiQWShizYJCsesNltdW4p7QVVldO0pf3Wo=; b=Fn1Wp2wU5N84NgCtOzruYZZ6b3oLcZjxYLtG4I8evVo5/natWkcunC3Z8QlxkwipV1 mG2AE5PqVb0epZmeXjzcB44+iQ28RX6EHskRVN2Kz8bmMThCQa9Om2c8eoSVg1C4FBdr jCbylAeVKctH/0Lhl76Ne3NHwdD6/os9TP9mUw8fkFVS2zl5NvUPxZ1QzAAaK5AGsX8n +XZHTx5qG6TzZws5WRzoGkhMGk5p8aKK/btu8adl7NWm+Bo1nIk8N9Uq2tVoS2Sdl5lJ dWdm9ddftDcJBVQvtL+AhjFnQnZuy2CMvA3eXbYLYCISNTblMxra59tiFuTR8+g1eOPY 6oGA== X-Gm-Message-State: AMCzsaVDJz2iOU+8IAJwIFWVQBeEjigW8uggRM/g+9vOdQfkOEuekTG7 YYTCySvQe5vt/IXGlkvCEGZhiGDaQ9Y= X-Google-Smtp-Source: ABhQp+TOSJH4Lno8YR+Ge5WCfqmPZxRZMIZQMJ3d7BOyqhOvAcDmoNUko4AgGKYP5yXJJDSn+fYb5g== X-Received: by 10.46.99.203 with SMTP id s72mr9976727lje.7.1509066873043; Thu, 26 Oct 2017 18:14:33 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:46 +0200 Message-Id: <1509066832-5285-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 04/10] Marvell/Library: MppLib: Prevent overwriting PCD values X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, Joe Zhou , ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Joe Zhou After enabling dynamic PCDs, it is possible to reconfigure MPP during platform initialization. It occurred that due to a faulty way of passing temporary values, information obtained from PCDs was overwritten. This patch fixes the issue, which on the occasion simplifies PcdToMppRegs function. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Joe Zhou Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Library/MppLib/MppLib.c | 21 ++++++++------------ 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/Platform/Marvell/Library/MppLib/MppLib.c b/Platform/Marvell/Li= brary/MppLib/MppLib.c index c09acf9..383c820 100644 --- a/Platform/Marvell/Library/MppLib/MppLib.c +++ b/Platform/Marvell/Library/MppLib/MppLib.c @@ -74,7 +74,7 @@ STATIC VOID SetRegisterValue ( UINT8 RegCount, - UINT8 **MppRegPcd, + UINT8 MppRegPcd[][MPP_PINS_PER_REG], UINTN BaseAddr, BOOLEAN ReverseFlag ) @@ -99,10 +99,10 @@ STATIC UINT8 PcdToMppRegs ( UINTN PinCount, - UINT8 **MppRegPcd + UINT8 **MppRegPcd, + UINT8 MppRegPcdTmp[][MPP_PINS_PER_REG] ) { - UINT8 MppRegPcdTmp[MPP_MAX_REGS][MPP_PINS_PER_REG]; UINT8 PcdGroupCount, MppRegCount; UINTN i, j, k, l; =20 @@ -125,14 +125,7 @@ PcdToMppRegs ( for (j =3D 0; j < PCD_PINS_PER_GROUP; j++) { k =3D (PCD_PINS_PER_GROUP * i + j) / MPP_PINS_PER_REG; l =3D (PCD_PINS_PER_GROUP * i + j) % MPP_PINS_PER_REG; - MppRegPcdTmp[k][l] =3D MppRegPcd[i][j]; - } - } - - /* Update input table */ - for (i =3D 0; i < MppRegCount; i++) { - for (j =3D 0; j < MPP_PINS_PER_REG; j++) { - MppRegPcd[i][j] =3D MppRegPcdTmp[i][j]; + MppRegPcdTmp[k][l] =3D (UINT8)MppRegPcd[i][j]; } } =20 @@ -191,6 +184,7 @@ MppInitialize ( BOOLEAN ReverseFlag[MAX_CHIPS]; UINT8 *MppRegPcd[MAX_CHIPS][MPP_MAX_REGS]; UINT32 i, ChipCount; + UINT8 TmpMppValue[MPP_MAX_REGS][MPP_PINS_PER_REG]; =20 ChipCount =3D PcdGet32 (PcdMppChipCount); =20 @@ -203,8 +197,9 @@ MppInitialize ( for (i =3D 0; i < MAX_CHIPS; i++) { if (i =3D=3D ChipCount) break; - RegCount =3D PcdToMppRegs (PinCount[i], MppRegPcd[i]); - SetRegisterValue (RegCount, MppRegPcd[i], BaseAddr[i], ReverseFlag[i]); + + RegCount =3D PcdToMppRegs (PinCount[i], MppRegPcd[i], TmpMppValue); + SetRegisterValue (RegCount, TmpMppValue, BaseAddr[i], ReverseFlag[i]); =20 /* * eMMC PHY IP has its own MPP configuration. --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 01:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509066886088505.99337410874557; Thu, 26 Oct 2017 18:14:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1B7B62034A886; Thu, 26 Oct 2017 18:10:53 -0700 (PDT) Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7BDA921CEB122 for ; Thu, 26 Oct 2017 18:10:49 -0700 (PDT) Received: by mail-lf0-x243.google.com with SMTP id 90so5655102lfs.13 for ; Thu, 26 Oct 2017 18:14:36 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:33 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::243; helo=mail-lf0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c2fyQgv2Z5WT0KL9Kq9Fe8K5V0Zyqvytvrut+0OQ5J0=; b=V9bIAmvubMSKTI3cyyPLPVPhl9am/hG7nLDvvAIFBPTu3l466ZKre2lfjnbmp49Ubx coIG+S9XIQIheaMn+8/TKEmxcYFaPR/c0Yf0wWlE2RlRNb+tAQ0vmBdjvr3txajsrbmj RHRAQm+TpZsI7A8j+ADViIc/Wjk2oZYDXFxo5AxNKdJE9NKk8A4caFQGING+QRgc6RGZ DErE2KHuwrZGlQ5SzhkyNAClu2Rz77dUsDrkEG0d8CRV+tqsHcjh/84/difzC/3lSs6d D8u+EshKVH0oWG7syqfslO2VsB/RCSIwDpUE+aXrX4WBJ2IQBlURHTCe58OvXqJ82N00 55uQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c2fyQgv2Z5WT0KL9Kq9Fe8K5V0Zyqvytvrut+0OQ5J0=; b=PcwdZuA4vojLTJhaPv8PKGUCJVJnSxNk4iGuEvesmwpFR6IYGAI3r5amc38k4M1C3X D2BTldJQ8F8w299REMiAAPZGXZ35WzO23m6GAHNHCQKd7FRhz4li2/7S38eFqZz456as dgjvdqrVnn+ZGNQZdnIEuq+TkEYGcIjB+zScZKHr43rtfomBsuNQMlkOdhZJXdO2eV3e 7l8Qmg/usixLpqfSpzBWLtSyCU4+t4GC20WE1sicX7Z771143jFb4Sk1uSJucY/SDskt W4+Fy9D2biwwIsgRC1taTfM9EUMp77J6xPBESgMQKdAYcXz2eksjR/WEDRwP1m5Ho2d8 kyVA== X-Gm-Message-State: AMCzsaVOMACeGe3pFxgWRxjx0wzQjM/2PiHyk8wCXRTGVVIgQUyjzAXK qBNExxaN96rycYYU+IaYuq/XwE+pieo= X-Google-Smtp-Source: ABhQp+QracqsFNdiTrNojjEzvJk6HXy7y0il3+2EB/flOVkeD5tjfY+vUI4j3PhiAhHDoDFYbNLaiw== X-Received: by 10.46.66.198 with SMTP id h67mr10545534ljf.108.1509066874261; Thu, 26 Oct 2017 18:14:34 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:47 +0200 Message-Id: <1509066832-5285-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 05/10] Marvell/Library: MppLib: Disable the stack protector X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel MppLib may be used very early (in SEC), at which point stack protection measures are more likely to cause harm than help, given that not even the UART has been configured to the point where we can complain usefully. So just disable it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Library/MppLib/MppLib.inf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Platform/Marvell/Library/MppLib/MppLib.inf b/Platform/Marvell/= Library/MppLib/MppLib.inf index 2de9cd0..1268542 100644 --- a/Platform/Marvell/Library/MppLib/MppLib.inf +++ b/Platform/Marvell/Library/MppLib/MppLib.inf @@ -106,3 +106,6 @@ gMarvellTokenSpaceGuid.PcdChip3MppSel7 =20 gMarvellTokenSpaceGuid.PcdPciESdhci + +[BuildOptions] + *_*_*_CC_FLAGS =3D -fno-stack-protector --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 01:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509066889089614.7412022695232; Thu, 26 Oct 2017 18:14:49 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 54CEB2034A88A; Thu, 26 Oct 2017 18:10:53 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9E4032034A882 for ; Thu, 26 Oct 2017 18:10:50 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id a132so5674999lfa.7 for ; Thu, 26 Oct 2017 18:14:37 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:34 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MEQtyXsQqjmj8ow5AzkWa+NyZ/kNRHhP3gpq5lhpC+U=; b=XMAb7ne2uZuztFj4GnHDh6AY72l04xssxoAKTXUYZbB+0AYKiEVe4x+PPmh3KS2KZh G6eErcMaoO8YbRHNWrleeHYLyAL62y2LTTjhYsAmMjNTtmFs5Uz6z5KrcvIeCP0T/eZa SoGmf1IYBLR4/W2L+EuJd6lhuZqpXiHoaHIfBpfo+XgKOqjyx+kU83Ibn4i94VM2c8jW fasj0CDBaw9frX2fpaqxa+5ATqdKeLIfJ887BTmTxEKpEoN5OypefWKsqY0uDsQg0Cva /uzaszARmVF+6y4WFtvMcgcVwThL8bDkiz1XEwTbOUQf4LOqT2OH1GhP25kYw4EfRUf0 oMpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MEQtyXsQqjmj8ow5AzkWa+NyZ/kNRHhP3gpq5lhpC+U=; b=sXw1eH+yNCJjCgE/Ua+CepX1437c6kzOf43zUvgD7SzExo7mTi5G+62txhPBfnPOiT AdVuDnAWogbVl4q08nlo3P6aQj0ArxBpF3V9Mi//gPSGHe0uE3zJ8igMjxG6XF3gJWBW vqhgOt+sjetyIjU0iVxExDwjFxNyk95+cLtgliesy0G281qrtCqpszx2iK76d9gBCiQ8 8QSIP0JCQjUTvBOCOVB0I49RKTn9Kvkk120PVakF6z1h9M4Usgar2SW+vezUrQZTMH5L uE8ns+t0Ih9oI48fpBbgkPt7E4IzSlC4y6CbSQpK7uT7YxRLm3MerGg9wyGQ5ZlJ4m6v 0cAQ== X-Gm-Message-State: AMCzsaWzv7KCPQXSeR3E73KKs78acyyBreSucDAssvv2KgUBKtAWRF28 ouldbgKRoE9b6H7+SMCPiDc94SEfdAY= X-Google-Smtp-Source: ABhQp+RAEzpXYHQuUMDxRDgH37NOsoAWwmQPMOuFGPCojZsvkSPJBhzONLDASCWdc1eTL5tTxkwiKA== X-Received: by 10.46.46.8 with SMTP id u8mr10353032lju.117.1509066875521; Thu, 26 Oct 2017 18:14:35 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:48 +0200 Message-Id: <1509066832-5285-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 06/10] Marvell/Library: MppLib: Take 0xFF placeholders into account X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The MppSel definition PCDs contain 0xFF placeholders for values that should be left untouched. MppLib needs to be taught how to take those into account. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Library/MppLib/MppLib.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/Platform/Marvell/Library/MppLib/MppLib.c b/Platform/Marvell/Li= brary/MppLib/MppLib.c index 383c820..297725f 100644 --- a/Platform/Marvell/Library/MppLib/MppLib.c +++ b/Platform/Marvell/Library/MppLib/MppLib.c @@ -79,18 +79,24 @@ SetRegisterValue ( BOOLEAN ReverseFlag ) { - UINT32 i, j, CtrlVal; + UINT32 i, j, CtrlVal, CtrlMask, PinIndex; INTN Sign; =20 Sign =3D ReverseFlag ? -1 : 1; =20 for (i =3D 0; i < RegCount; i++) { CtrlVal =3D 0; + CtrlMask =3D 0; for (j =3D 0; j < MPP_PINS_PER_REG; j++) { - CtrlVal |=3D MPP_PIN_VAL(7 * (UINTN) ReverseFlag + j * Sign, - MppRegPcd[i][7 * (UINTN) ReverseFlag + j * Sign]); + + PinIndex =3D 7 * (UINTN)ReverseFlag + j * Sign; + + if (MppRegPcd[i][PinIndex] !=3D 0xff) { + CtrlVal |=3D MPP_PIN_VAL(PinIndex, MppRegPcd[i][PinIndex]); + CtrlMask |=3D MPP_PIN_VAL(PinIndex, 0xf); + } } - MmioWrite32 (BaseAddr + 4 * i * Sign, CtrlVal); + MmioAndThenOr32 (BaseAddr + 4 * i * Sign, ~CtrlMask, CtrlVal); } } =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 01:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509066891573225.26518894956905; Thu, 26 Oct 2017 18:14:51 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9461F2034A88C; Thu, 26 Oct 2017 18:10:55 -0700 (PDT) Received: from mail-lf0-x242.google.com (mail-lf0-x242.google.com [IPv6:2a00:1450:4010:c07::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 482F021CEB134 for ; Thu, 26 Oct 2017 18:10:52 -0700 (PDT) Received: by mail-lf0-x242.google.com with SMTP id a132so5675043lfa.7 for ; Thu, 26 Oct 2017 18:14:38 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:36 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::242; helo=mail-lf0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+pgbiwN6vf/suH442VjrtTqEaZr6+AdUix4BO1mVPTY=; b=ygsgnWv+rTBPi7+1sxNpMSkey9I9u+YBFedAKUCTQAU8AuS8QaU7EUUG9kwsyeM7vP JuRJsfZMQuyKUFImDV10ARF/p0qfz5b/wHHfcl3w3uPtMqKl6ILEfgu9hP+TH3Fs1Vkk xQ6khTDAl4Lt/k4e+ftFsMa28xN2xq6RuSwEjJXUD1j14AdYtrUabhlwF4uh3vgCase6 lUxej6uzlZ9yeJa5gWF0PtF1gOWgTg9AwoJwmkKsLTW9W5IFQhmobmZXSkK/vMi54eKC VFFOFddlGlHqsChYzh1NpyTHcZ9ID0hI6GAYGqt+D6vkUqb08GaLzlihwYZCA/gqPTHj 7Q7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+pgbiwN6vf/suH442VjrtTqEaZr6+AdUix4BO1mVPTY=; b=Gjcu42SEJBfsEYZKu5MND6Jr+Amn9RrbbTBl5VbhCyLylQr1KzmopIlQtKP7jgNx9W MCDANxc7CaguVq2rr0jmrsAalyDltJDW7/sFghlffhqEpQkkBbthZOcyFQlt1B83Nu/z KsHctjeDf7Re1YFdFJQ9Q/TnkoGoZ5H/lzBIAZxRb1sRHJIJOFoWi8QPDChCjLC8DAGd x30hWQ75Uvqnu2xeKuNoXEcUHrqOghtPr/7RvN98wduWH2ucJDYtuuSpJ05V1MGvBYgX AOFo+2Kzm53WJrAd8KTCmGkLoRMxE3k8rXJhmuPdYANiB/uWXCn2Oz80R5E+XsBRiddB JD5Q== X-Gm-Message-State: AMCzsaXqozCVrmDsnp7EKXkj/NhPJ3Wf2VvCKFIsY0FnkMWp7/WM10kG Y8jfY3uCMn/4EVLV61pKX+HRC+z1x8w= X-Google-Smtp-Source: ABhQp+Q274TFsQTP84M1Lyr2TJa4D1Wck8k+uXSao69POHwtJzYd8jnQdKtsb4ko+QAcYHDh2IQAiA== X-Received: by 10.46.80.30 with SMTP id e30mr11003707ljb.126.1509066876806; Thu, 26 Oct 2017 18:14:36 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:49 +0200 Message-Id: <1509066832-5285-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 07/10] Marvell/Drivers: Pp2Dxe: Change settings for the always-up link X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Currently initial forcing link status happened for all ports, not only marked as 'always-up'. Although this didn't actually matter for the MAC settings, because MAC is automatically updated with PHY HW polling feature of the controller, perform mv_gop110_fl_cfg only when the appropriate flag is true. Also in such case, force the link as up, using a new library routine. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c | 25 ++++++++++++++++++++ Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h | 6 +++++ Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 6 ++++- 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c index 53154db..c2d0199 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c @@ -4804,6 +4804,31 @@ MvGop110PortEventsMask ( return 0; } =20 +/* + * Sets "Force Link Pass" and "Do Not Force Link Fail" bits. + * This function should only be called when the port is disabled. + */ +VOID +MvGop110GmacForceLinkModeSet( + IN PP2DXE_PORT *Port, + IN BOOLEAN LinkUp + ) +{ + UINT32 RegVal; + + RegVal =3D MvGop110GmacRead (Port, MVPP2_PORT_AUTO_NEG_CFG_REG); + + if (LinkUp) { + RegVal |=3D MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_UP_MASK; + RegVal &=3D ~MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN_MASK; + } else { + RegVal &=3D ~MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_UP_MASK; + RegVal |=3D MVPP2_PORT_AUTO_NEG_CFG_FORCE_LINK_DOWN_MASK; + } + + MvGop110GmacWrite (Port, MVPP2_PORT_AUTO_NEG_CFG_REG, RegVal); +} + INT32 MvGop110FlCfg ( IN PP2DXE_PORT *Port diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h index a7011f7..3ebe294 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h @@ -504,6 +504,12 @@ MvGop110XlgPortLinkEventMask ( IN PP2DXE_PORT *Port ); =20 +VOID +MvGop110GmacForceLinkModeSet ( + IN PP2DXE_PORT *Port, + IN BOOLEAN LinkUp + ); + INT32 MvGop110FlCfg ( IN PP2DXE_PORT *Port diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 2827976..4a1b9d5 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -1310,7 +1310,11 @@ Pp2DxeInitialiseController ( NetCompConfig |=3D MvpPp2xGop110NetcCfgCreate(&Pp2Context->Port); =20 MvGop110PortInit(&Pp2Context->Port); - MvGop110FlCfg(&Pp2Context->Port); + + if (Pp2Context->Port.AlwaysUp =3D=3D TRUE) { + MvGop110GmacForceLinkModeSet (&Pp2Context->Port, TRUE); + MvGop110FlCfg (&Pp2Context->Port); + } =20 Status =3D gBS->CreateEvent ( EVT_SIGNAL_EXIT_BOOT_SERVICES, --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 01:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509066894263138.86948734673763; Thu, 26 Oct 2017 18:14:54 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CE56C2034A88F; Thu, 26 Oct 2017 18:10:55 -0700 (PDT) Received: from mail-lf0-x244.google.com (mail-lf0-x244.google.com [IPv6:2a00:1450:4010:c07::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 48B652034A888 for ; Thu, 26 Oct 2017 18:10:53 -0700 (PDT) Received: by mail-lf0-x244.google.com with SMTP id a2so5653215lfh.11 for ; Thu, 26 Oct 2017 18:14:40 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::244; helo=mail-lf0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ziz/sbppFLzAIoc98FDxG9GdhC99rNuYyqabjsRh7Mg=; b=M59lg0eifnSR90Iyfr+NWqvxZT9qmSTp0osJy6jkZelHj3eenRJxugQdlAz9y3rX9y mtXzOcMWUj+7GlmTtPgHtT0xCBlQXgvppqX4yH2yuslhYa8nM0OHpq7do/d0D0Pjmp3Z t4R4v+wtOOLB0hEk2MYvJZF2fM/Go8Zv9LiAMOIKJfCcI2Zq+axniyfKuUTfetJevKIZ +n5cvxAl74XcjLxjNKE0KhtuU7aBVMSne4k0YL5WHkfjbeyZdpXcwAGh+lasYfHwED0T BV5Ze+gbSced8ijUCmTJni7ikFrErXctrRvQ2IrWhlk6lzL/b0SeAX/cyOZPSoYLn4gi LUag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ziz/sbppFLzAIoc98FDxG9GdhC99rNuYyqabjsRh7Mg=; b=nU+Dcs2ssSj0SXnIU2zltsJ2drY5CRoK0c4yh2OODfNVFGHAKQbLitjlK8jUmlx2Jj AYfnzmWHxvlQ5dk+lD/0hbTEMN8hfHmdvCgjRjA122S0LSa1bTUAud1ZqFuNEyf9qgkI Xa//TXNWGjmpWXCaoJwXGemaWOJ/K75nMoy4VInwlseoIXbEkmsJoKuEFDdxM6qvn2y0 brVbI2VGm7GweWhlTYG78teNJPDSEj65So0LK7zC4qsaEt3OubZqku/43yWQpq1gHRgi qm7laInGXjxXHthv+tvS/Pzm4U9rdhcWxNGu7fi55iO3t1xxJNDTJN2zZNDYQQLx57Su 7M4g== X-Gm-Message-State: AMCzsaVJqRmayWG5NacfQ1tupROsDjcEAfn+Vzf8+RSgl96OBBA6MQ1/ WefMrPB5TJ6KmXt0Y8fnZfT3dgGnwPk= X-Google-Smtp-Source: ABhQp+Q06RELqJ2GiTiQj2nNIaoC20LrXbELemy9eVkxY+FcHlNZYTVVeLWSOj+7Kft9n2dmpZ+g3w== X-Received: by 10.46.93.137 with SMTP id v9mr10151257lje.39.1509066878159; Thu, 26 Oct 2017 18:14:38 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:50 +0200 Message-Id: <1509066832-5285-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 08/10] Marvell/Drivers: XenonDxe: Fix UHS signalling mode setting X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch fixes incorrect settings for UHS mode in SD_MMC_HC_HOST_CTRL2 register for SDR50 and SDR25, of which the latter was missing. This field should be set to: 0x4 for DDR52 0x2 for SDR50 0x1 for SDR25 0x0 for others. This way EmmcSwitchToHighSpeed function is on par with Linux set_uhs_signaling routine in the Xenon driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platfor= m/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 3f73194..4d4833f 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -772,6 +772,8 @@ EmmcSwitchToHighSpeed ( if (IsDdr) { HostCtrl2 =3D BIT2; } else if (ClockFreq =3D=3D 52) { + HostCtrl2 =3D BIT1; + } else if (ClockFreq =3D=3D 26) { HostCtrl2 =3D BIT0; } else { HostCtrl2 =3D 0; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 01:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509066897219120.28942509853619; Thu, 26 Oct 2017 18:14:57 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1695D2034A888; Thu, 26 Oct 2017 18:10:59 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B4DB921CEB142 for ; Thu, 26 Oct 2017 18:10:54 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id l23so5657291lfk.10 for ; Thu, 26 Oct 2017 18:14:41 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:38 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z0oTrunMpZOqlOX2ru72d6YhxoBH4RK9yDWsgrCym7k=; b=v2pcuhq/5N6Ivd9Hep8lDV65tK6BIEsUREB+qBhY3wYiCcKL/3Y0ROUhN9lOhxfQw4 /gkRq1p3wEDrebh5cqgjz0oP3xzrKmIha5LwYx6/7ivzzP0btqgFIu3dbKfG1mBBpGKV 4UU9GEgapIDkStpRcl50DBq2LnW0mPBqjc+nGOZXcuZRLMb5zoMtZBFWSifD7xYPBePJ jJZkWJ6QCjW4VsJLneS00dICYUaICE4QV64hZu4EcGy5EgoIPqZHlHbYa3+QLXZXe/a2 mz33oLduQZInUzlgtay93mbH1ErNeoR+huyIIMoKPITvpb8RNyxzjGA5S+mBZLzwACIc FzBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z0oTrunMpZOqlOX2ru72d6YhxoBH4RK9yDWsgrCym7k=; b=gh6rNWHi0xaYBggUqGlidUBE5DkltAbU+KP66geOfKsXz4EVDlLNEUlO+oaydIz7vy DOD6mc25qqbc7HNr7OcZZ1ew/ORoOMjSQGSznrvIUnmNIRhsgS8x91jZoeaWYtznQu+9 zmHeOXD5C4Vv4hsHxg1Rx77fJZQc1/PE6rV81k2JeZsb1iu3S0Gnc1gHNrmg1CC6m7lK WE6vMwUC7zoDBSXRNnx19Ar2Vb3CI6xsqyOmx8Cto+/q1/OygpHVbrDc/Tv9k1MW9Al2 u4SPfbXK2ZGa2R2JSPLEwFCCLwoRzn/NGYWWQ/SBhPIL8y5gQRrKQHrtnkYYjYNeRjGv rkkw== X-Gm-Message-State: AMCzsaXEBVsV5ceWPbSkQaN4LrJf774JFUoth3bG3ZL+4w56Nzgewznl 7TXqYGpcPPGbr0/XueWxs9o7h4yJc1A= X-Google-Smtp-Source: ABhQp+Rfj8KlRheDv4RacIVN651qJPeHPgCHuRdcAEENgeurFXxZ0vkGZZ4ure2gwbUveNXAxXlolA== X-Received: by 10.25.145.88 with SMTP id y24mr7335919lfj.5.1509066879375; Thu, 26 Oct 2017 18:14:39 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:51 +0200 Message-Id: <1509066832-5285-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 09/10] Marvell/Drivers: XenonDxe: Allow overriding base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Some SdMmc host controllers are run by clocks with different frequency than it is reflected in Capabilities Register 1. Because the bitfield is only 8 bits wide, a maximum value that could be obtained from hardware is 255(MHz). In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient to be used for setting the clock speed in SdMmcHcClockSupply function. This patch adds new UINT32 array ('BaseClkFreq[]') to SD_MMC_HC_PRIVATE_DATA structure for specifying the input clock speed for each slot of the host controller. All routines that are used for clock configuration are updated accordingly. Thanks to above the Xenon host controller driver could be modified to configure clock speed relatively to actual 400MHz input. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c | 4 ++-- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c | 4 ++-- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c | 13 ++++++++---- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h | 6 ++++++ Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 22 ++++++++++---= ------- Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h | 12 ++++++----- 6 files changed, 37 insertions(+), 24 deletions(-) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c b/Platfor= m/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c index 4d4833f..530a01c 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/EmmcDevice.c @@ -705,7 +705,7 @@ EmmcSwitchClockFreq ( // // Convert the clock freq unit from MHz to KHz. // - Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->C= apability[Slot]); + Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->B= aseClkFreq[Slot]); =20 return Status; } @@ -1007,7 +1007,7 @@ EmmcSetBusMode ( return Status; } =20 - ASSERT (Private->Capability[Slot].BaseClkFreq !=3D 0); + ASSERT (Private->BaseClkFreq[Slot] !=3D 0); // // Check if the Host Controller support 8bits bus width. // diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c b/Platform/= Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c index 9122848..ea7eed7 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdDevice.c @@ -972,7 +972,7 @@ SdCardSetBusMode ( return Status; } =20 - Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capabilit= y); + Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->B= aseClkFreq[Slot]); if (EFI_ERROR (Status)) { return Status; } @@ -1144,7 +1144,7 @@ SdCardIdentification ( goto Error; } =20 - SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]); + SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]); =20 gBS->Stall (1000); =20 diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c b/Plat= form/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c index 981eab5..10e15c5 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.c @@ -291,7 +291,10 @@ SdMmcPciHcEnumerateDevice ( // // Reinitialize slot and restart identification process for the ne= w attached device // - Status =3D SdMmcHcInitHost (Private->PciIo, Slot, Private->Capabil= ity[Slot]); + Status =3D SdMmcHcInitHost (Private->PciIo, + Slot, + Private->Capability[Slot], + Private->BaseClkFreq[Slot]); if (EFI_ERROR (Status)) { continue; } @@ -617,9 +620,11 @@ SdMmcPciHcDriverBindingStart ( Private->Capability[Slot].Sdr50 =3D 0; Private->Capability[Slot].BusWidth8 =3D 0; =20 - if (Private->Capability[Slot].BaseClkFreq =3D=3D 0) { - Private->Capability[Slot].BaseClkFreq =3D 0xff; - } + // + // Override inappropriate base clock frequency from Capabilities Registe= r 1. + // Actual clock speed of Xenon controller is 400MHz. + // + Private->BaseClkFreq[Slot] =3D XENON_MMC_MAX_CLK / 1000 / 1000; =20 DumpCapabilityReg (Slot, &Private->Capability[Slot]); =20 diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h b/Plat= form/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h index 6a2a279..067b9ac 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHcDxe.h @@ -115,6 +115,12 @@ typedef struct { UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT]; =20 UINT32 ControllerVersion; + + // + // Some controllers may require to override base clock frequency + // value stored in Capabilities Register 1. + // + UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT]; } SD_MMC_HC_PRIVATE_DATA; =20 #define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T') diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platfo= rm/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c index ccbf355..706618d 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c @@ -678,7 +678,7 @@ SdMmcHcStopClock ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] ClockFreq The max clock frequency to be set. The unit is= KHz. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -689,11 +689,10 @@ SdMmcHcClockSupply ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, IN UINT64 ClockFreq, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ) { EFI_STATUS Status; - UINT32 BaseClkFreq; UINT32 SettingFreq; UINT32 Divisor; UINT32 Remainder; @@ -703,9 +702,8 @@ SdMmcHcClockSupply ( // // Calculate a divisor for SD clock frequency // - ASSERT (Capability.BaseClkFreq !=3D 0); + ASSERT (BaseClkFreq !=3D 0); =20 - BaseClkFreq =3D Capability.BaseClkFreq; if (ClockFreq =3D=3D 0) { return EFI_INVALID_PARAMETER; } @@ -896,7 +894,7 @@ SdMmcHcSetBusWidth ( =20 @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -906,7 +904,7 @@ EFI_STATUS SdMmcHcInitClockFreq ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClkFreq ) { EFI_STATUS Status; @@ -915,7 +913,7 @@ SdMmcHcInitClockFreq ( // // Calculate a divisor for SD clock frequency // - if (Capability.BaseClkFreq =3D=3D 0) { + if (BaseClkFreq =3D=3D 0) { // // Don't support get Base Clock Frequency information via another meth= od // @@ -925,7 +923,7 @@ SdMmcHcInitClockFreq ( // Supply 400KHz clock frequency at initialization phase. // InitFreq =3D 400; - Status =3D SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability); + Status =3D SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq); return Status; } =20 @@ -1024,6 +1022,7 @@ SdMmcHcInitTimeoutCtrl ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The host controller is initialized successfull= y. @retval Others The host controller isn't initialized successf= ully. @@ -1033,12 +1032,13 @@ EFI_STATUS SdMmcHcInitHost ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN SD_MMC_HC_SLOT_CAP Capability, + IN UINT32 BaseClkFreq ) { EFI_STATUS Status; =20 - Status =3D SdMmcHcInitClockFreq (PciIo, Slot, Capability); + Status =3D SdMmcHcInitClockFreq (PciIo, Slot, BaseClkFreq); if (EFI_ERROR (Status)) { return Status; } diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h b/Platfo= rm/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h index fb62758..a4ec4fe 100644 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.h @@ -414,7 +414,7 @@ SdMmcHcStopClock ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] ClockFreq The max clock frequency to be set. The unit is= KHz. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -425,7 +425,7 @@ SdMmcHcClockSupply ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, IN UINT64 ClockFreq, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClockFreq ); =20 /** @@ -473,7 +473,7 @@ SdMmcHcSetBusWidth ( =20 @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The clock is supplied successfully. @retval Others The clock isn't supplied successfully. @@ -483,7 +483,7 @@ EFI_STATUS SdMmcHcInitClockFreq ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN UINT32 BaseClockFreq ); =20 /** @@ -531,6 +531,7 @@ SdMmcHcInitTimeoutCtrl ( @param[in] PciIo The PCI IO protocol instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] Capability The capability of the slot. + @param[in] BaseClkFreq The base clock frequency of host controller in= MHz. =20 @retval EFI_SUCCESS The host controller is initialized successfull= y. @retval Others The host controller isn't initialized successf= ully. @@ -540,7 +541,8 @@ EFI_STATUS SdMmcHcInitHost ( IN EFI_PCI_IO_PROTOCOL *PciIo, IN UINT8 Slot, - IN SD_MMC_HC_SLOT_CAP Capability + IN SD_MMC_HC_SLOT_CAP Capability, + IN UINT32 BaseClockFreq ); =20 #endif --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Wed May 1 01:12:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1509066900212820.2220482167845; Thu, 26 Oct 2017 18:15:00 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4E53A2034A892; Thu, 26 Oct 2017 18:10:59 -0700 (PDT) Received: from mail-lf0-x241.google.com (mail-lf0-x241.google.com [IPv6:2a00:1450:4010:c07::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C2B452034A88D for ; Thu, 26 Oct 2017 18:10:55 -0700 (PDT) Received: by mail-lf0-x241.google.com with SMTP id 90so5655294lfs.13 for ; Thu, 26 Oct 2017 18:14:42 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m9sm1675702ljb.61.2017.10.26.18.14.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 26 Oct 2017 18:14:39 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::241; helo=mail-lf0-x241.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A7zc2/u0Y4h9ChbtWDS94GyHyj90ZIKnWA4DhvOjBBw=; b=fHIs1tvnEYx2oqp2qnyYjc276ulStxfJuku7usuri1fHCGCzZ/YnQSA6xFTS1ZBxf+ TnL8qNrhxk/7Lj8TvduAwzBE6u9fnKd4jNlE4+6yFb8msn1AyjEj1+yQ2iHPTMDBQ8Jf bnWVFyg8Gnf4ttIx5rHPWT98UFV5qiQ3N0dTVAbR4CWL+7D0rE1gkWXRkJlhOsSytBl9 VUhfv8OmH0+OV05mMe5iyiL70krywQPjg6ZNE524r5c5f9zPVSNGtBuyAweHS/oOOayn x8mOi3Ajuue2vCpjohjVXBLKJWfQFNvt6KCM9eWFiAQboaRTLzm+lVxbbYNoScz4eSmS w6AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A7zc2/u0Y4h9ChbtWDS94GyHyj90ZIKnWA4DhvOjBBw=; b=BORh191uphbXM/FA/+ostkdGtTO05i+jttWghHnBPwXQLmcu+PtDdzkGJVl0ejH7sE bHlyUiHbNn0Heux1Y6YKsuTcYO7wtZgM0D9AX40aR6nfv8kybK9GFgRZVWzyugYqlD0d q5gqiU8jEdfCUSFZewADPwEQHPw9vgjkD2XP4sSgrrnB2493aS+N4rkCDIgrONSi+yms hfXe42lRSECwPpwc+VgiYFkp5NcBbiorUq8WOzGPE4FGISSzZKJlDbRAJnKKENrE0RtR OW4lzpUM41HO1w3zMU0G3XWqpvOt/j28teAwQhFvn4qv5pjHzNgIkWi1xsUufRmUhxJ4 x6gQ== X-Gm-Message-State: AMCzsaVdw0LWXHPB/PrV8w7sVbmnCsp/UOkhm2sntG41u8a1W46btwas n9zkZlW5rImKxhlInoMnIKzNp0uBqAc= X-Google-Smtp-Source: ABhQp+QpU+/gSSio0T4m+rBzp5R5tg/uaskQ/IQ4EVXZadRROghhY2j+NaAOE9U8r331Zed6diwElA== X-Received: by 10.25.18.169 with SMTP id 41mr7111662lfs.166.1509066880680; Thu, 26 Oct 2017 18:14:40 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 27 Oct 2017 03:13:52 +0200 Message-Id: <1509066832-5285-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509066832-5285-1-git-send-email-mw@semihalf.com> References: <1509066832-5285-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 10/10] Marvell/Drivers: XenonDxe: Do not modify FIFO default values X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Changing controller's FIFO default values is not necessary and possibly can cause instabilities, when using some devices. Disable the modification and rely on initial settings. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c b/Platfor= m/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c index 31f207e..6bbe5bc 100755 --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.c @@ -44,20 +44,6 @@ XenonReadVersion ( SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SD_MMC_HC_CTRL_VER, TRUE, SDHC_REG_S= IZE_2B, ControllerVersion); } =20 -STATIC -VOID -XenonSetFifo ( - IN EFI_PCI_IO_PROTOCOL *PciIo - ) -{ - UINTN Data; - - // Set FIFO_RTC, FIFO_WTC, FIFO_CS and FIFO_PDLVMC - Data =3D SDHC_SLOT_FIFO_DEFAULT_CONFIG; - - SdMmcHcRwMmio (PciIo, SD_BAR_INDEX, SDHC_SLOT_FIFO_CTRL, FALSE, SDHC_REG= _SIZE_4B, &Data); -} - // Auto Clock Gating STATIC VOID @@ -634,8 +620,6 @@ XenonInit ( // Read XENON version XenonReadVersion (PciIo, &Private->ControllerVersion); =20 - XenonSetFifo (PciIo); - // Disable auto clock generator XenonSetAcg (PciIo, FALSE); =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel