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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22e; helo=mail-lf0-x22e.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=T00heUOAzs8t00R4Ro6g7LJkk1jxXQc3DWVY0TaYgRs=; b=Uv3jhBccyItrpkwu2vfkauJIfoQJzsgmdUC0PwhGBDDWy/rxbYy2gDtiA1UzW1iFQf WTFZnNWuvPyDFK3TT+QDnlrVBxKkrEOUALuf+Rx6D18wWj9/ZSVS1n8OX2uAvLvtcADA xvQIkgjazYq3v/L2xco55ny8voKAzsTOB23NlkDoCwXZS5lSsJarxXZgp9gdlG0aKJ2K d+/UfPBiMVkg4X8l3rohrin81lMav42BGXwgGAQNW2kPvHkvBU0Jblk6wNT8CUh4R5n9 fl+470Z9oScxaVx+D1CtRwsw3+6v9T4kFU6D+pYf8ef6p7DZTLMmGLf9+T9gyxK/YAcr wdjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=T00heUOAzs8t00R4Ro6g7LJkk1jxXQc3DWVY0TaYgRs=; b=gTf7sqjcvORXl7zl89gjAndTs52TR4KOGae7kVSXRJgIS+TvXkEoSIx4tQZXI5YMGo PpYg48zWslojmX8s2GkZC/rUgyZkUGCHOceUF4Rs7tVAfvqfNJKg2vI+18WeI5VhFkqQ yCTyrRH7pXq80ZGIT89Cx1AoEV83EEbF0rYpWNxD6m+Lkxf3gJlFYJVIG4PcZYuBciXr 5SNROPHqYitBlvuiJMdoAP6ON+Z/aSsT8K4qode3C0f4G9ZZBDaGRstPllLxUTZ35l1q vWf/tDlKheOcLOuuV84ysAW2gonQQ+7oPL6FkpeaEvw6l6TPUmNNKE9bCqKqVGd7xffW 0oiw== X-Gm-Message-State: AMCzsaVbp+7BP0uVDBLAJlaK2xcj9MXmNb7GKMDwYBe47J4GHzjxPJ+N F8An3IxFES3Zk0Yhmh/rCuQkvaSlgMk= X-Google-Smtp-Source: ABhQp+RwcOSjXiR6LATQbJqe3jPMB9nRpzkaAKPiqxNcCnIaTMkYigUKp90xE9sCI6CViV1iE3KcWg== X-Received: by 10.25.37.202 with SMTP id l193mr18871lfl.78.1507736472931; Wed, 11 Oct 2017 08:41:12 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:42 +0200 Message-Id: <1507736449-6073-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 1/8] Marvell/Armada: Implement EFI_RNG_PROTOCOL driver for EIP76 TRNG X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Add an implementation of EFI_RNG_PROTOCOL so that the OS loader has access to entropy for KASLR and other purposes (i.e., seeding the OS's entropy pool very early on). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Armada.dsc.inc | = 4 + Platform/Marvell/Armada/Armada70x0.fdf | = 1 + Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c | 25= 4 ++++++++++++++++++++ Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf | 4= 7 ++++ Platform/Marvell/Marvell.dec | = 3 + 5 files changed, 309 insertions(+) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 1aa485c..ec24d76 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -364,6 +364,9 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 gArmTokenSpaceGuid.PcdArmScr|0x531 =20 + # TRNG + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 + ##########################################################################= ###### # # Components Section - list of all EDK II Modules needed by this Platform @@ -400,6 +403,7 @@ Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf Platform/Marvell/Drivers/Spi/MvSpiDxe.inf Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf + Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf =20 # Network support MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 933c3ed..a94a9ff 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -113,6 +113,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c INF Platform/Marvell/Drivers/I2c/Devices/MvEeprom/MvEeprom.inf INF Platform/Marvell/Drivers/Spi/MvSpiDxe.inf INF Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf + INF Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf =20 # Network support INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0Rng= Dxe.c b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c new file mode 100644 index 0000000..dca6dcc --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.c @@ -0,0 +1,254 @@ +/** @file + + This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TR= NG + + Copyright (C) 2017, Linaro Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include +#include +#include +#include + +#include + +#define TRNG_OUTPUT_REG mTrngBaseAddress +#define TRNG_OUTPUT_SIZE 0x10 + +#define TRNG_STATUS_REG (mTrngBaseAddress + 0x10) +#define TRNG_STATUS_READY BIT0 + +#define TRNG_INTACK_REG (mTrngBaseAddress + 0x10) +#define TRNG_INTACK_READY BIT0 + +#define TRNG_CONTROL_REG (mTrngBaseAddress + 0x14) +#define TRNG_CONTROL_REG_ENABLE BIT10 + +#define TRNG_CONFIG_REG (mTrngBaseAddress + 0x18) +#define __MIN_REFILL_SHIFT 0 +#define __MAX_REFILL_SHIFT 16 +#define TRNG_CONFIG_MIN_REFILL_CYCLES (0x05 << __MIN_REFILL_SHIF= T) +#define TRNG_CONFIG_MAX_REFILL_CYCLES (0x22 << __MAX_REFILL_SHIF= T) + +#define TRNG_FRODETUNE_REG (mTrngBaseAddress + 0x24) +#define TRNG_FRODETUNE_MASK 0x0 + +#define TRNG_FROENABLE_REG (mTrngBaseAddress + 0x20) +#define TRNG_FROENABLE_MASK 0xffffff + +#define TRNG_MAX_RETRIES 20 + +STATIC EFI_PHYSICAL_ADDRESS mTrngBaseAddress; + +/** + Returns information about the random number generation implementation. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL + instance. + @param[in,out] RNGAlgorithmListSize On input, the size in bytes of + RNGAlgorithmList. + On output with a return code of + EFI_SUCCESS, the size in bytes of the + data returned in RNGAlgorithmList. On + output with a return code of + EFI_BUFFER_TOO_SMALL, the size of + RNGAlgorithmList required to obtain = the + list. + @param[out] RNGAlgorithmList A caller-allocated memory buffer fil= led + by the driver with one EFI_RNG_ALGOR= ITHM + element for each supported RNG algor= ithm. + The list must not change across mult= iple + calls to the same driver. The first + algorithm in the list is the default + algorithm for the driver. + + @retval EFI_SUCCESS The RNG algorithm list was returned + successfully. + @retval EFI_UNSUPPORTED The services is not supported by this + driver. + @retval EFI_DEVICE_ERROR The list of algorithms could not be + retrieved due to a hardware or firmw= are + error. + @retval EFI_INVALID_PARAMETER One or more of the parameters are + incorrect. + @retval EFI_BUFFER_TOO_SMALL The buffer RNGAlgorithmList is too s= mall + to hold the result. + +**/ +STATIC +EFI_STATUS +EFIAPI +Armada70x0RngGetInfo ( + IN EFI_RNG_PROTOCOL *This, + IN OUT UINTN *RNGAlgorithmListSize, + OUT EFI_RNG_ALGORITHM *RNGAlgorithmList + ) +{ + if (This =3D=3D NULL || RNGAlgorithmListSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (*RNGAlgorithmListSize < sizeof (EFI_RNG_ALGORITHM)) { + *RNGAlgorithmListSize =3D sizeof (EFI_RNG_ALGORITHM); + return EFI_BUFFER_TOO_SMALL; + } + + if (RNGAlgorithmList =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *RNGAlgorithmListSize =3D sizeof (EFI_RNG_ALGORITHM); + CopyGuid (RNGAlgorithmList, &gEfiRngAlgorithmRaw); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +GetTrngData ( + IN UINTN Length, + OUT UINT8 *Bits + ) +{ + UINTN Tries; + UINT32 Buf[TRNG_OUTPUT_SIZE / sizeof (UINT32)]; + UINTN Index; + + for (Tries =3D 0; Tries < TRNG_MAX_RETRIES; Tries++) { + if (MmioRead32 (TRNG_STATUS_REG) & TRNG_STATUS_READY) { + for (Index =3D 0; Index < ARRAY_SIZE (Buf); Index++) { + Buf[Index] =3D MmioRead32 (TRNG_OUTPUT_REG + Index * sizeof (UINT3= 2)); + } + CopyMem (Bits, Buf, Length); + MmioWrite32 (TRNG_INTACK_REG, TRNG_INTACK_READY); + + return EFI_SUCCESS; + } + gBS->Stall (10); + } + return EFI_DEVICE_ERROR; +} + +/** + Produces and returns an RNG value using either the default or specified = RNG + algorithm. + + @param[in] This A pointer to the EFI_RNG_PROTOCOL + instance. + @param[in] RNGAlgorithm A pointer to the EFI_RNG_ALGORITHM t= hat + identifies the RNG algorithm to use.= May + be NULL in which case the function w= ill + use its default RNG algorithm. + @param[in] RNGValueLength The length in bytes of the memory bu= ffer + pointed to by RNGValue. The driver s= hall + return exactly this numbers of bytes. + @param[out] RNGValue A caller-allocated memory buffer fil= led + by the driver with the resulting RNG + value. + + @retval EFI_SUCCESS The RNG value was returned successfu= lly. + @retval EFI_UNSUPPORTED The algorithm specified by RNGAlgori= thm + is not supported by this driver. + @retval EFI_DEVICE_ERROR An RNG value could not be retrieved = due + to a hardware or firmware error. + @retval EFI_NOT_READY There is not enough random data avai= lable + to satisfy the length requested by + RNGValueLength. + @retval EFI_INVALID_PARAMETER RNGValue is NULL or RNGValueLength is + zero. + +**/ +STATIC +EFI_STATUS +EFIAPI +Armada70x0RngGetRNG ( + IN EFI_RNG_PROTOCOL *This, + IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL + IN UINTN RNGValueLength, + OUT UINT8 *RNGValue + ) +{ + UINTN Length; + EFI_STATUS Status; + + if (This =3D=3D NULL || RNGValueLength =3D=3D 0 || RNGValue =3D=3D NULL)= { + return EFI_INVALID_PARAMETER; + } + + // + // We only support the raw algorithm, so reject requests for anything el= se + // + if (RNGAlgorithm !=3D NULL && + !CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw)) { + return EFI_UNSUPPORTED; + } + + do { + Length =3D MIN (RNGValueLength, TRNG_OUTPUT_SIZE); + Status =3D GetTrngData (Length, RNGValue); + if (EFI_ERROR (Status)) { + return Status; + } + + RNGValue +=3D Length; + RNGValueLength -=3D Length; + } while (RNGValueLength > 0); + + return EFI_SUCCESS; +} + +STATIC EFI_RNG_PROTOCOL mArmada70x0RngProtocol =3D { + Armada70x0RngGetInfo, + Armada70x0RngGetRNG +}; + +// +// Entry point of this driver. +// +EFI_STATUS +EFIAPI +Armada70x0RngDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mTrngBaseAddress =3D PcdGet64 (PcdEip76TrngBaseAddress); + + // + // Disable the TRNG before updating its configuration + // + MmioAnd32 (TRNG_CONTROL_REG, ~TRNG_CONTROL_REG_ENABLE); + + // + // Configure the internal conditioning parameters of the TRNG + // + MmioWrite32 (TRNG_CONFIG_REG, TRNG_CONFIG_MIN_REFILL_CYCLES | + TRNG_CONFIG_MAX_REFILL_CYCLES); + + // + // Configure the FROs + // + MmioWrite32 (TRNG_FRODETUNE_REG, TRNG_FRODETUNE_MASK); + MmioWrite32 (TRNG_FROENABLE_REG, TRNG_FROENABLE_MASK); + + // + // Enable the TRNG + // + MmioOr32 (TRNG_CONTROL_REG, TRNG_CONTROL_REG_ENABLE); + + return SystemTable->BootServices->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiRngProtocolGuid, + &mArmada70x0RngProtocol, + NULL + ); +} diff --git a/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0Rng= Dxe.inf b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe= .inf new file mode 100644 index 0000000..189ffc5 --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/Armada70x0RngDxe/Armada70x0RngDxe.inf @@ -0,0 +1,47 @@ +## @file +# This driver produces an EFI_RNG_PROTOCOL instance for the Armada 70x0 TR= NG +# +# Copyright (C) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials are licensed and made availa= ble +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WI= THOUT +# WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D Armada70x0RngDxe + FILE_GUID =3D dd87096a-cae5-4328-bec1-2ddb755f2e08 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D Armada70x0RngDxeEntryPoint + +[Sources] + Armada70x0RngDxe.c + +[Packages] + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + BaseMemoryLib + IoLib + PcdLib + UefiDriverEntryPoint + +[Pcd] + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress + +[Protocols] + gEfiRngProtocolGuid ## PRODUCES + +[Guids] + gEfiRngAlgorithmRaw + +[Depex] + TRUE diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index e7d7c2c..78f5e53 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -195,6 +195,9 @@ #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 =20 +#TRNG + gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 + [Protocols] gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 18:18:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150773648385377.68969838798125; Wed, 11 Oct 2017 08:41:23 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 046A121F7D4E8; Wed, 11 Oct 2017 08:37:49 -0700 (PDT) Received: from mail-lf0-x230.google.com (mail-lf0-x230.google.com [IPv6:2a00:1450:4010:c07::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 32EE621FC7499 for ; Wed, 11 Oct 2017 08:37:47 -0700 (PDT) Received: by mail-lf0-x230.google.com with SMTP id 90so2554581lfs.13 for ; Wed, 11 Oct 2017 08:41:16 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:13 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::230; helo=mail-lf0-x230.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V/2M2b6W+hG3st6Uu5mKZVAlzB/bTaiqYrDMvw3ma2g=; b=zncG20QV2ZfGvushy3BmxKGCZxnZJBspgUarUsIMU0++Egsj4qIzWyLgv4e1py7bLH JW6n2RZWUiSKrB/3+WjyDCTK3uCaL8aoh51UaOaqQmMppDmNNqb6SOWEz0EFhvMyL9Dq frpKLbrWcoQaQYKHUFSJLSF6a4TEyirwvF8HEfynO2tPaD1EsUkqWTr6ZQFxBvgWsjEm WCrpt47yb4pj6UFFVdX3+jCjHukHceiJ4fCq4jLQyPrWRl+Cq5b+9MRA1evg8HXbYzCV DgzxHYGo0UrDDbjSQ+2O6EKeiV3UU0yq2ARVYkb8aqd6+WmGgZGn2JBhhh8kfcwCSgPC mqbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V/2M2b6W+hG3st6Uu5mKZVAlzB/bTaiqYrDMvw3ma2g=; b=qj1VsqQkLXk9H74NFtpnHSPQXXzqkMMpUUQz0LtC6cdN5NDQsbpW8IfVK/hA+9RU9p 2ZqEOR1RX4nx8y0rAula0YaHtlq8aLiUuNagqZPJbH7BeYd30acaCGYNeMy59mTeQ0RD Cx0gPcdWnjd7DgGkl2P73qrTwliwJl0YyNNGRTRks3uFCtFnR95NQmdkzqASgm58Sa7t g3YekLQYtOxoxtflPCdeGm1B+1q1ESCxSAz+S2c02RC8Fy0pxvqbMpakPaGcvmMYr4Yn DnL8cR71y/vvgRfvKi6ECxY9lcRlld7Ybue0AfKXh76o4xPCIU9gv8/49lDLAAMVx9bY sawg== X-Gm-Message-State: AMCzsaVTTjM6LiICuQ8vrnx99IQzxFp0dmAR42ZfM3iRpCcmIoDBLIX2 rzboyEM/BW2fVIPC0CRVgYL77/bAq6k= X-Google-Smtp-Source: ABhQp+RCMuiTnl8Rh2gw93KLxBmXYjKkzVR+RYEP1CxrRvMtReXfxtCNx2EAq5DXtdNDG23tmD042w== X-Received: by 10.25.18.169 with SMTP id 41mr16515lfs.166.1507736474770; Wed, 11 Oct 2017 08:41:14 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:43 +0200 Message-Id: <1507736449-6073-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/8] Marvell/Armada: Increase preallocated memory region size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel In order to prevent fragmentation of the UEFI memory map, increase the sizes of the preallocated regions. Note that this does not increase the memory footprint of UEFI, it just modifies it allocation policy to keep similar region types together. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index ec24d76..56d8941 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -341,10 +341,10 @@ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 - gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|1000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|1000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|2000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|35000 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 =20 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 18:18:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507736487731921.663370139193; Wed, 11 Oct 2017 08:41:27 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 41C6921F7D4E7; Wed, 11 Oct 2017 08:37:51 -0700 (PDT) Received: from mail-lf0-x22c.google.com (mail-lf0-x22c.google.com [IPv6:2a00:1450:4010:c07::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7650F21F7D4E7 for ; Wed, 11 Oct 2017 08:37:48 -0700 (PDT) Received: by mail-lf0-x22c.google.com with SMTP id n69so2561176lfn.2 for ; Wed, 11 Oct 2017 08:41:17 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:15 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22c; helo=mail-lf0-x22c.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dwv/Fr4N35nZLSf70S50ynqOxcSGgkWPv2OAlKpRD2Y=; b=ntVSscafm3410DgLHugvy96GiNc8Hvk5XK03bkEwFH/EzhlCBygQbCiOnNF6qh2/jC ervaDpVK1e4HI/hR91PW4o+2TFhRiEX24vLhu/0J/GZKZll2+6sk8UGVN1G1tZmamzd/ uz6Ve8jcR9COSvl95l0U5bg18Lp7SmT0LTQHkcnZXM+oCplqaRlwns2f0ZuT6njkuDes EfFzxHbTPfJw8E/p2qEniV3XLCz0XD9MGfSTyiQ3I0z5Yr7fybYkvzieHifPx7q+tvc0 R2aI10R4rdLoEb/0VJtSm/ZqO+O8jldHWrPw6gAxHtRGEqO/kO3db0fydIaOCRgQwEX7 MeGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dwv/Fr4N35nZLSf70S50ynqOxcSGgkWPv2OAlKpRD2Y=; b=QmikUH/lRSlt9aOwNLg3rtqeZwFZH4bi3KJIf5M1HiqGD1OWf1vwzfUKxGZRChiqPn h3/a0CMiZ+ee3YK+RZuEMUIJwYNnWnuULx8eSreEd7rSoFODh4PMJLJb4KALRmw90e9z Spt/1ihJH7h+xUWOyJHv1c3TJNgWonwbFdRxBF9cwNZQx/2znPT4+qodcyEX0QjtFWjr BljzBLENHeQTDc/TL6Wadx+A6b8s1Iqz/jm1GOkHk77XDN21G18GGW5cPecw0G0xhdFX UQaNMZXH2ow7eYNDpfdn8LcjzaxFXVIW3XN9I30NA3ntxTLadx/CYt6skBrf9oQdOsDX z5fg== X-Gm-Message-State: AMCzsaXYhWpvSbKb41Og4xlwcaxAetQ01EMiqrA+0j0NFug2CGrzmXOx 1afH3GyKyJpAVlSLGmOCXzU9EsnCaYw= X-Google-Smtp-Source: ABhQp+SrgtrPGzE9x2VNjlZstgkxKEsXFJiZl8bp26U04oYfhI3dx1FnuAG9YcFXWnAptzKeLVLqfg== X-Received: by 10.25.222.202 with SMTP id i71mr9874lfl.177.1507736476044; Wed, 11 Oct 2017 08:41:16 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:44 +0200 Message-Id: <1507736449-6073-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 3/8] Marvell/Armada: Remove custom reset library residues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" When switching to generic PSCI reset library, obsolete parts of previous custom reset library (PCDs, documentation) remained. Remove them. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada70x0.dsc | 4 ---- Platform/Marvell/Marvell.dec | 4 ---- Silicon/Marvell/Documentation/PortingGuide.txt | 9 --------- 3 files changed, 17 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 430803c..946c93e 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -138,9 +138,5 @@ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } =20 - #ResetLib - gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084 - gMarvellTokenSpaceGuid.PcdResetRegMask|0x1 - #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x1 } diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 78f5e53..434d6cb 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -188,10 +188,6 @@ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0 }|VOID*|0x3000034 gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x0 }|VOID*|0x3000035 =20 -#ResetLib - gMarvellTokenSpaceGuid.PcdResetRegAddress|0|UINT64|0x40000050 - gMarvellTokenSpaceGuid.PcdResetRegMask|0|UINT32|0x4000051 - #RTC gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0 }|VOID*|0x40000052 =20 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 66ec918..cbe3bed 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -383,15 +383,6 @@ Set pin 6 and 7 to 0xa function: gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } =20 =20 -MarvellResetSystemLib configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -This simple library allows to mask given bits in given reg at UEFI 'reset' -command call. These variables are configurable through PCDs: - - - gMarvellTokenSpaceGuid.PcdResetRegAddress - - gMarvellTokenSpaceGuid.PcdResetRegMask - - Ramdisk configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D There is one PCD available for Ramdisk configuration --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 18:18:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507736491285699.6946995689818; Wed, 11 Oct 2017 08:41:31 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8008821F7D4EE; Wed, 11 Oct 2017 08:37:51 -0700 (PDT) Received: from mail-lf0-x22f.google.com (mail-lf0-x22f.google.com [IPv6:2a00:1450:4010:c07::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AF09421F7D4E6 for ; Wed, 11 Oct 2017 08:37:49 -0700 (PDT) Received: by mail-lf0-x22f.google.com with SMTP id a16so2569604lfk.0 for ; Wed, 11 Oct 2017 08:41:19 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:16 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22f; helo=mail-lf0-x22f.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tpaYvPEHCOnkXubX5p8FMb1RSp12TrG2brLFUhyII3M=; b=cCTueOPlAiQ0FtuOBTdgIoje+DxlfOmiUMNka0BCWaoiHwPrG7gMgbudAWke7/Mjud fkvZ1lApLr2lL6mMdvDVYWVHleGq/YR/ZQFgnVhy+04uTC3Ei4sAImW5JdMF1MNXuFBP vFsDqBEW/wlYziVWlQY18l9+XaKqwdhjwb4VeLdle8WAQYz593MrfkrHu3RBDH60G7Yv rofABL0A3y21rWV+T4R3yrTrkA5FRRiRUaWCx0GyG60ZaNnws1kEBplu1vOEv0Hmc2Eo hNBsUap2fVMY6zCW5PzvcdOjHyHQzIp0jmb2h521MqkTDZ6hkODEF5Do4rRC+4S8uX8n Tw0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tpaYvPEHCOnkXubX5p8FMb1RSp12TrG2brLFUhyII3M=; b=hRGefjUEgm4fU17ht7OnK1WvbjP2POKupeMgW0u0uHxBZHCipA720MZx2VVeeoN1Uk WGEIkT1jyxegbOJhkhntRp8mcvHqMlly8zCZq+i9XWD9kTQvkLBAtoP6Em6cmH/8GHJ2 VX3WcQkcmU+WmuvTbnE9XG+BxU1eHvcE0YGDYKDo+cbBRoeMsMgVBCB8ktewoM08ZDnH NGCXmArRYHtZo9VUSXnamiOuaIOr1y47uItj7yACdfnFi+clUfj/pRIXHCeMLCqEIVQD LW/qDRqY5kvcBVsUOEzYh0+f2yH+qiX/OSwLb8YlDHYyC+KdEIvMeG5aC0Bn4H/YqE/I 5M5A== X-Gm-Message-State: AMCzsaV6z7H5Dqk3O9LrzuLVmWDUwW8/PlwLhnIdUBFvAuUE3xBHPX0S RWPH/EttaMkiFIQyl5D6vciw4dVddiQ= X-Google-Smtp-Source: AOwi7QBtQDiYxlgGudlD4TIdGh8GIZfRU4H1M9a0Ek7WHhRi+nPFI+6YJeXNUAuMENAlfce2MdD/tA== X-Received: by 10.46.97.1 with SMTP id v1mr21129ljb.176.1507736477282; Wed, 11 Oct 2017 08:41:17 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:45 +0200 Message-Id: <1507736449-6073-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 4/8] Marvell/Armada: Add support from DRAM remapping X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The Armada 70x0/80x0 DRAM controller allows a single window of DRAM to be remapped to another location in the physical address space. This allows us to free up some memory in the 32-bit addressable region for peripheral MMIO and PCI MMIO32 and CONFIG spaces. This patch adjusts memory blocks to the configuration done in ATF. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S = | 15 +++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf = | 3 + Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c = | 60 ++++++++++++++++---- Platform/Marvell/Marvell.dec = | 13 +++++ 4 files changed, 81 insertions(+), 10 deletions(-) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatf= ormHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlat= formHelper.S index 72f8cfc..c5be1a9 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelp= er.S +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelp= er.S @@ -17,6 +17,21 @@ =20 ASM_FUNC(ArmPlatformPeiBootAction) mov x29, xzr + + .if FixedPcdGet64 (PcdSystemMemoryBase) !=3D 0 + .err PcdSystemMemoryBase should be 0x0 on this platform! + .endif + + .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapT= arget) + // + // Use the low range for UEFI itself. The remaining memory will be map= ped + // and added to the GCD map later. + // + adr x0, mSystemMemoryEnd + MOV64 (x1, FixedPcdGet32 (PcdDramRemapTarget) - 1) + str x1, [x0] + .endif + ret =20 //UINTN diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.in= f b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 2e198c3..838a670 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -67,5 +67,8 @@ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask gArmTokenSpaceGuid.PcdArmPrimaryCore =20 + gMarvellTokenSpaceGuid.PcdDramRemapSize + gMarvellTokenSpaceGuid.PcdDramRemapTarget + [Ppis] gArmMpCoreInfoPpiGuid diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem= .c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c index 74c9956..2cb2e15 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include #include =20 // The total number of descriptors, including the final "end-of-table" des= criptor. @@ -44,6 +45,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_NONSEC= URE_WRITE_BACK #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACH= ED_UNBUFFERED =20 +STATIC ARM_MEMORY_REGION_DESCRIPTOR VirtualMemoryTable[MAX_VIRTUAL_MEMORY_= MAP_DESCRIPTORS]; + /** Return the Virtual Memory Map of your platform =20 @@ -59,20 +62,41 @@ ArmPlatformGetVirtualMemoryMap ( IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap ) { - ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; UINTN Index =3D 0; + UINT64 MemSize; + UINT64 MemLowSize; + UINT64 MemHighStart; + UINT64 MemHighSize; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; =20 ASSERT (VirtualMemoryMap !=3D NULL); =20 - VirtualMemoryTable =3D (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_= SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MA= P_DESCRIPTORS)); - if (VirtualMemoryTable =3D=3D NULL) { - return; - } + MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); + MemLowSize =3D MIN (FixedPcdGet64 (PcdDramRemapTarget), MemSize); + MemHighStart =3D (UINT64)FixedPcdGet64 (PcdDramRemapTarget) + + FixedPcdGet32 (PcdDramRemapSize); + MemHighSize =3D MemSize - MemLowSize; + + ResourceAttributes =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED + ); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + FixedPcdGet64 (PcdSystemMemoryBase), + MemLowSize + ); =20 // DDR - VirtualMemoryTable[Index].PhysicalBase =3D PcdGet64 (PcdSystemMemoryB= ase); - VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdSystemMemoryB= ase); - VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdSystemMemoryS= ize); + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64 (PcdSystemMe= moryBase); + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64 (PcdSystemMe= moryBase); + VirtualMemoryTable[Index].Length =3D MemLowSize; VirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED; =20 // Configuration space 0xF000_0000 - 0xFFFF_FFFF @@ -81,13 +105,29 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length =3D 0x10000000; VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBUT= E_DEVICE; =20 + if (MemSize > MemLowSize) { + // + // If we have more than MemLowSize worth of DRAM, the remainder will be + // mapped at the top of the remapped window. + // + VirtualMemoryTable[++Index].PhysicalBase =3D MemHighStart; + VirtualMemoryTable[Index].VirtualBase =3D MemHighStart; + VirtualMemoryTable[Index].Length =3D MemHighSize; + VirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED; + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + MemHighStart, + MemHighSize + ); + } + // End of Table VirtualMemoryTable[++Index].PhysicalBase =3D 0; VirtualMemoryTable[Index].VirtualBase =3D 0; VirtualMemoryTable[Index].Length =3D 0; VirtualMemoryTable[Index].Attributes =3D 0; =20 - ASSERT((Index + 1) <=3D MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); - *VirtualMemoryMap =3D VirtualMemoryTable; } diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 434d6cb..db1c7fa 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -194,6 +194,19 @@ #TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0x0|UINT64|0x50000053 =20 + # + # DRAM remapping controls. + # On the 70x0/80x0 SOCs, the DRAM is mapped at 0x0, and could be up to + # 16 GB in size. To allow for 32-bit addressable MMIO peripherals or PCI + # windows, a single window of up to 4 GB in size can be remapped elsewhe= re. + # So let's define a 1 GB window at 0xC000000 by default: this is the min= imum + # alignment that Linux can map optimally (i.e., it's section shift is 30= bits) + # and gives us an additional 768 MB (on top of the 256 MB platform MMIO = window + # at 0xF0000000) for the PCI MMIO32 and CONFIG spaces. + # + gMarvellTokenSpaceGuid.PcdDramRemapSize|0x40000000|UINT32|0x50000004 + gMarvellTokenSpaceGuid.PcdDramRemapTarget|0xC0000000|UINT32|0x50000003 + [Protocols] gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 18:18:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507736494887133.0877614547652; Wed, 11 Oct 2017 08:41:34 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C9EE121F7D4F0; Wed, 11 Oct 2017 08:37:53 -0700 (PDT) Received: from mail-lf0-x22a.google.com (mail-lf0-x22a.google.com [IPv6:2a00:1450:4010:c07::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AB59A21F7D4F0 for ; Wed, 11 Oct 2017 08:37:51 -0700 (PDT) Received: by mail-lf0-x22a.google.com with SMTP id l23so2543418lfk.10 for ; Wed, 11 Oct 2017 08:41:21 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:17 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22a; helo=mail-lf0-x22a.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Rzw+9OOUwEFnJNsa73IcJxgculLzL6dsX72yn2hfE3E=; b=c7WahB++HugRO0cXVVUTEKjzWB68X/IZ2Ek4vzK9+NqvWtxIZ7xfvGUXe7AlkX5vh3 KNiRgTHAOrMosr4UBQCoB79ndd5Mma4dyudJzcM0NjlkkCLV8U/xPJU/uw9m8GruV/Jy p92zaoXGL6OBVtHN8kSTk/23G0XcV8jyOszq3RbCBedD70aZvp+3eEHek+YKAQUujjdJ c8IdmJKECxMLglae1w5yWPGoFSb+7kgTM/QGLDgSaCYMYgPktaxg41Ey7ZymUCvcI8xQ 8Fk+pCHZr68wCvkDKzVgRUehSt1DhgFYro6KC3heC886mcgnE9u3f8u+PTSjp9U9d72H bncA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Rzw+9OOUwEFnJNsa73IcJxgculLzL6dsX72yn2hfE3E=; b=sWJO7f6PeeRWZOFd1ckygRh7ekiIhAnV1JqL7x7vxoFUySa+cfu8R32YcpUaJIBrWO P32TIN4e3Ag9FSKMJRWDnOCGCTnSrUAv62UfyTbgLKiCVdRB5HlEw2Jy9KJPu4sdPFYz k5M9q61q7LYReJZJzoVKpRqmDt3Ke/d9z5VblAJ95LhpmFnNUlrU6CAc4IpPTdHWoXC+ 51/0ibr7KmqJR/Tssxjq9aIT/LWr2voa7LVEyMacb4u9xdSslylqccK8wbZzujGs2nxg QwR6kYfK7uIKL1yYiF9HVTlERQnUlk55Ehe2Vg8xL5qbsJ0/1SE+xQWUiLbZcfneMvdX h+tQ== X-Gm-Message-State: AMCzsaWyqhW7Ba9wSkG1EgZPxF+8JaC0MZPmLJ6Ig7Q3OnVSaSf2ESoo lF1gf2LlBJJ8BZ60RVLuE4KrZ0+BHZc= X-Google-Smtp-Source: AOwi7QCeFmhV2l2wNw5Fk6OawKIiZN7uCXtnd01nwJG+aDODOYJsmiCjD8XfUCyXJA7vwYpQB2070A== X-Received: by 10.46.58.2 with SMTP id h2mr23003lja.132.1507736479162; Wed, 11 Oct 2017 08:41:19 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:46 +0200 Message-Id: <1507736449-6073-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 5/8] Marvell/Armada: Add MemoryInitPeiLib that reserves secure region X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The default MemoryInitPeiLib implementation insists on reserving the region occupied by our own FV, while this is not necessary at all (the compressed payload is uncompressed elsewhere, so the moment we enter DXE core, we don't care about the FV contents in memory) So clone MemoryInitPeiLib and modify it to suit our needs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc = | 6 +- Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0Memor= yInitPeiLib.c | 158 ++++++++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0Memor= yInitPeiLib.inf | 46 ++++++ Platform/Marvell/Marvell.dec = | 8 + 4 files changed, 217 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 56d8941..b0a8240 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -153,7 +153,7 @@ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf =20 [LibraryClasses.common.SEC, LibraryClasses.common.PEIM] - MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + MemoryInitPeiLib|Platform/Marvell/Armada/Library/Armada70x0MemoryInitPei= Lib/Armada70x0MemoryInitPeiLib.inf BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf =20 [LibraryClasses.common.DXE_CORE] @@ -364,6 +364,10 @@ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 gArmTokenSpaceGuid.PcdArmScr|0x531 =20 + # Secure region reservation + gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000 + # TRNG gMarvellTokenSpaceGuid.PcdEip76TrngBaseAddress|0xF2760000 =20 diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Arm= ada70x0MemoryInitPeiLib.c b/Platform/Marvell/Armada/Library/Armada70x0Memor= yInitPeiLib/Armada70x0MemoryInitPeiLib.c new file mode 100644 index 0000000..53119f4 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0= MemoryInitPeiLib.c @@ -0,0 +1,158 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2017, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the B= SD License +* which accompanies this distribution. The full text of the license may = be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +STATIC +VOID +InitMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable + ) +{ + + VOID *TranslationTableBase; + UINTN TranslationTableSize; + RETURN_STATUS Status; + + Status =3D ArmConfigureMmu (MemoryTable, + &TranslationTableBase, + &TranslationTableSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n")); + } +} + +/*++ + +Routine Description: + + + +Arguments: + + FileHandle - Handle of the file being invoked. + PeiServices - Describes the list of possible PEI Services. + +Returns: + + Status - EFI_SUCCESS if the boot mode could be set + +--*/ +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + UINT64 ResourceLength; + EFI_PEI_HOB_POINTERS NextHob; + EFI_PHYSICAL_ADDRESS SecureTop; + EFI_PHYSICAL_ADDRESS ResourceTop; + + // Get Virtual Memory Map from the Platform Library + ArmPlatformGetVirtualMemoryMap (&MemoryTable); + + SecureTop =3D (EFI_PHYSICAL_ADDRESS)FixedPcdGet64 (PcdSecureRegionBase) + + FixedPcdGet32 (PcdSecureRegionSize); + + // + // Search for System Memory Hob that covers the secure firmware, + // and punch a hole in it + // + for (NextHob.Raw =3D GetHobList (); + NextHob.Raw !=3D NULL; + NextHob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, + NextHob.Raw)) { + + if ((NextHob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYST= EM_MEMORY) && + (FixedPcdGet64 (PcdSecureRegionBase) >=3D NextHob.ResourceDescript= or->PhysicalStart) && + (SecureTop <=3D NextHob.ResourceDescriptor->PhysicalStart + + NextHob.ResourceDescriptor->ResourceLength)) + { + ResourceAttributes =3D NextHob.ResourceDescriptor->ResourceAttribute; + ResourceLength =3D NextHob.ResourceDescriptor->ResourceLength; + ResourceTop =3D NextHob.ResourceDescriptor->PhysicalStart + Resource= Length; + + if (FixedPcdGet64 (PcdSecureRegionBase) =3D=3D NextHob.ResourceDescr= iptor->PhysicalStart) { + // + // This region starts right at the start of the reserved region, s= o we + // can simply move its start pointer and reduce its length by the = same + // value + // + NextHob.ResourceDescriptor->PhysicalStart +=3D FixedPcdGet32 (PcdS= ecureRegionSize); + NextHob.ResourceDescriptor->ResourceLength -=3D FixedPcdGet32 (Pcd= SecureRegionSize); + + } else if ((NextHob.ResourceDescriptor->PhysicalStart + + NextHob.ResourceDescriptor->ResourceLength) =3D=3D Secur= eTop) { + + // + // This region ends right at the end of the reserved region, so we + // can simply reduce its length by the size of the region. + // + NextHob.ResourceDescriptor->ResourceLength -=3D FixedPcdGet32 (Pcd= SecureRegionSize); + + } else { + // + // This region covers the reserved region. So split it into two re= gions, + // each one touching the reserved region at either end, but not co= vering + // it. + // + NextHob.ResourceDescriptor->ResourceLength =3D FixedPcdGet64 (PcdS= ecureRegionBase) - + NextHob.ResourceDescr= iptor->PhysicalStart; + + // Create the System Memory HOB for the remaining region (top of t= he FD) + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, + ResourceAttributes, + SecureTop, + ResourceTop - SecureTop); + } + + // + // Reserve the memory space occupied by the secure firmware + // + BuildResourceDescriptorHob (EFI_RESOURCE_MEMORY_RESERVED, + 0, + FixedPcdGet64 (PcdSecureRegionBase), + FixedPcdGet32 (PcdSecureRegionSize)); + + break; + } + NextHob.Raw =3D GET_NEXT_HOB (NextHob); + } + + // Build Memory Allocation Hob + InitMmu (MemoryTable); + + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { + // Optional feature that helps prevent EFI memory map fragmentation. + BuildMemoryTypeInformationHob (); + } + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Arm= ada70x0MemoryInitPeiLib.inf b/Platform/Marvell/Armada/Library/Armada70x0Mem= oryInitPeiLib/Armada70x0MemoryInitPeiLib.inf new file mode 100644 index 0000000..ebaed01 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0MemoryInitPeiLib/Armada70x0= MemoryInitPeiLib.inf @@ -0,0 +1,46 @@ +#/** @file +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D Armada70x0MemoryInitPeiLib + FILE_GUID =3D abc4e8a7-89a7-4aea-92bc-0e9421c4a473 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MemoryInitPeiLib|SEC PEIM + +[Sources] + Armada70x0MemoryInitPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + ArmPlatformLib + DebugLib + HobLib + ArmMmuLib + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdSecureRegionBase + gMarvellTokenSpaceGuid.PcdSecureRegionSize diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index db1c7fa..63ea071 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -207,6 +207,14 @@ gMarvellTokenSpaceGuid.PcdDramRemapSize|0x40000000|UINT32|0x50000004 gMarvellTokenSpaceGuid.PcdDramRemapTarget|0xC0000000|UINT32|0x50000003 =20 + # + # The secure firmware may occupy a DRAM region that is accessible by the + # normal world. These PCDs describe such a region, which will be convert= ed + # to 'reserved' memory before DXE is entered. + # + gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x0|UINT64|0x50000000 + gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0|UINT32|0x50000001 + [Protocols] gMarvellEepromProtocolGuid =3D { 0x71954bda, 0x60d3, 0x4ef= 8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} gMarvellMdioProtocolGuid =3D { 0x40010b03, 0x5f08, 0x496= a, { 0xa2, 0x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 18:18:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507736499636738.6288765387611; Wed, 11 Oct 2017 08:41:39 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 11ABF21F7D4F5; Wed, 11 Oct 2017 08:37:54 -0700 (PDT) Received: from mail-lf0-x22b.google.com (mail-lf0-x22b.google.com [IPv6:2a00:1450:4010:c07::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1765521F7D4F0 for ; Wed, 11 Oct 2017 08:37:53 -0700 (PDT) Received: by mail-lf0-x22b.google.com with SMTP id k40so2555950lfi.4 for ; Wed, 11 Oct 2017 08:41:22 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:19 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22b; helo=mail-lf0-x22b.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1yr23/bNsNUB/H1OZK14WdkfIV/L+PN6cBXM9vntJDA=; b=Ydxa9P4ok4ivE3Uln5r/seg9efkdCC+Opl16RQA07UtJv0y+Y06PujgbTfRVx3ivm9 a9S3QTrBYwzHmdopAqwypt0Hwivm3zXW/9R9eG+9PrhDGwkBT7VbbGyizM8BYGn40317 IFLVvzg1jI0izoD10lX8XmTJmy6TFTVN7VoZ8zoLJsFU2q/Fq2aPuvjbqzVEnI3HVQo4 iGu58yXd8FKM6aogf6fQRR+Re2SZBGTZ7PlFPnrGcv+XRt4lYVTCXmbQ5UVaQEoD8LkL B16yjyYUIE8YLq3Ol42JGYqJkpRQXskw6WkJB6VZ0HQ0ToQVH7YvpdpIc0vNye1qbaXO lV7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1yr23/bNsNUB/H1OZK14WdkfIV/L+PN6cBXM9vntJDA=; b=Zwby5Yboe/bpp6Qsmubd6DZiuWLgSrAmVi0fKRpTFvYhyWbBPuQVU28+kdjlNMfNri +QZhWsFw/I8Buy5tX+MExBX+tW/w5gNNBgqaorjq8h2Jrk1Acy5F9iko3SZdxDYfzrv3 93SNmM9kDM8UNEyuZgYVEwJbsIejsZe82i7JtPkm2gnggwjsDfK8WazWhd+v8g8B7V8K CHYgcd0Mq42Ntr4skKlrJ3YcEkvx8stbU8mowZHnLWvmjXeB7/GTjnhcH2qhZIpJGz2B O+bxWtdsDLYD1YZpvwq6RkHnN2BL5pK9DTYvcIiYyfZMvmajPFj2OJ1ZqlTHyPAEKJRJ 8Frg== X-Gm-Message-State: AMCzsaXBzC3xAVs+d2sfsuW9ID1jr2/5i64dKiKpFJJtv6iNxxNhSCtN 7lZbKWPfOK4Qb4GaSBCTlyNVeU59dT4= X-Google-Smtp-Source: AOwi7QDn8QvVZzORvujPBjOk9IhMCZ46/S0J1BSFi4aFL5UXjDqp1uDozVDg8GbF5wuJEmt/5wJGiA== X-Received: by 10.46.65.216 with SMTP id d85mr25726ljf.156.1507736480594; Wed, 11 Oct 2017 08:41:20 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:47 +0200 Message-Id: <1507736449-6073-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 6/8] Marvell/Armada: Enable dynamic DRAM size detection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Instead of using hardcoded value in PcdSystemMemorySize PCD, obtain DRAM size directly from SoC registers, which are filled by firmware during early initialization stage. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c | 111 +++= ++++++++++++++++- Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h | 49 +++= ++++++ 2 files changed, 159 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem= .c b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c index 2cb2e15..22cbe47 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.c @@ -36,8 +36,11 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #include #include #include +#include #include =20 +#include "Armada70x0LibMem.h" + // The total number of descriptors, including the final "end-of-table" des= criptor. #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 16 =20 @@ -47,6 +50,105 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. =20 STATIC ARM_MEMORY_REGION_DESCRIPTOR VirtualMemoryTable[MAX_VIRTUAL_MEMORY_= MAP_DESCRIPTORS]; =20 +// Obtain DRAM size basing on register values filled by early firmware. +STATIC +UINT64 +DramSizeGet ( + UINT64 *MemSize + ) +{ + UINT64 BaseAddr; + UINT32 RegVal; + UINT8 AreaLengthMap; + UINT8 Cs; + + *MemSize =3D 0; + + for (Cs =3D 0; Cs < DRAM_MAX_CS_NUM; Cs++) { + + RegVal =3D MmioRead32 (DRAM_CH0_MMAP_LOW_REG (Cs)); + + /* Exit loop on first disabled DRAM CS */ + if (!(RegVal & DRAM_CS_VALID_ENABLED_MASK)) { + break; + } + + /* + * Sanity check for base address of next DRAM block. + * Only continuous space will be used. + */ + BaseAddr =3D ((UINT64)MmioRead32 (DRAM_CH0_MMAP_HIGH_REG (Cs)) << + DRAM_START_ADDR_HTOL_OFFS) | (RegVal & DRAM_START_ADDRESS_= L_MASK); + if (BaseAddr !=3D *MemSize) { + DEBUG ((DEBUG_ERROR, + "DramSizeGet: DRAM blocks are not contiguous, limit size to 0x%llx= \n", + *MemSize)); + return EFI_SUCCESS; + } + + /* Decode area length for current CS from register value */ + AreaLengthMap =3D ((RegVal & DRAM_AREA_LENGTH_MASK) >> DRAM_AREA_LENGT= H_OFFS); + switch (AreaLengthMap) { + case 0x0: + *MemSize +=3D 0x18000000; + break; + case 0x1: + *MemSize +=3D 0x30000000; + break; + case 0x2: + *MemSize +=3D 0x60000000; + break; + case 0x3: + *MemSize +=3D 0xC0000000; + break; + case 0x7: + *MemSize +=3D 0x00800000; + break; + case 0x8: + *MemSize +=3D 0x01000000; + break; + case 0x9: + *MemSize +=3D 0x02000000; + break; + case 0xA: + *MemSize +=3D 0x04000000; + break; + case 0xB: + *MemSize +=3D 0x08000000; + break; + case 0xC: + *MemSize +=3D 0x10000000; + break; + case 0xD: + *MemSize +=3D 0x20000000; + break; + case 0xE: + *MemSize +=3D 0x40000000; + break; + case 0xF: + *MemSize +=3D 0x80000000; + break; + case 0x10: + *MemSize +=3D 0x100000000; + break; + case 0x11: + *MemSize +=3D 0x200000000; + break; + case 0x12: + *MemSize +=3D 0x400000000; + break; + case 0x13: + *MemSize +=3D 0x800000000; + break; + default: + DEBUG ((DEBUG_ERROR, "Invalid area length (0x%x) for CS#%d\n", AreaL= engthMap, Cs)); + return EFI_INVALID_PARAMETER; + } + } + + return EFI_SUCCESS; +} + /** Return the Virtual Memory Map of your platform =20 @@ -68,10 +170,17 @@ ArmPlatformGetVirtualMemoryMap ( UINT64 MemHighStart; UINT64 MemHighSize; EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; + EFI_STATUS Status; =20 ASSERT (VirtualMemoryMap !=3D NULL); =20 - MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); + // Obtain total memory size from the hardware. + Status =3D DramSizeGet (&MemSize); + if (EFI_ERROR (Status)) { + MemSize =3D FixedPcdGet64 (PcdSystemMemorySize); + DEBUG ((DEBUG_ERROR, "Limit total memory size to %d MB\n", MemSize / 1= 024 / 1024)); + } + MemLowSize =3D MIN (FixedPcdGet64 (PcdDramRemapTarget), MemSize); MemHighStart =3D (UINT64)FixedPcdGet64 (PcdDramRemapTarget) + FixedPcdGet32 (PcdDramRemapSize); diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem= .h b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h new file mode 100644 index 0000000..b81fd1d --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0LibMem.h @@ -0,0 +1,49 @@ +/*************************************************************************= ****** +Copyright (C) 2017 Marvell International Ltd. + +Marvell BSD License Option + +If you received this File from Marvell, you may opt to use, redistribute a= nd/or +modify this File under the following licensing terms. +Redistribution and use in source and binary forms, with or without modific= ation, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +* Neither the name of Marvell nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +**************************************************************************= *****/ + +#define DRAM_CONF_BASE 0xf0020000 + +#define DRAM_CH0_MMAP_LOW_BASE (DRAM_CONF_BASE + 0x200) +#define DRAM_CH0_MMAP_LOW_REG(cs) (DRAM_CH0_MMAP_LOW_BASE + (cs) * 0x8) +#define DRAM_CS_VALID_ENABLED_MASK 0x1 +#define DRAM_AREA_LENGTH_OFFS 16 +#define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) +#define DRAM_START_ADDRESS_L_OFFS 23 +#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS) + +#define DRAM_CH0_MMAP_HIGH_BASE (DRAM_CONF_BASE + 0x204) +#define DRAM_CH0_MMAP_HIGH_REG(cs) (DRAM_CH0_MMAP_HIGH_BASE + (cs) * 0x= 8) +#define DRAM_START_ADDR_HTOL_OFFS 32 + +#define DRAM_MAX_CS_NUM 8 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 18:18:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507736503674528.6921234833641; Wed, 11 Oct 2017 08:41:43 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 504E621F7D4F8; Wed, 11 Oct 2017 08:37:55 -0700 (PDT) Received: from mail-lf0-x231.google.com (mail-lf0-x231.google.com [IPv6:2a00:1450:4010:c07::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7A7D621F7D4F4 for ; Wed, 11 Oct 2017 08:37:54 -0700 (PDT) Received: by mail-lf0-x231.google.com with SMTP id g70so2556815lfl.3 for ; Wed, 11 Oct 2017 08:41:23 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:21 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::231; helo=mail-lf0-x231.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hk66oXNfmi1mIMfvmK//JVJdGthOZYrSl3pzB9f+g2o=; b=ILUWpjxVog0vb+1Hkfy1XROoBbMIIypP7GSUSohvUtnN8DkCF6TpagXSXmiqX+qDUm bxulid/xvVDCiGzdiq3ZMxJZw3jYdjHR2dLrpUDOrlMrTi/458cNAcFpdgk9H0JOLRjk M6raGl67sG1aJc1toQNMFtBkxWVaDaFD0hBVVghTedAG349265gzQ8WVLop2aPQC5kEn 37xtM/zjCG+QwDI1Nk4KXwQeC6CQoKO6e64uj9fHra1x+TgmGMW5ZQnR8LHpUa21rMaX 0uV5TX9W2Jy9LCq2yu/Z/6QFxmeCRGp+0zKk90R56szXwZD/9ejJzQ7yp5u8dDN37dKY 5Hzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hk66oXNfmi1mIMfvmK//JVJdGthOZYrSl3pzB9f+g2o=; b=FRiTF49KPN4R5/BCUUPITlDS3h+UadZofCgBX4+20Cd4g1OBwVB45yLqrFPEAWsY4I Ppi8FHo7pTih3tgYKsNx3EhEWP0K2Pmmw6AcjRwpM0y4F+G0ITt19Jq/PZsN7SNzkYJn ZICY3G3+ekugP/Lm4KaLnsPcDMmGqZ4Mp728hP8mq/L2/axZeAmXFG2UGZUiH3EkZwL5 sMvjdRI/4/zm9aZGAJD50tpAmB3UGrkTOfMBzy2wHzwqsjtRrUZ6EljrPqzndFu7ciwG sK18JPPcQADv3EsTZZ5U5WMW+J3sspP5UAI7asEviucOjv35rXpcuMF+WaC9tg3B6gzF AFxA== X-Gm-Message-State: AMCzsaWql0nh2L7azbRZKQnXfeVylTcCFgWiWk4uJUOirhvoNKXRdwQy RBBxl47ui05uTDum/93dvowjp5cOCGo= X-Google-Smtp-Source: AOwi7QAXy8AA9saV8byTDcx772jPgfRD6VEBofEkWVXY3xLt1CGbVzrrqgamXLKLF9ieeSo9VCYSUw== X-Received: by 10.46.99.86 with SMTP id x83mr11041ljb.161.1507736482022; Wed, 11 Oct 2017 08:41:22 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:48 +0200 Message-Id: <1507736449-6073-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 7/8] Marvell/Armada: Armada70x0Lib: Add support for 32-bit ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Add an ARM implementation of ArmPlatformHelper.S. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S | 77= ++++++++++++++++++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf | 3= + 2 files changed, 80 insertions(+) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformH= elper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelp= er.S new file mode 100644 index 0000000..21459e5 --- /dev/null +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/ARM/ArmPlatformHelper.S @@ -0,0 +1,77 @@ +//Based on ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/ArmPlatformHe= lper.S +// +// Copyright (c) 2012-2013, ARM Limited. All rights reserved. +// Copyright (c) 2016, Marvell. All rights reserved. +// Copyright (c) 2017, Linaro Limited. All rights reserved. +// +// This program and the accompanying materials are licensed and made avai= lable +// under the terms and conditions of the BSD License which accompanies th= is +// distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED +// + +#include +#include + +#define CCU_MC_BASE 0xF0001700 +#define CCU_MC_RCR_OFFSET 0x0 +#define CCU_MC_RCR_REMAP_EN BIT0 +#define CCU_MC_RCR_REMAP_SIZE(Size) (((Size) - 1) ^ (SIZE_1MB - 1)) + +#define CCU_MC_RSBR_OFFSET 0x4 +#define CCU_MC_RSBR_SOURCE_BASE(Base) (((Base) >> 20) << 10) +#define CCU_MC_RTBR_OFFSET 0x8 +#define CCU_MC_RTBR_TARGET_BASE(Base) (((Base) >> 20) << 10) + +ASM_FUNC(ArmPlatformPeiBootAction) + .if FixedPcdGet64 (PcdSystemMemoryBase) !=3D 0 + .err PcdSystemMemoryBase should be 0x0 on this platform! + .endif + + .if FixedPcdGet64 (PcdSystemMemorySize) > FixedPcdGet32 (PcdDramRemapT= arget) + // + // Use the low range for UEFI itself. The remaining memory will be map= ped + // and added to the GCD map later. + // + ADRL (r0, mSystemMemoryEnd) + MOV32 (r2, FixedPcdGet32 (PcdDramRemapTarget) - 1) + mov r3, #0 + strd r2, r3, [r0] + .endif + + bx lr + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos =3D (ClusterId * 2) + CoreId +ASM_FUNC(ArmPlatformGetCorePosition) + and r1, r0, #ARM_CORE_MASK + and r0, r0, #ARM_CLUSTER_MASK + add r0, r1, r0, LSR #7 + bx lr + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (r0, FixedPcdGet32(PcdArmPrimaryCore)) + bx lr + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCoreMask)) + and r0, r0, r1 + MOV32 (r1, FixedPcdGet32(PcdArmPrimaryCore)) + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.in= f b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf index 838a670..0dabd4b 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.inf @@ -60,6 +60,9 @@ [Sources.AArch64] AArch64/ArmPlatformHelper.S =20 +[Sources.ARM] + ARM/ArmPlatformHelper.S + [FixedPcd] gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 18:18:31 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507736507815401.8370073607607; Wed, 11 Oct 2017 08:41:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8AC3821F7D4F4; Wed, 11 Oct 2017 08:37:57 -0700 (PDT) Received: from mail-lf0-x232.google.com (mail-lf0-x232.google.com [IPv6:2a00:1450:4010:c07::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BB0B721F7D4F4 for ; Wed, 11 Oct 2017 08:37:55 -0700 (PDT) Received: by mail-lf0-x232.google.com with SMTP id d10so2560788lfg.11 for ; Wed, 11 Oct 2017 08:41:25 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p15sm160610lje.24.2017.10.11.08.41.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 08:41:22 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::232; helo=mail-lf0-x232.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LTimKYWTUq+stlmO2jUWw5uumx/gilGp4pE/BMHK9I4=; b=QvYEUJRFoMJOrjmpBFd8NkBLMQU/C/16fxO7T0Tm0Djhwf+99W+zUizThob7MEFhR9 +4835SMtmw+rjBIzVP5ndvuSG++WSm6LLHQnLGw6edi/0N1Pmzv7m3rYvNwrEBnDI76D QJ8CCTJ/HnPYQvx8OPfDUy4q+LRlpYvm/CUYWd/iHpZ9uUBEtj/9PmB6yYnf2Fqth0eK SO7/D/ipAk+/3Ta6HK0CvmguYTUFpFAFaTdX7T5/OonFGPz/5r4a/0BiZ/liyUgAeIiA wzhzHjkrw+V4UhLpjP1ubMtvzD89SN4APpPF8TxgZcdzkFpjD6fqW/Qo/melSqKgFSiK LhaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LTimKYWTUq+stlmO2jUWw5uumx/gilGp4pE/BMHK9I4=; b=ZKYlNMnO04CSpfSSNVQdWgFZjqS9OpH0004o7y/WU6b6NHSnTBIcyva4TrmVwAfwJT VTvXmL5+kDsA9kFm7fXpQQkB0FKbY4NHad3XaCNjerajd1/MsejeQqviJstyTIqgv3KZ OxDKNAWO9OwSWqBH5NGmjPHks2Cqa94nPE48Ru9ly3PBjrhltkAHNAdRMP1M3nIG7UXg /wmhTd/kkUBm4fYHIei8KnI/VrhsKDbkCbsf1JeXTxcK3QtPfnjaDtQZEksABbN5Zwom gX6QwOjl9UiXYgGG82I8DZHLNbwXkwgKxPpoNymuKcVA4wyiAx+ghKuTQGYRlEVnza/o uU0A== X-Gm-Message-State: AMCzsaXH7g1ZwMdZ/Oi/T29G0uhXPapRI6CVXlG+Bc2pBWMsM/RTVjHu ru3zgi7tKrIoEZyGdlJALGv1fP9Z3YI= X-Google-Smtp-Source: AOwi7QBwGf9KMLQmbAxrV5P1S+7WRnsgJMTFAvODh1SBcxfFSqs9Xx7uzty8Odm7myHsAdrISkk8pg== X-Received: by 10.46.68.155 with SMTP id b27mr26046ljf.86.1507736483376; Wed, 11 Oct 2017 08:41:23 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 17:40:49 +0200 Message-Id: <1507736449-6073-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507736449-6073-1-git-send-email-mw@semihalf.com> References: <1507736449-6073-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 8/8] Marvell/Armada: Add 32-bit ARM support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Update the included components and library classes to make this platform build for 32-bit ARM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 3 +-- Platform/Marvell/Armada/Armada70x0.dsc | 4 ++-- Platform/Marvell/Armada/Armada70x0.fdf | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index b0a8240..b9fc384 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -132,7 +132,6 @@ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf =20 -[LibraryClasses.AARCH64] ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/Ar= mGenericTimerPhyCounterLib.inf @@ -362,7 +361,7 @@ # ARM Pcds gArmTokenSpaceGuid.PcdSystemMemoryBase|0 gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 - gArmTokenSpaceGuid.PcdArmScr|0x531 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36 =20 # Secure region reservation gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 946c93e..0396e8e 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -39,8 +39,8 @@ PLATFORM_GUID =3D f837e231-cfc7-4f56-9a0f-5b218d746ae3 PLATFORM_VERSION =3D 0.1 DSC_SPECIFICATION =3D 0x00010005 - OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) - SUPPORTED_ARCHITECTURES =3D AARCH64 + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH) + SUPPORTED_ARCHITECTURES =3D AARCH64|ARM BUILD_TARGETS =3D DEBUG|RELEASE SKUID_IDENTIFIER =3D DEFAULT FLASH_DEFINITION =3D Platform/Marvell/Armada/Armada70x0.fdf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index a94a9ff..ec2c368 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -237,7 +237,7 @@ READ_LOCK_STATUS =3D TRUE # ##########################################################################= ## =20 -[Rule.AARCH64.SEC] +[Rule.Common.SEC] FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi } --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel