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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.15.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:15:57 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::236; helo=mail-lf0-x236.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EpjCl/cmnnUgdY7RglaorymXIFAIcFW29XiqxJtKBrg=; b=fOCJbehWCAFwnuESzRjNpjoXzfuWsb+kNNXMV7oYWZ3kEKPOdT4h7gsBgAotlcSkbr kSNCIlSwRBFpue/uuVtsa6CxVcd283cjJBeQ/QkT/10jfVZltLoEAlEA9isZrDk+gDTg LM/VosF6o4ungAy6+kFzxV9mRYnKuA5U4qmHQr3ioaH99LTcZ+IS6Kc9mgGJa+EL0zWQ +TGx3PaEA00VJi9xb+GE0u+Q+bysN4FgJM8gsot//mp9Qb8fhoEvj5PfCFg2px/7gfak WnmUoAA5gnAoF6pl7j3UovzvdmVfskyTphb0ANfE+lFpO5PThMjSTKi7l3OzHisHJc31 y0HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EpjCl/cmnnUgdY7RglaorymXIFAIcFW29XiqxJtKBrg=; b=L2lPSq1p01wNvkYWuku0pFTWcqOyfWJsXGLq3deMrVDAPyhkwBWr/0GWLeoXnog+SX dEUdeKuhC/u2urfnfoBiQT+W/Ln20ppSpgSuFIdNdFk4sct6JLjy4reNgdjLOdPYAkQL QboOBcEUyTHpQq7CdVcKMzLMPr8pSfcgIbnb2GdNfvVPg18e4B0DMSZP8r8kBTH4YqfB N0pFHN5ZGPjECuDS62IC4QpU//cNFAynUbc9hIM1MulLDxDtH5cYuzxnBqqHvDVCv98i /2Y2KCXDXC0CZMTNCmaWtQzACuFFbgAftU4W3DkdFD2ESREYvYJq1bBAGKsrgwrSNqrv 1G5w== X-Gm-Message-State: AMCzsaXCtDx1U4Lax23+XsGDcttF/rV2YrAsK7tbwbUaNiUKicVAjfav ZwFFSpVgnS4jUueG56GzYbdNIPXUG+Y= X-Google-Smtp-Source: AOwi7QAnpzR8EdZFQmrRsJU+hTvaYYSk+SDW6aL2ymSY7elihpMqkhko6l33DtirET+baNu5UPqwUQ== X-Received: by 10.25.193.81 with SMTP id r78mr3151909lff.187.1507716958645; Wed, 11 Oct 2017 03:15:58 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:28 +0200 Message-Id: <1507716939-31798-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 01/12] Marvell/Armada: Introduce platform initialization driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In order to enable modification of dynamic PCD's for the libraries and DXE drivers, this patch introduces new driver. It is executed prior to other drivers. Mpp, ComPhy and Utmi libraries initialization were moved from PrePi stage to DXE. To force the correct driver dispatch sequence, introduce a protocol GUID and install the protocol as a NULL protocol when PlatInitDxe executes. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas [Introduce protocol GUID to force correct driver dispatch order] Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 3 ++ Platform/Marvell/Armada/Armada70x0.fdf | 5 +++ Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c | 45 +++++++= +++++++++++++ Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf | 45 +++++++= +++++++++++++ Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c | 11 ----- Platform/Marvell/Marvell.dec | 5 +++ 6 files changed, 103 insertions(+), 11 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 89fb7e7..417bb0c 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -378,6 +378,9 @@ ArmPkg/Drivers/TimerDxe/TimerDxe.inf ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf =20 + # Platform Initialization + Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf + # Platform drivers Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index c861e78..763d76a 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -89,6 +89,11 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1b= 30c =20 INF MdeModulePkg/Core/Dxe/DxeMain.inf =20 + # + # Platform Initialization + # + INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf + # PI DXE Drivers producing Architectural Protocols (EFI Services) INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c b/Pl= atform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c new file mode 100644 index 0000000..1efad77 --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.c @@ -0,0 +1,45 @@ +/** @file + Copyright (c) 2017, Linaro Limited. All rights reserved. + Copyright (c) 2017, Marvell International Ltd. and its affiliates + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +ArmadaPlatInitDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_ERROR, "\nArmada Platform Init\n\n")); + + Status =3D gBS->InstallProtocolInterface (&ImageHandle, + &gMarvellPlatformInitCompleteProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR (Status); + + MvComPhyInit (); + UtmiPhyInit (); + MppInitialize (); + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf b/= Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf new file mode 100644 index 0000000..790b7e3 --- /dev/null +++ b/Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -0,0 +1,45 @@ +#/* @file +# Copyright (c) 2017, Linaro Limited. All rights reserved. +# Copyright (c) 2017, Marvell International Ltd. and its affiliates +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +#*/ + +[Defines] + INF_VERSION =3D 0x00010019 + BASE_NAME =3D PlatInitDxe + FILE_GUID =3D 8c66f65b-08a6-4c91-b993-ff81e0adf818 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D ArmadaPlatInitDxeEntryPoint + +[Sources] + PlatInitDxe.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/Marvell/Marvell.dec + +[LibraryClasses] + ComPhyLib + DebugLib + MppLib + PcdLib + TimerLib + UefiDriverEntryPoint + UtmiPhyLib + +[Protocols] + gMarvellPlatformInitCompleteProtocolGuid ## PRODUCES + +[Depex] + TRUE diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c = b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c index 0ed310f..968d28f 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0Lib.c @@ -15,12 +15,8 @@ =20 #include #include -#include -#include -#include #include =20 - ARM_CORE_INFO mArmada7040MpCoreInfoTable[] =3D { { // Cluster 0, Core 0 @@ -90,13 +86,6 @@ ArmPlatformInitialize ( IN UINTN MpId ) { - if (!ArmPlatformIsPrimaryCore (MpId)) { - return RETURN_SUCCESS; - } - - MvComPhyInit (); - UtmiPhyInit (); - MppInitialize (); return RETURN_SUCCESS; } =20 diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 0902086..e7d7c2c 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -56,6 +56,11 @@ gShellFUpdateHiiGuid =3D { 0x9b5d2176, 0x590a, 0x49db, { 0x89, 0x5d, 0x4= a, 0x70, 0xfe, 0xad, 0xbe, 0x24 } } gShellSfHiiGuid =3D { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x= 0f, 0x6d, 0x58, 0x81, 0x39 } } =20 +[Protocols] + # installed as a protocol by PlatInitDxe to force ordering between DXE d= rivers + # that depend on the lowlevel platform initialization having been comple= ted + gMarvellPlatformInitCompleteProtocolGuid =3D { 0x465b8cf7, 0x016f, 0x4ba= 6, { 0xbe, 0x6b, 0x28, 0x0e, 0x3a, 0x7d, 0x38, 0x6f } } + [PcdsFixedAtBuild.common] #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|0|UINT32|0x30000001 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507716966067149.52673803959658; Wed, 11 Oct 2017 03:16:06 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 242C721F3C190; Wed, 11 Oct 2017 03:12:34 -0700 (PDT) Received: from mail-lf0-x22c.google.com (mail-lf0-x22c.google.com [IPv6:2a00:1450:4010:c07::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 17FDC21F3C18B for ; Wed, 11 Oct 2017 03:12:32 -0700 (PDT) Received: by mail-lf0-x22c.google.com with SMTP id g70so1494982lfl.3 for ; Wed, 11 Oct 2017 03:16:02 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.15.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:15:59 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22c; helo=mail-lf0-x22c.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dDbcHj9oSEcsWj6JvTpjYMEqhFOEBf+iGfpOKk8RSzo=; b=XcRnYAD6nHExswqVvSsiCYT526DV7B5czpCOO3T1ZUPHS1gcF9lqle3qrGNdgcqnUo fqlVzM/hHuzeYvmfJHKLPjt4OFBDylUM+QAgvYC/4puv1Yu34XMbsGVAHwvH3cvMlhYS qwdk0i9Pe6p2pVlUtIONP0QIFyozQwGgaz/ZnHs/VtMySgHCle7hZerwx9RD8jRF5Jyc 5bUZRVDjsdR0NhjdkGUiC6WW1+gr/k6xG5Mlah6gayTAPmoPgegLqG63boOzDGoEKL0n n/M2aifkBzSE4aZVBvwf2kR4CvpR5/SoyhWPJbte8bWLvi9OM/cyzsCIWZ4mMiqKWhdr bVPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dDbcHj9oSEcsWj6JvTpjYMEqhFOEBf+iGfpOKk8RSzo=; b=SnY7uolArvrY3mAHpfhMwGpuB0lABbL8gNIlB2X5He3cmBqMe+zcKIr0tftvsuyBjM tkuQOg8hPrK8mS6J23UoZaAi3sM6Vdwzg1LB/LsC0CZHybLSJVMBKmoaLXZmMpblyYOS RQmCDcTvL1pPk7beEHZyevHxRQefVxp+MBUCnbN5RTG35xa0IXhrb5o+iSCynEmclIVw 9ML1hBNp/4BG1ryJTk6psfwQU41up53V/LrnMSjaB8naaGTjc+9P1YeoClSTNc1f+muK o5goFa46CiWrUS4s0y3s+oJJmyY3XlznX3lC4CTPbXjsDWxTYUF9ShedFAOBnKcTYhrx uTlQ== X-Gm-Message-State: AMCzsaW5G72qzj+0GnedgSMCGrvW+Uf5sHPc/wIkcOjinS9rA04P6Q4m VBJUwGde6n/7/qIq4BvTRs4Q5++11v8= X-Google-Smtp-Source: AOwi7QA1hnXD9jEnjUnGBu+FNnCqxCIYoDJH41LkTwxvjtD7n3BRhPSL0WYZMGhtYAViyQcP8GQUPA== X-Received: by 10.25.228.1 with SMTP id b1mr5995978lfh.23.1507716960239; Wed, 11 Oct 2017 03:16:00 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:29 +0200 Message-Id: <1507716939-31798-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 02/12] Marvell/Armada: Switch to dynamic PCDs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel For full functionality, including HII forms wired to non-volatile UEFI variables, we need dynamic PCDs as well. So let's enable those. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 10 +++++++--- Platform/Marvell/Armada/Armada70x0.fdf | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 417bb0c..433892e 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -67,8 +67,7 @@ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf =20 - # Assume everything is fixed at build. do not use runtime PCD feature - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf =20 BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf =20 @@ -150,6 +149,7 @@ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/Pre= PiHobListPointerLib.inf PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf =20 [LibraryClasses.common.SEC, LibraryClasses.common.PEIM] MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf @@ -368,10 +368,14 @@ # DXE MdeModulePkg/Core/Dxe/DxeMain.inf { - PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Gu= idedSectionExtractLib.inf } =20 + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + # Architectural Protocols DXE ArmPkg/Drivers/CpuDxe/CpuDxe.inf ArmPkg/Drivers/ArmGic/ArmGicDxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 763d76a..b3d1c60 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -95,6 +95,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1b3= 0c INF Platform/Marvell/Armada/Drivers/PlatInitDxe/PlatInitDxe.inf =20 # PI DXE Drivers producing Architectural Protocols (EFI Services) + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507716968908528.558458189259; Wed, 11 Oct 2017 03:16:08 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 5DB1021FC7475; Wed, 11 Oct 2017 03:12:36 -0700 (PDT) Received: from mail-lf0-x236.google.com (mail-lf0-x236.google.com [IPv6:2a00:1450:4010:c07::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2B74A21EA15D8 for ; Wed, 11 Oct 2017 03:12:35 -0700 (PDT) Received: by mail-lf0-x236.google.com with SMTP id a16so1499884lfk.0 for ; Wed, 11 Oct 2017 03:16:04 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:01 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::236; helo=mail-lf0-x236.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4kB0WtZ99414zik4Tx61FAcKtHMMNOTx33aTZ2ghG5s=; b=mAWd+FG7Z/Wu4ZNG+g3+Xu9/pDzqHl16tbQF7gDPJx/tfLjtDnlZTmsuvFgjSV5Kle wLRPQELdc71+oOudaXyDomhuP8k3A3Hu7ATBXUyY3bpBVGR8LmNl9n3jnYKC30tOIb8h u7KrdwVhvsn0WDsEl5jb39gfCio5IPPos+MGfuFK+hfo7pFB2+YC8kU/oOxswIClhUFm Bd0RuaUdl5gjjXOkhE9s4pmJhhfeksSDrNRQqYDuh22fzBLcILkAjLlIjEEbVCEpibSn wL1UzWXY1fL2GZ+9+ffWCrsRfbtoKvkd6amjd1E2vndxcRP8hj2Tva1NvGZoBINtbIlw m4eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4kB0WtZ99414zik4Tx61FAcKtHMMNOTx33aTZ2ghG5s=; b=i/9m6osgObJ6Gv2UYKKLqM4qIGVgoyWiSBdsXXuLzOajAKvK9B8U4PzMF1gwOzJFdj ClYSnJZJROT272OVICDzZaIleX/qO0yhOT3gbeUzlE2yVtZ4UyYy6BUl+Psm8QykXDXK DXF6bxw5gdbYI6e+zvXNJj5KrUGB3ga7UwsfOH9qKzaXJEdEIuquxUBFhegQZHVdINVp gDgjixcyKFSskiFuORokaFWcZEI5Cam2mQ9VmHgqi3idoM5uAzOh6tJhgOCFw1r/wZlO wEjvY/XDFOk5jMOp65v9BKgdzFc/4exzB3uvAnLZxQIIM9+d/P6SJtkygZYdnvpN7xbx CgKQ== X-Gm-Message-State: AMCzsaVvb2zcmTF2n1DW0tssBX8kN0kVn9w7yq5ehlbxYybxztrE4tvJ Vy6tYuTErc//KDH6SmcoscheAxbfNfI= X-Google-Smtp-Source: AOwi7QBA/8zAFXVigvHCnJ8ktLO/T6DM9GqZSsh3ZHkzoQoTkOhoKCogl3FLa/yBqbUB38ePohA/hA== X-Received: by 10.25.77.75 with SMTP id a72mr5784686lfb.262.1507716962558; Wed, 11 Oct 2017 03:16:02 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:30 +0200 Message-Id: <1507716939-31798-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 03/12] Marvell/Armada: Armada70x0Lib: Terminate call stack list at entry X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel To avoid dereferencing junk when walking the call stack in exception handlers (which may prevent us from getting a full backtrace), set the frame pointer to 0x0 when first entering UEFI. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelper.S = | 1 + 1 file changed, 1 insertion(+) diff --git a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatf= ormHelper.S b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlat= formHelper.S index 9265636..72f8cfc 100644 --- a/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelp= er.S +++ b/Platform/Marvell/Armada/Library/Armada70x0Lib/AArch64/ArmPlatformHelp= er.S @@ -16,6 +16,7 @@ #include =20 ASM_FUNC(ArmPlatformPeiBootAction) + mov x29, xzr ret =20 //UINTN --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507716972206126.37485167022828; Wed, 11 Oct 2017 03:16:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 99AE721FC7487; Wed, 11 Oct 2017 03:12:38 -0700 (PDT) Received: from mail-lf0-x22e.google.com (mail-lf0-x22e.google.com [IPv6:2a00:1450:4010:c07::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 803EF21EA15DA for ; Wed, 11 Oct 2017 03:12:36 -0700 (PDT) Received: by mail-lf0-x22e.google.com with SMTP id c82so1485827lfc.6 for ; Wed, 11 Oct 2017 03:16:05 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:03 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22e; helo=mail-lf0-x22e.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9ZrWZyQ5ZafqO4LV0B47zKmpbv4zRwnmPrs2dc1FoKE=; b=xsHNMkeT4bxUaOrAgehZi57XBvwJ8Z7sp0DTeyQHrqRuWygShIlzHLyws05c6mF4sM pabuWyr5g0nibhSyVbfJTefl2Em6gqFxTbjctsfb5LMj4JkGKQiMdkTS8WSeO/6SV698 woXL40a9eDc0p2Wmy0kUv8i/Yt9+5BCToIds8kA+bdmvbdtIE4H5JC2IYfMbk5/JWMl8 f3YgMT/yTss0yRydyhlCPDg+z6HyhKt9yAQX1ZNVa6aTeBPzpTtMtMbr9vuGWr8QyRnF F0RNHR6Y71KkzdCCysKZQpis2qgFXPlwW79ktpPmMq+rAYkvOF2jHQwqBEW1nzH3SaaJ Rajg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9ZrWZyQ5ZafqO4LV0B47zKmpbv4zRwnmPrs2dc1FoKE=; b=R1cBF14dwNT+J9qqOckCLVZrD9wuolseM2fPBDjN8nXu8LiP8hZGWzT8xmIskMWg6T XacDKuNjm40aoKZC0VckV1FMckkzsOYr50NnBAdHF0ZhPA7ruWNOaAGdy2e2/m72rgB8 o8kk/DTtGnIVsI1JbbEB9fy0PQEv1wsFYEOTxUaCPTj5162kbfhH0zR1Tsc1m1btR9VM b45EUMhcECMXK6PM4uvI6EplGc5Q66EWUtstCuIDSU6+KJtBNZ04GFB19itJifnE5RVL 7eK+vxwKy4GCnlVWSum7lF6kqEV87J2K3h7o4SBbVYwFcQmDpig/0hcvLCADK6cWxow1 hZ4g== X-Gm-Message-State: AMCzsaX3smg0mUKGvGtnbKNDkxDC36xN0MCMeqV/MhVBKnpgwzXAGwr3 PxAgz8PPGNbA0JY+NuTDEVby6VTOkNA= X-Google-Smtp-Source: AOwi7QDgn/HGCnLtu6zSlaTJR+drDGblvqPXWli/IdndJ5CSu4/rhTmBL7nom9KCXYSVy92CCfIaCQ== X-Received: by 10.25.80.68 with SMTP id z4mr5859102lfj.112.1507716963851; Wed, 11 Oct 2017 03:16:03 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:31 +0200 Message-Id: <1507716939-31798-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 04/12] Marvell/Armada: Use 4k/64k aligned sections for DXE/DXE-rt modules X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Enable strict memory protection at boot time and under the OS, by using 4 KB section alignment for DXE_DRIVER, UEFI_DRIVER and UEFI_APPLICATION modules, and 64 KB alignment for DXE_RUNTIME_DRIVER modules. Note that the latter is mandated by the UEFI spec. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 433892e..1b4e713 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -486,6 +486,12 @@ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 } =20 +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,B= uildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICA= TION] + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x10000 + ##########################################################################= ###### # # Defines - platform description macros --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507716975450489.342901754345; Wed, 11 Oct 2017 03:16:15 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D4D7C21F3C181; Wed, 11 Oct 2017 03:12:39 -0700 (PDT) Received: from mail-lf0-x232.google.com (mail-lf0-x232.google.com [IPv6:2a00:1450:4010:c07::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E5B2A21EA15DA for ; Wed, 11 Oct 2017 03:12:37 -0700 (PDT) Received: by mail-lf0-x232.google.com with SMTP id r129so1488644lff.8 for ; Wed, 11 Oct 2017 03:16:07 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:04 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::232; helo=mail-lf0-x232.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ERF9HvlYQnMbUGuFfMQwRjWyGHd1d9LCnLFZMee85d8=; b=EbJVVZQzTcC2oFWixgi9s5MjTvDXR5/r1uBE32/5f+U8dfTH3irVAE5cZsV39NmUur mKAyd/0QEYkM4EIXQI5SKjpCn1OFmJ3v6FbBohCJJkaYUuHByZZqT1zJyYPvG1ObJMjY 942+z4e8m8RLWlcVb7TnWqrScfod1/LQpgLK1DbLpDuTVvamnFldLYRX7XsT62PzeIcM 2oSaRzxK3XwU7wcT33iiCyUXVQnUTrokEKy6h3EHeU1CeYViHMaRR4jZTeeNSPLxsqD+ jnJegcJoQToINMziMpRLrHx+IyzBmsf93PuFyGxtig8D/hF1SYikoOcIQeODf2CIrHIP 0JgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ERF9HvlYQnMbUGuFfMQwRjWyGHd1d9LCnLFZMee85d8=; b=ErlWWqO4lyInqj56snBhm1+O5QjazQwaZwBP0Fa13w1khqKbAJU6n9kb/Tbd18Qjqp QbmZVDxwYQipOsJiiYfvRz8g+fltRXotc1eV8X1qlHI8a1TSwO5H69MCJOIjurpP4OaN hFCn8F0qvRSIVBI/ve7unX/+7ZX1pSCgMoyaC9/KMVLjmV9qOxIX6vDWnf6zhSW8OuZN z799ce/XqQZo+KyBlE6b/44d3fQN+NrcByR1hq8pn9mA8Y9OwdEexB783XL5/WKu/sjR ODX8KuI44OL1BJ1DS+2+5t9QiciuIjtRp324zjRhsJuz+O3mRjKK4qXrAFMDoK0o3yRZ BRAQ== X-Gm-Message-State: AMCzsaWSAD0HWTv2CCBUJTFnRmG3Kujn1eJ82fmBpkr8JpXW6qlDhhtS GtoOkvDrER5qoBHaGeTupUf8oWydws8= X-Google-Smtp-Source: AOwi7QBSdYGalVjHXZ7Z665cg6pxZWw9xOozZWpsv5F5W81otRkX/+EIjT0JqCCujtm1LEKPWnNOww== X-Received: by 10.25.167.85 with SMTP id q82mr2539972lfe.171.1507716965114; Wed, 11 Oct 2017 03:16:05 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:32 +0200 Message-Id: <1507716939-31798-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 05/12] Marvell/Armada: Switch to generic BDS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Switch from the Intel BDS to the generic BDS, which is preferred for ARM platforms given that it is completely legacy free. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 19 ++++++++++++++++--- Platform/Marvell/Armada/Armada70x0.fdf | 3 ++- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 1b4e713..e920461 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -126,8 +126,9 @@ =20 # BDS Libraries CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf - GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLi= b.inf - PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelB= dsLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBoo= tManagerLib.inf CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf =20 @@ -350,6 +351,12 @@ # Shell. gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE =20 + # GUID of the generic BDS UiApp + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + + # use the 'TTYTERM' terminal type for optimal compatibility with Linux t= erminal emulators + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + # ARM Pcds gArmTokenSpaceGuid.PcdSystemMemoryBase|0 gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 @@ -459,7 +466,13 @@ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc= eManagerUiLib.inf + } =20 # UEFI application (Shell Embedded Boot Loader) ShellPkg/Application/Shell/Shell.inf { diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index b3d1c60..999b968 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -175,7 +175,8 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf - INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf =20 =20 # PEI phase firmware volume --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507716978413792.9258957916481; Wed, 11 Oct 2017 03:16:18 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 28E6221FCA260; Wed, 11 Oct 2017 03:12:42 -0700 (PDT) Received: from mail-lf0-x235.google.com (mail-lf0-x235.google.com [IPv6:2a00:1450:4010:c07::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 27B2B21FC7499 for ; Wed, 11 Oct 2017 03:12:39 -0700 (PDT) Received: by mail-lf0-x235.google.com with SMTP id c82so1485961lfc.6 for ; Wed, 11 Oct 2017 03:16:08 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:05 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::235; helo=mail-lf0-x235.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m8KAWlp6LUs9N3IPV6VxeR82nLZy7w1MQHPTJtwxjjM=; b=e6rThK2isDoRixk/H1n7SUBQCt1D78zkuk/wRPiStgPj2D7lDNs3BpsXa5TvIEHluG odzPZeActlEVUSURu1TL0He0Cnif9TtjkYVlgrfPOWJIvveFCctMBm5LIelRMUcZNL2t LlhpaLCziB+3wnH8LIYivDcvGHfXZbhbitp+Xftm0MMEzrZcPvVoOTf+NQCpkSXjyR0R 47dsXALrIs7T2zqnkfNW2QEZJNQPJH76fzi4VE307pyxoVM+itmc4lQrJxOlKtsBRTNO dCaHSidnRQ34wRR9JIeRBn4IsFWrjfVwpfC9vnx/2emFNPSxVRcO+Q8JNYU6qoFGoSjH I89Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m8KAWlp6LUs9N3IPV6VxeR82nLZy7w1MQHPTJtwxjjM=; b=SOMNbCYspl9Bq7hmORQldnkWfoqLwxeYIe/iUWbE+oFwgXh6dK5a2p7/v7OgBG6o5J ldStwzcXGq6pHRAI22ev5q1LHB2KeyI9CDW5oiJEquuQCRO9A7Vqamh6ru32IVm7awxk mlN/RIpzw8qSEBJvsugTH74fC4yvE+qzabFaOT+N9CP/1wSpuYHzryFGoOP89TpW3oQs vznJXeItNcvtetf6xZcP87glck4va+Lb+RZsvvNlOnwunu8sOzB228to54RxtNwlGPQ1 IPvVnns/gp/xEyP5k+sNEHssmB8gLmVfnNPwk4xmc3VP6oSMYoF5b8sGJmhZeYHPUuea RHgA== X-Gm-Message-State: AMCzsaUUfygN0B8c9VopgEO1ciksRi/MSgYNWg0SxtjXt2JvkVr0piey Rf9x0D6n+FHIR2GjZXAzzPEPBNiKd9I= X-Google-Smtp-Source: AOwi7QBlixr5LE+npaumS3BHjlV6O9WoosVtdOb0w3eldRrJWC9OdNIKPqpqHej4p14lZmpiBWgJDw== X-Received: by 10.25.149.131 with SMTP id x125mr5872916lfd.231.1507716966491; Wed, 11 Oct 2017 03:16:06 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:33 +0200 Message-Id: <1507716939-31798-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 06/12] Marvell/Armada: Re-enable driver model diagnostics PCDs X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel For some reason, one of the early ARM platforms disabled all the diagnostics related to the UEFI driver model, resulting in the output of UEFI shell utilities such as 'devices' or 'drivers' to become completely useless. Armada's shared .DSC include file inherited this for no good reason, so let's revert it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index e920461..5071bd5 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -207,10 +207,6 @@ ##########################################################################= ###### =20 [PcdsFeatureFlag.common] - gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE - gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE =20 # # Control what commands are supported from the UI --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507716981426140.23224302788105; Wed, 11 Oct 2017 03:16:21 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6A29D21FCA264; Wed, 11 Oct 2017 03:12:42 -0700 (PDT) Received: from mail-lf0-x22b.google.com (mail-lf0-x22b.google.com [IPv6:2a00:1450:4010:c07::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6857E21EA15DA for ; Wed, 11 Oct 2017 03:12:40 -0700 (PDT) Received: by mail-lf0-x22b.google.com with SMTP id n69so1496620lfn.2 for ; Wed, 11 Oct 2017 03:16:09 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:07 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22b; helo=mail-lf0-x22b.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TtztnqOEA+dqX1b9tOWUSOVeM+ZgsPTKBfHC+zwyRTs=; b=LcHESo4UO02gTdv7/0KXMVloz4s7svt5Oni6UnWluj+Jih7qR2+HfxrSa0gZlWDl+u imB8vHAIF0ZsDu/+/bkuXmEhBey0qLW+AaN6mWUHD9DgTYK7VRwiYmj3RN/jlQdL0wgI Hpzl56SfSgrGjeYY3T7yi96tXj7Cf7NsvztR97oo3FitWJzqTobAKA5PXn++pOqFBkBV L7H73nblpDWKw+CpKU9BI2sZJgVZlWl/Cv0YRfm8V34dW+ozseTTvJOSCWlHbO/Eh1sK YYk91f2Bvt96BQoZlPjq9xACFvSdG5oCS06mK5IyutQKmHvOBPVoxFpGSTpJoUNU+35d 6hfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TtztnqOEA+dqX1b9tOWUSOVeM+ZgsPTKBfHC+zwyRTs=; b=UrOKxpDhKmyszbTXChC32AVlUMFqLRyvEsDbPLePPiLLRFNZq5DEIpRQMwJvnMOTOP yx1WR+zhwpR3Cb2mSIkrUqKvF7oTckUTf1nRvqxjYAFkc/s5xf2iQoNe5AyNb065EF46 Kc2Xztr/trMAxd6YEm4rdxvJKaPPWCtL/5wnA6YwwMLDHl1e2DtPPjeCRcB05SowV1jj coktMvilVu5RU1C87lrgG+3N3lszSTgdt5smHG7cDkqDFs2nCAIL/aXrjgTUVuVfBRW/ OKfKkF5Cx9apIkmU8X7LUuMZWD1M3FhADa5OacAj7si0stEXvWJ8Y19042Wicm6MgZ/U ZyWg== X-Gm-Message-State: AMCzsaVdloD4WCXEL5eh18c/V6VktJnAeBdWpJVB78rCBc4P+1oTCvrQ oHL2EUL01jTg3JpjvowBU3SSSTJEgFg= X-Google-Smtp-Source: AOwi7QBCci67uWsO99V00Gm9Y6nAuWrcvwdszkcWqQetl/yzuunc5v5GZ2AWgMidozx1ZCP30X1zqg== X-Received: by 10.25.145.88 with SMTP id y24mr3045651lfj.5.1507716967738; Wed, 11 Oct 2017 03:16:07 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:34 +0200 Message-Id: <1507716939-31798-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 07/12] Marvell/Armada: Ensure GICC frames adjacency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The GIC architecture mandates that the CPU interface, which consists of 2 consecutive 4 KB frames, can be mapped using separate mappings. Since this is problematic on 64 KB pages, the MMU-400 aliases each frame 16 times, and the two consecutive frames can be found at offset 0xf000. Therefore use the last alias from the first series of aliases as the base address, so that the first frame from the second series becomes directly adjacent, whilst remaining covered by a separate 64KB page. This patch is intended to expose correct GICC alias via MADT, once ACPI support is added. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 5071bd5..bd2336f 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -263,7 +263,14 @@ =20 # ARM Generic Interrupt Controller gArmTokenSpaceGuid.PcdGicDistributorBase|0xF0210000 - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF0220000 + + # + # NOTE: the GIC architecture mandates that the CPU interface, which cons= ists + # of 2 consecutive 4 KB frames, can be mapped using separate mappings. + # Since this is problematic on 64 KB pages, the MMU-400 aliases each fra= me + # 16 times, and the two consecutive frames can be found at offset 0xf000 + # + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xF022F000 =20 # ARM Architectural Timer Support gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|25000000 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150771698457593.23500003138122; Wed, 11 Oct 2017 03:16:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id ADE8D21FCA269; Wed, 11 Oct 2017 03:12:43 -0700 (PDT) Received: from mail-lf0-x234.google.com (mail-lf0-x234.google.com [IPv6:2a00:1450:4010:c07::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C933521FC749B for ; Wed, 11 Oct 2017 03:12:41 -0700 (PDT) Received: by mail-lf0-x234.google.com with SMTP id b190so1483776lfg.9 for ; Wed, 11 Oct 2017 03:16:11 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:08 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::234; helo=mail-lf0-x234.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cqOqsdTHi7f2ZH4BL8++104Hl0ZT235eMVz9wpp88c4=; b=g5+RRJ+VEbR/KvY07NMsmXw/iL6m9lBvlA846vMmMzmUQiENz55r8Cd7jef0U1ZWM4 ka5vvvWbetBeQgDS/1SLbtQi+xsrHM7KbdB04xC9ecxjbAWlXR/zu4tioHIK/Den5xUh kmLGfKfRHXJ5nKCkIW4JyrRL9Izh7nf61N9R8ele4Jw1JznQzK9IxfkvSRga/RWq0WtN tc8ZEnA+4RQRGqRv343c3QtBjAsTyxH8rRobzI5NfBS8x0qZs8vJTf8lgtEPJZPVFc1x W5nGw4eNI6R1U87s6/PteUtTn+tguhGUz04t+ft9ufWAIed0+ZUFzKnpRcHnsNcHq1mn vmgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cqOqsdTHi7f2ZH4BL8++104Hl0ZT235eMVz9wpp88c4=; b=ZplrIuYi+Yo4QQL8VlG8hTRMHd+bHguQYeRd6Y9MPdshc0Q4H5AeHIo5dhhyPgl+Lw XbkOIfLjl0nJ3GZXUjNhBxs3oRHCgPMGJ6PRE7/n5f7z8YFNoPX7BSfCUv8ehdlJSD+j G5/1oeIRsIbgbciKNgKYPnGpjk1JfeIOW1RL8OYd3XxRtYtROfHdEOfngvlR65FjpBue 8zerp8mlME2003acC7RHsdDcfmUPQAM+CTiSwwIzCY26N3D4favXoVSw6e2ot+aOS1tA Y/yPEfSmsxQFgOAs8gXk9LcJLMbwi9kpb8fOOlRavjGWDUNuHW6Ja4ScqQomLzX6LnV2 lstw== X-Gm-Message-State: AMCzsaXbGx3TQxm3K6C6QEWUBPXVarVx6kP+2xtr9hEIkpIjT1CgRqc0 PwRhFiEpid394HXrFDbe5JjjWqL4VDw= X-Google-Smtp-Source: AOwi7QBPvVgjdKClSOxFTaixbq0bY5hvl4QdxzKmYZmeC5ge7sTS2t7/VBlDpoYC2zc2oPnqEZbvUw== X-Received: by 10.25.156.66 with SMTP id f63mr5985798lfe.194.1507716969155; Wed, 11 Oct 2017 03:16:09 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:35 +0200 Message-Id: <1507716939-31798-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 08/12] Marvell/Armada: Disable PerformanceLibrary X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Remove the gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask setting so it reverts to its default of 0, and disables performance profiling. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index bd2336f..b718c60 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -251,7 +251,6 @@ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|1 --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507716987692163.50443839855836; Wed, 11 Oct 2017 03:16:27 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id F274321FCA26C; Wed, 11 Oct 2017 03:12:44 -0700 (PDT) Received: from mail-lf0-x22a.google.com (mail-lf0-x22a.google.com [IPv6:2a00:1450:4010:c07::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2685B21FCA267 for ; Wed, 11 Oct 2017 03:12:43 -0700 (PDT) Received: by mail-lf0-x22a.google.com with SMTP id a16so1500245lfk.0 for ; Wed, 11 Oct 2017 03:16:12 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:09 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22a; helo=mail-lf0-x22a.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EuvaJb6WbBALFDBu5fNnp1n9u3rNea3sjT2zvkgbmhw=; b=JwvilVQtiXbcZSfHvbQ8CHa/UL1hV9nQHzjv6fhf4SyNBgGnq0n/vKus2/gJcy2G8v 7yKEXGTe0Dzpszmixn/cSUpeXDdyACWMwEFl6bTFlhH3/juHHNsA85DkWf3R3vuvivEM HVI/aRAIptpubgf4zr+DXsPQygBXBf/or+L9H6QfRGjp6TUq1RyjtmtCeCnaLsR3137F Q50/eYIwPwcavUlADg7UbRMD6pYqPPs/riteH004cKgaSZT28tJht0ZXSZrcFVOfowHh i6H4wwKH2x3+RbA4rEEvO51iibd6v5wProrDjDa0+OJ7MPbRheFaBHH5nFKz45hm5nYw QX6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EuvaJb6WbBALFDBu5fNnp1n9u3rNea3sjT2zvkgbmhw=; b=kPd6Sd5uqpBslT6I8ZosQWNN4/WbP0+21blPILC8/xa48ZA80aZc59OZcv/3/E3xkm sks0OQx2OgFC0+0ejVMYEvSeKtHev8K9l/ekOtgUcJHKDFR+ONT8M/wNTwkhz1HlmCc9 cewn8kS3FZwpC4fCpbWCd1Rfpe6/gEXOAglnZQJ+4dPW33rJlNx144kLuI2YAb+o4Ezy bjmatxhY274MlfOrgdfyawQ+kq4ONBwIVsKQhbBRu7UFanqdTsV3gx89FGEaNAgSwlDj Y26K3dPaIk7nJI0IOe4/MRcvPIiBzs/YoJySwwoE7vMl1ObYIsvvCEZeInvFS7wVnfPc WU1w== X-Gm-Message-State: AMCzsaWRb4HSTkyM0cZeKqWwOOBfHxTvY10Ps6S53ACkOkqkp5Eyvh8P s8RtgcRTo6jNv4Xx9qdGJWNgEZ4IIbY= X-Google-Smtp-Source: AOwi7QDJ+LZnunoabI88sHJy+XRvVpXZKvAZBWX5piPeGjywp7yPadkiy93TXsYqdAMO54JTCzJcfA== X-Received: by 10.25.212.213 with SMTP id l204mr6551481lfg.59.1507716970455; Wed, 11 Oct 2017 03:16:10 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:36 +0200 Message-Id: <1507716939-31798-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 09/12] Marvell/Armada: Switch to unicore PrePi X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel There is no point in using the MPCore PrePi, given that only the primary core will enter UEFI at EL2, and the secondaries will be held in EL3 until summoned by the OS. So use the unicore flavour instead. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 2 +- Platform/Marvell/Armada/Armada70x0.fdf | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index b718c60..5a5fde9 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -372,7 +372,7 @@ [Components.common] =20 # PEI Phase modules - ArmPlatformPkg/PrePi/PeiMPCore.inf + ArmPlatformPkg/PrePi/PeiUniCore.inf =20 # DXE MdeModulePkg/Core/Dxe/DxeMain.inf { diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 999b968..2c3efe0 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -199,7 +199,7 @@ READ_STATUS =3D TRUE READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE =20 - INF ArmPlatformPkg/PrePi/PeiMPCore.inf + INF ArmPlatformPkg/PrePi/PeiUniCore.inf =20 FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150771699069784.15463585861721; Wed, 11 Oct 2017 03:16:30 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3CC6E21FCA270; Wed, 11 Oct 2017 03:12:47 -0700 (PDT) Received: from mail-lf0-x22d.google.com (mail-lf0-x22d.google.com [IPv6:2a00:1450:4010:c07::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 01C8C21FCA26D for ; Wed, 11 Oct 2017 03:12:45 -0700 (PDT) Received: by mail-lf0-x22d.google.com with SMTP id a16so1500348lfk.0 for ; Wed, 11 Oct 2017 03:16:14 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:11 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22d; helo=mail-lf0-x22d.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=POj5weXKwfA+/p7iQaRlOOoa7CzAGD191BV9H6yL8b0=; b=o/iRPDuNZNeBGqE53GWyZAajaA1LBBCib/8Otw3SW8glpoVMzdbuodzZjRTlKELSku oqWgsBzSlMvsXOpCM8ldrSx16Jd0XIfLU2yIHJWHv8GD0at2jt7yzotOsYtR3Qd+meAW 7eI83Wx6sQLPkMC0V72c4jIMJrSazRdS0/cN0YB95x7PNmqB5pC04ftZsFWfARb0z2wm 0nv0+uzrY1yUQPiwZNh1PNYQ298du++4XlPrUlX3YwJYct3cIdw0dA5Xv94SFpliyToy yXjf+NLcWF/3RozKVGu4om3zu41oqCCBHhAQdIi4CHSPl6zZicsERdluq4cHb3C6Qh1m OFDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=POj5weXKwfA+/p7iQaRlOOoa7CzAGD191BV9H6yL8b0=; b=AeCxSWfs98OsyjQU7LhNMWJzezcfXJ5Q9mVT1GGcd7wNqt63F+Cw3FxBMdLk+Q83ld F/qX0t7xx6YX1wsAnRW8Y20E/eYFLq9lsRzHV5b301oqbkFWBZAO1imbsELJHpgUcTlw rtyWlp0zKeD3Zlvt2+Kkltjq2huS0dlTlP+fQ9fCv8TMhJypowElYvJPQdFh2kusNQGO jZl481oBcZ2yq1jrKwrnce82vvo6SdE/RNScyXa/Svum8Tsg8AmTtx3bnaHODRde48Er vK1ohjFlumWxHHBS7S7xb4Dtt7WXiwtr25BEbeURp3i43BSGCKPclBW4WjScFVXPLMLw Rx/Q== X-Gm-Message-State: AMCzsaUKh1E1whjL7cwn73bzaalR8aj+D0lT7wj5Z3WrY5cbnWUb7s83 zJYBRuXvYydPjJTYlUMiOog5wjdusdI= X-Google-Smtp-Source: AOwi7QA/5RqRhaJYcGxLJElcME6kkytZ/aEbKl9+u0n3RXZBjrP9HYGDUpWZ6oP1kbGNAcYw/wk8rg== X-Received: by 10.25.161.208 with SMTP id k199mr6039665lfe.110.1507716972254; Wed, 11 Oct 2017 03:16:12 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:37 +0200 Message-Id: <1507716939-31798-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 10/12] Marvell/Armada: Remove outdated SEC alignment override X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel The FDFs no longer require explicit alignment for sections containing aligned objects, so change it to 'Auto' and FIXED (which allows some padding to be removed), and remove some other cruft while at it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada70x0.fdf | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 2c3efe0..3f0471d 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -235,16 +235,9 @@ READ_LOCK_STATUS =3D TRUE # ##########################################################################= ## =20 -[Rule.ARM.SEC] - FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { - TE TE Align =3D 32 $(INF_OUTPUT)/$(MODULE_NAME).efi - } - -# The AArch64 Vector Table requires a 2K alignment that is not supported b= y the FDF specification. -# It is the reason 4K is used instead of 2K for the module alignment. [Rule.AARCH64.SEC] - FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { - TE TE Align =3D 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align =3D Auto $(INF_OUTPUT)/$(MODULE_NAME).efi } =20 [Rule.Common.PEI_CORE] --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507716993800894.0825809785738; Wed, 11 Oct 2017 03:16:33 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 7437121FCA276; Wed, 11 Oct 2017 03:12:48 -0700 (PDT) Received: from mail-lf0-x22d.google.com (mail-lf0-x22d.google.com [IPv6:2a00:1450:4010:c07::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4959F21FCA267 for ; Wed, 11 Oct 2017 03:12:46 -0700 (PDT) Received: by mail-lf0-x22d.google.com with SMTP id a69so1496732lfe.5 for ; Wed, 11 Oct 2017 03:16:15 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22d; helo=mail-lf0-x22d.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2I4C8QdJzwenrvW5qaKaiovMdUK5FyBcx+NH68kf6gk=; b=QgPXkKGuyrfDjrUOGH0r6ECh3SWksaxvWYgDCWhOHyDNu849MZMc+0vkOYA6co+su1 8jPrW8bih2Ipx1AYUk8+my3rBaJXNg39x5MGV/C3C/u4VECSzV1+wjJ8JttQoGsSP3jT Wvvah4cY3AJU3bByaNT609Ctnx5he+3Iz51i/fkZxqNnzo31qtnH9ZnAZPO5C0OYjNGB yy89ZVC11jLRdiokcRDLu63hypLMxYH2teQzrW4ve2eq+9VJNYkqkv7FCBDz+berzfE6 LdvXYczX3cxxG3E24Owl1e3nDXMLRb30T8eiL2G9w5jX8baOatnMJeILU4JZoI1MRD0/ 04Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2I4C8QdJzwenrvW5qaKaiovMdUK5FyBcx+NH68kf6gk=; b=oHnTUMFvm7UlkPHa2QOVnezQ1HQMWqXwi5eIw3k7Z4KMHiO8BjUPM8BfcKLnRmgvN8 TvuAFltvnuf0YGiXEUIaTSdRBFtqqj4tZ2WIHEufqBmYAfKJAPUhADgDpH80+iHsOFmT hPOVGs7kgtxL4h4ygCgC+xLCjVpO7Co0xd7ejtTYURCYZjKRpWNyWq2cBN1KORU4j4XV 5WXgY6rEcT4q93lNVwP1ls5v/qyNU+i/cYjpfYBT+y8aV/ER5G83rradUpDmxc21Oynl uAJXueqV9ShUEfjgjKsk7YCJtYZEZNg5UWEoWJBTrwCHVCvPxyu6CgkuxfNI3pChygFi AL6Q== X-Gm-Message-State: AMCzsaV8bqZqjmUSBkbxNcUbJRdVhtqBVjarSXj8otj0ItL5LB2/n13T BdyH/4JI7YHLvwqa8GoWgf0E5K0MisU= X-Google-Smtp-Source: AOwi7QBjHDaEJ3O2qBmUk7fD1hqehLW9C6DTrK2G741lhHJdVdidXjhsBS1OMcRSpwBR/irsnV7uIg== X-Received: by 10.25.90.81 with SMTP id o78mr6009154lfb.80.1507716973694; Wed, 11 Oct 2017 03:16:13 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:38 +0200 Message-Id: <1507716939-31798-12-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 11/12] Marvell/Armada: Add the UefiPxeBcDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel This driver allows automatic booting via the network. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 1 + Platform/Marvell/Armada/Armada70x0.fdf | 1 + 2 files changed, 2 insertions(+) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 5a5fde9..1aa485c 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -412,6 +412,7 @@ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf diff --git a/Platform/Marvell/Armada/Armada70x0.fdf b/Platform/Marvell/Arma= da/Armada70x0.fdf index 3f0471d..933c3ed 100644 --- a/Platform/Marvell/Armada/Armada70x0.fdf +++ b/Platform/Marvell/Armada/Armada70x0.fdf @@ -125,6 +125,7 @@ FvNameGuid =3D 5eda4200-2c5f-43cb-9da3-0baf74b1= b30c INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf + INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf INF Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf INF Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf INF Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon May 6 19:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507716997022789.1924863343204; Wed, 11 Oct 2017 03:16:37 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B19B421FCA26D; Wed, 11 Oct 2017 03:12:49 -0700 (PDT) Received: from mail-lf0-x22f.google.com (mail-lf0-x22f.google.com [IPv6:2a00:1450:4010:c07::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5D13121FCA273 for ; Wed, 11 Oct 2017 03:12:48 -0700 (PDT) Received: by mail-lf0-x22f.google.com with SMTP id 75so1505120lfx.1 for ; Wed, 11 Oct 2017 03:16:17 -0700 (PDT) Received: from gilgamesh.semihalf.com (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id 84sm1539781ljc.67.2017.10.11.03.16.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Oct 2017 03:16:14 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::22f; helo=mail-lf0-x22f.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=R9w0t1nsyj+t+Is8Pw/MaUc2NrJpopvmY7cyYHekP1E=; b=1Vid5hkBiQ0TvvRyB1MA2fU3EalazU2Sp9YKTaDz9iAR294SHLJhYUnszzGn24gGI6 vr73R76uKig47Y701pDI3MQVvn7Gh6I2YULDbvXFXghvy5SdNwYuqbgYK6YFrRY0Z7wr 43ay71wixOrJ1M2rcbCcUpn6q1I/cHyVthP1zLtNmAfvsvruY+kYPeXPQMTrZo9RgXWT StKBvJsY9+JYjS6Xkbsuo47kt7fXLpWFlc1JdE7p2GzQW1B3fm9LlcE/bAzs8NTyjUZu Ht/MTyf+WOfMuvXnUwHHleCqG2e7GJWr/cGLV6uyRYUgtO1KcTN2KHLyZCxALMmGc0TU J5NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=R9w0t1nsyj+t+Is8Pw/MaUc2NrJpopvmY7cyYHekP1E=; b=A98LKYxxrySgt1KYGcJDbHLzckrv56TtmopJtcU7XW4dsWoyX49tIiEg6C6GxMhyZo 6UAZWcOVMlRr5gKnmwiDdhpSSzX6AFOA6mcquHMiJTl30urop6auxWfUFEiynYQwJxoy doHm3143Q4piS1NLT643BMsZLeWq7/1H7aibfPybm1EucVddL2yt45BE6wUyfKn9fcym gfNWbZb+hD86XtdpAQp109Dft1dESh7+PxgExpxCPMJASpzP24ehBeIuVgI7U4u8fJZL XEYDvjlSoBjbjk+wYSAG3/l+FKg6dqUmJQ5fUB04oKxURb9Kkqv357o0tc0Cj/puP7pO 4u8Q== X-Gm-Message-State: AMCzsaUMA5n0D40V5mON6Kvfgx6oQvpx0JeeXxeXd29amGSCFCGVbF1L spi04pDBsoJXYSG78GDg9jYugDxN20U= X-Google-Smtp-Source: AOwi7QA7htE3DNhNwpLMTZ2JSAKfQwqZ00dLseTjdZT/DfTms/HfvXGM3+hsuv+TlllYvtyoebemTg== X-Received: by 10.25.33.2 with SMTP id h2mr6668767lfh.75.1507716975052; Wed, 11 Oct 2017 03:16:15 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Wed, 11 Oct 2017 12:15:39 +0200 Message-Id: <1507716939-31798-13-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507716939-31798-1-git-send-email-mw@semihalf.com> References: <1507716939-31798-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH v2 12/12] Marvell/Documentation: Follow EDK2 coding style in the PortingGuide X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch removes tabs and wrong line endings in the file, maiking it acceptable to the PatchCheck.py script. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Silicon/Marvell/Documentation/PortingGuide.txt | 800 ++++++++++---------- 1 file changed, 400 insertions(+), 400 deletions(-) diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index f0da515..66ec918 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -1,400 +1,400 @@ -UEFI Porting Guide -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -This document provides instructions for adding support for new Marvell Arm= ada -board. For the sake of simplicity new Marvell board will be called "new_bo= ard". - -1. Create configuration files for new target - 1.1 Create FDF file for new board - - - Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70x0.fdf = to - edk2-platforms/Platform/Marvell/Armada/new_board.fdf - - Change the first no-comment line: - [FD.Armada70x0_EFI] to [FD.{new_board}_EFI] - - 1.2 Create DSC file for new board - - - Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armada direc= tory - - Insert following [Defines] section to new_board.dsc: - - [Defines] - PLATFORM_NAME =3D {new_board} - PLATFORM_GUID =3D {newly_generated_GUID} - PLATFORM_VERSION =3D 0.1 - DSC_SPECIFICATION =3D 0x00010019 - OUTPUT_DIRECTORY =3D {output_directory} - SUPPORTED_ARCHITECTURES =3D AARCH64 - BUILD_TARGETS =3D DEBUG|RELEASE - SKUID_IDENTIFIER =3D DEFAULT - FLASH_DEFINITION =3D {path_to_fdf_file} - - - Add "!include Armada.dsc.inc" entry to new_board.dsc - -2. Driver support - - According to content of files from - edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt - insert PCD entries into new_board.dsc for every needed interface (as li= sted below). - -3. Compilation - - Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change - {platform} to new_board in order to point build system to newly created= DSC file. - -4. Output file - - Output files (and among others FD file, which may be used by ATF) are - generated under directory pointed by "OUTPUT_DIRECTORY" entry (see poin= t 1.2). - - -COMPHY configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -In order to configure ComPhy library, following PCDs are available: - - - gMarvellTokenSpaceGuid.PcdComPhyDevices - -This array indicates, which ones of the ComPhy chips defined in -MVHW_COMPHY_DESC template will be configured. - -Every ComPhy PCD has part where stands for chip ID (order is n= ot -important, but configuration will be set for first PcdComPhyChipCount chip= s). - -Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes -settings for this chip. Their format is array of up to 10 values reflecting -defined numbers for SPEED/TYPE/INVERT, whose description can be found in: - - OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h - - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes - (Array of types - currently supported are: - - CP_UNCONNECTED 0x0 - CP_PCIE0 0x1 - CP_PCIE1 0x2 - CP_PCIE2 0x3 - CP_PCIE3 0x4 - CP_SATA0 0x5 - CP_SATA1 0x6 - CP_SATA2 0x7 - CP_SATA3 0x8 - CP_SGMII0 0x9 - CP_SGMII1 0xA - CP_SGMII2 0xB - CP_SGMII3 0xC - CP_QSGMII 0xD - CP_USB3_HOST0 0xE - CP_USB3_HOST1 0xF - CP_USB3_DEVICE 0x10 - CP_XAUI0 0x11 - CP_XAUI1 0x12 - CP_XAUI2 0x13 - CP_XAUI3 0x14 - CP_RXAUI0 0x15 - CP_RXAUI1 0x16 - CP_SFI 0x17 ) - - - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds - (Array of speeds - currently supported are: - - CP_1_25G 0x1 - CP_1_5G 0x2 - CP_2_5G 0x3 - CP_3G 0x4 - CP_3_125G 0x5 - CP_5G 0x6 - CP_5_15625G 0x7 - CP_6G 0x8 - CP_6_25G 0x9 - CP_10_3125G 0xA ) - - - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags - (Array of lane inversion types - currently supported are: - - CP_NO_INVERT 0x0 - CP_TXD_INVERT 0x1 - CP_RXD_INVERT 0x2 - CP_ALL_INVERT 0x3 ) - -Example -------- - - #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_H= OST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $= (CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } - - -PHY Driver configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. -Currently only 1518 series PHYs are supported. Following PCDs are required: - - - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg - (boolean - if true, driver waits for autonegotiation on startup) - - gMarvellTokenSpaceGuid.PcdPhyDeviceIds - (list of values corresponding to MV_PHY_DEVICE_ID enum) - - gMarvellTokenSpaceGuid.PcdPhySmiAddresses - (addresses of PHY devices) - - gMarvellTokenSpaceGuid.PcdPhy2MdioController - (Array specifying, which Mdio controller the PHY is attached to) - - -MV_PHY_DEVICE_ID: - - typedef enum { - 0 MV_PHY_DEVICE_1512, - } MV_PHY_DEVICE_ID; - -It should be extended when adding support for other PHY models. - -Disable autonegotiation: - - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE - -assuming, that PHY models are 1512: - - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } - - -MDIO configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd -EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: - - - gMarvellTokenSpaceGuid.PcdMdioControllers - (Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled) - - -I2C configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -In order to enable driver on a new platform, following steps need to be ta= ken: - - add following line to .dsc file: - edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - - add following line to .fdf file: - INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - - add PCDs with relevant values to .dsc file: - - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } - (addresses of I2C slave devices on bus) - - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } - (buses to which accoring slaves are attached) - - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 - (number of SoC's I2C buses) - - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } - (array with used controllers) - - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 - (I2C host controller clock frequency) - - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 - (baud rate used in I2C transmission) - - -PciEmulation configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D -Installation of various NonDiscoverable devices via PciEmulation driver is= performed -via set of PCDs. Following are available: - - - gMarvellTokenSpaceGuid.PcdPciEXhci - (Indicates, which Xhci devices are used) - - - gMarvellTokenSpaceGuid.PcdPciEAhci - (Indicates, which Ahci devices are used) - - - gMarvellTokenSpaceGuid.PcdPciESdhci - (Indicates, which Sdhci devices are used) - -All above PCD's correspond to hardware description in a dedicated structur= e: - -STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate - -in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device -count, base addresses, register region size and DMA-coherency type. - -Example -------- - -Assuming we want to enable second XHCI port and one SDHCI port on Armada -70x0 board, following needs to be declared: - - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } - - -SATA configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -There is one additional PCD for AHCI: - - - gMarvellTokenSpaceGuid.PcdSataBaseAddress - (Base address of SATA controller register space - used in SATA ComPhy init - sequence) - - -Pp2Dxe configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs -are required to operate: - - - gMarvellTokenSpaceGuid.PcdPp2Controllers - (Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled) - - - gMarvellTokenSpaceGuid.PcdPp2Port2Controller - (Array specifying, to which controller the port belongs to) - - - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes - (Indicates speed of the network interface: - - PHY_RGMII 0x0 - PHY_RGMII_ID 0x1 - PHY_RGMII_TXID 0x2 - PHY_RGMII_RXID 0x3 - PHY_SGMII 0x4 - PHY_RTBI 0x5 - PHY_XAUI 0x6 - PHY_RXAUI 0x7 - PHY_SFI 0x8 ) - - - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes - (Array specifying, to which PHY from - gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none, - e.g. in 10G SFI in-band link detection, 0xFF value must - be specified) - - - gMarvellTokenSpaceGuid.PcdPp2PortIds - (Identificators of PP2 ports) - - - gMarvellTokenSpaceGuid.PcdPp2GopIndexes - (Indexes used in GOP operation) - - - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp - (Set to 0x1 for always-up interface, 0x0 otherwise) - - - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed - (Indicates speed of the network interface: - - PHY_SPEED_10 0x1 - PHY_SPEED_100 0x2 - PHY_SPEED_1000 0x3 - PHY_SPEED_2500 0x4 - PHY_SPEED_10000 0x5 ) - - -UTMI PHY configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -In order to configure UTMI, following PCDs are available: - - - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled - (Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled) - - - gMarvellTokenSpaceGuid.PcdUtmiPortType - (Indicates type of the connected USB port: - - UTMI_USB_HOST0 0x0 - UTMI_USB_HOST1 0x1 - UTMI_USB_DEVICE0 0x2 ) - -Example -------- - - # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 } - gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB= _HOST1) } - - -SPI driver configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Following PCDs are available for configuration of spi driver: - - - gMarvellTokenSpaceGuid.PcdSpiClockFrequency - (Frequency (in Hz) of SPI clock) - - - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency - (Max SCLK line frequency (in Hz) (max transfer frequency) ) - -SpiFlash configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Folowing PCDs for spi flash driver configuration must be set properly: - - - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - (Size of SPI flash address in bytes (3 or 4) ) - - - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - (Size of minimal erase block in bytes) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - (Size of SPI flash page) - - - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize - (Size of SPI flash sector, 65536 bytes by default) - - - gMarvellTokenSpaceGuid.PcdSpiFlashId - (Id of SPI flash) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - (Spi flash polling flag) - - - gMarvellTokenSpaceGuid.PcdSpiFlashMode - (Default SCLK mode (see SPI_MODE enum in file - edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h)) - - - gMarvellTokenSpaceGuid.PcdSpiFlashCs - (Chip select used for communication with the Flash) - -MPP configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Multi-Purpose Ports (MPP) are configurable through platform PCDs. -In order to set desired pin multiplexing, .dsc file needs to be modified. -(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer= to -Documentation/Build.txt for currently supported {platftorm_name} ) -Following PCDs are available: - - - gMarvellTokenSpaceGuid.PcdMppChipCount - (Indicates how many different chips are placed on board. So far up to 4 c= hips - are supported) - -Every MPP PCD has part where - stands for chip ID (order is not important, but configuration will = be - set for first PcdMppChipCount chips). - -Below is example for the first chip (Chip0). - - - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag - (Indicates that register order is reversed. (Needs to be used only for AP= 806-Z1) ) - - - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress - (This is base address for MPP configuration register) - - - gMarvellTokenSpaceGuid.PcdChip0MppPinCount - (Defines how many MPP pins are available) - - - gMarvellTokenSpaceGuid.PcdChip0MppSel0 - - gMarvellTokenSpaceGuid.PcdChip0MppSel1 - - gMarvellTokenSpaceGuid.PcdChip0MppSel2 - (This registers defines functions of 10 pins in ascending order) - -Examples --------- - - # APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, = 0x1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, = 0x0, 0x0, 0x0, 0x0 } - -Set pin 6 and 7 to 0xa function: - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, = 0xa, 0xa, 0x0, 0x0 } - - -MarvellResetSystemLib configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -This simple library allows to mask given bits in given reg at UEFI 'reset' -command call. These variables are configurable through PCDs: - - - gMarvellTokenSpaceGuid.PcdResetRegAddress - - gMarvellTokenSpaceGuid.PcdResetRegMask - - -Ramdisk configuration -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -There is one PCD available for Ramdisk configuration - - - gMarvellTokenSpaceGuid.PcdRamDiskSize - (Defines size of Ramdisk) +UEFI Porting Guide +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This document provides instructions for adding support for new Marvell Arm= ada +board. For the sake of simplicity new Marvell board will be called "new_bo= ard". + +1. Create configuration files for new target + 1.1 Create FDF file for new board + + - Copy and rename edk2-platforms/Platform/Marvell/Armada/Armada70= x0.fdf to + edk2-platforms/Platform/Marvell/Armada/new_board.fdf + - Change the first no-comment line: + [FD.Armada70x0_EFI] to [FD.{new_board}_EFI] + + 1.2 Create DSC file for new board + + - Add new_board.dsc file to edk2-platforms/Platform/Marvell/Armad= a directory + - Insert following [Defines] section to new_board.dsc: + + [Defines] + PLATFORM_NAME =3D {new_board} + PLATFORM_GUID =3D {newly_genera= ted_GUID} + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010019 + OUTPUT_DIRECTORY =3D {output_direc= tory} + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D {path_to_fdf_= file} + + - Add "!include Armada.dsc.inc" entry to new_board.dsc + +2. Driver support + - According to content of files from + edk2-platforms/Silicon/Marvell/Documentation/PortingGuide.txt + insert PCD entries into new_board.dsc for every needed interface (as li= sted below). + +3. Compilation + - Refer to edk2-platforms/Platform/Marvell/Readme.md. Remember to change + {platform} to new_board in order to point build system to newly created= DSC file. + +4. Output file + - Output files (and among others FD file, which may be used by ATF) are + generated under directory pointed by "OUTPUT_DIRECTORY" entry (see poin= t 1.2). + + +COMPHY configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to configure ComPhy library, following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdComPhyDevices + +This array indicates, which ones of the ComPhy chips defined in +MVHW_COMPHY_DESC template will be configured. + +Every ComPhy PCD has part where stands for chip ID (order is n= ot +important, but configuration will be set for first PcdComPhyChipCount chip= s). + +Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes +settings for this chip. Their format is array of up to 10 values reflecting +defined numbers for SPEED/TYPE/INVERT, whose description can be found in: + + OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h + + - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + (Array of types - currently supported are: + + CP_UNCONNECTED 0x0 + CP_PCIE0 0x1 + CP_PCIE1 0x2 + CP_PCIE2 0x3 + CP_PCIE3 0x4 + CP_SATA0 0x5 + CP_SATA1 0x6 + CP_SATA2 0x7 + CP_SATA3 0x8 + CP_SGMII0 0x9 + CP_SGMII1 0xA + CP_SGMII2 0xB + CP_SGMII3 0xC + CP_QSGMII 0xD + CP_USB3_HOST0 0xE + CP_USB3_HOST1 0xF + CP_USB3_DEVICE 0x10 + CP_XAUI0 0x11 + CP_XAUI1 0x12 + CP_XAUI2 0x13 + CP_XAUI3 0x14 + CP_RXAUI0 0x15 + CP_RXAUI1 0x16 + CP_SFI 0x17 ) + + - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds + (Array of speeds - currently supported are: + + CP_1_25G 0x1 + CP_1_5G 0x2 + CP_2_5G 0x3 + CP_3G 0x4 + CP_3_125G 0x5 + CP_5G 0x6 + CP_5_15625G 0x7 + CP_6G 0x8 + CP_6_25G 0x9 + CP_10_3125G 0xA ) + + - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + (Array of lane inversion types - currently supported are: + + CP_NO_INVERT 0x0 + CP_TXD_INVERT 0x1 + CP_RXD_INVERT 0x2 + CP_ALL_INVERT 0x3 ) + +Example +------- + + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1= ), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G= ), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } + + +PHY Driver configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. +Currently only 1518 series PHYs are supported. Following PCDs are required: + + - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + (boolean - if true, driver waits for autonegotiation on startup) + - gMarvellTokenSpaceGuid.PcdPhyDeviceIds + (list of values corresponding to MV_PHY_DEVICE_ID enum) + - gMarvellTokenSpaceGuid.PcdPhySmiAddresses + (addresses of PHY devices) + - gMarvellTokenSpaceGuid.PcdPhy2MdioController + (Array specifying, which Mdio controller the PHY is attached to) + + +MV_PHY_DEVICE_ID: + + typedef enum { + 0 MV_PHY_DEVICE_1512, + } MV_PHY_DEVICE_ID; + +It should be extended when adding support for other PHY models. + +Disable autonegotiation: + + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + +assuming, that PHY models are 1512: + + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + + +MDIO configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd +EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: + + - gMarvellTokenSpaceGuid.PcdMdioControllers + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) + + +I2C configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to enable driver on a new platform, following steps need to be ta= ken: + - add following line to .dsc file: + edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf + - add following line to .fdf file: + INF edk2-platforms/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf + - add PCDs with relevant values to .dsc file: + - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } + (addresses of I2C slave devices on bus) + - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } + (buses to which accoring slaves are attached) + - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + (number of SoC's I2C buses) + - gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x1 } + (array with used controllers) + - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 + (I2C host controller clock frequency) + - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + (baud rate used in I2C transmission) + + +PciEmulation configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +Installation of various NonDiscoverable devices via PciEmulation driver is= performed +via set of PCDs. Following are available: + + - gMarvellTokenSpaceGuid.PcdPciEXhci + (Indicates, which Xhci devices are used) + + - gMarvellTokenSpaceGuid.PcdPciEAhci + (Indicates, which Ahci devices are used) + + - gMarvellTokenSpaceGuid.PcdPciESdhci + (Indicates, which Sdhci devices are used) + +All above PCD's correspond to hardware description in a dedicated structur= e: + +STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate + +in Platform/Marvell/PciEmulation/PciEmulation.c file. It comprises device +count, base addresses, register region size and DMA-coherency type. + +Example +------- + +Assuming we want to enable second XHCI port and one SDHCI port on Armada +70x0 board, following needs to be declared: + + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } + + +SATA configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +There is one additional PCD for AHCI: + + - gMarvellTokenSpaceGuid.PcdSataBaseAddress + (Base address of SATA controller register space - used in SATA Com= Phy init + sequence) + + +Pp2Dxe configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs +are required to operate: + + - gMarvellTokenSpaceGuid.PcdPp2Controllers + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) + + - gMarvellTokenSpaceGuid.PcdPp2Port2Controller + (Array specifying, to which controller the port belongs to) + + - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes + (Indicates speed of the network interface: + + PHY_RGMII 0x0 + PHY_RGMII_ID 0x1 + PHY_RGMII_TXID 0x2 + PHY_RGMII_RXID 0x3 + PHY_SGMII 0x4 + PHY_RTBI 0x5 + PHY_XAUI 0x6 + PHY_RXAUI 0x7 + PHY_SFI 0x8 ) + + - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes + (Array specifying, to which PHY from + gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none, + e.g. in 10G SFI in-band link detection, 0xFF value must + be specified) + + - gMarvellTokenSpaceGuid.PcdPp2PortIds + (Identificators of PP2 ports) + + - gMarvellTokenSpaceGuid.PcdPp2GopIndexes + (Indexes used in GOP operation) + + - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp + (Set to 0x1 for always-up interface, 0x0 otherwise) + + - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed + (Indicates speed of the network interface: + + PHY_SPEED_10 0x1 + PHY_SPEED_100 0x2 + PHY_SPEED_1000 0x3 + PHY_SPEED_2500 0x4 + PHY_SPEED_10000 0x5 ) + + +UTMI PHY configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to configure UTMI, following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) + + - gMarvellTokenSpaceGuid.PcdUtmiPortType + (Indicates type of the connected USB port: + + UTMI_USB_HOST0 0x0 + UTMI_USB_HOST1 0x1 + UTMI_USB_DEVICE0 0x2 ) + +Example +------- + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, = 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST= 0), $(UTMI_USB_HOST1) } + + +SPI driver configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Following PCDs are available for configuration of spi driver: + + - gMarvellTokenSpaceGuid.PcdSpiClockFrequency + (Frequency (in Hz) of SPI clock) + + - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency + (Max SCLK line frequency (in Hz) (max transfer frequency) ) + +SpiFlash configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Folowing PCDs for spi flash driver configuration must be set properly: + + - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles + (Size of SPI flash address in bytes (3 or 4) ) + + - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize + (Size of minimal erase block in bytes) + + - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize + (Size of SPI flash page) + + - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize + (Size of SPI flash sector, 65536 bytes by default) + + - gMarvellTokenSpaceGuid.PcdSpiFlashId + (Id of SPI flash) + + - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd + (Spi flash polling flag) + + - gMarvellTokenSpaceGuid.PcdSpiFlashMode + (Default SCLK mode (see SPI_MODE enum in file + edk2-platforms/Platform/Marvell/Drivers/Spi/MvSpi.h)) + + - gMarvellTokenSpaceGuid.PcdSpiFlashCs + (Chip select used for communication with the Flash) + +MPP configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Multi-Purpose Ports (MPP) are configurable through platform PCDs. +In order to set desired pin multiplexing, .dsc file needs to be modified. +(edk2-platforms/Platform/Marvell/Armada/{platform_name}.dsc - please refer= to +Documentation/Build.txt for currently supported {platftorm_name} ) +Following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdMppChipCount + (Indicates how many different chips are placed on board. So far up= to 4 chips + are supported) + +Every MPP PCD has part where + stands for chip ID (order is not important, but configuration will = be + set for first PcdMppChipCount chips). + +Below is example for the first chip (Chip0). + + - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag + (Indicates that register order is reversed. (Needs to be used only= for AP806-Z1) ) + + - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress + (This is base address for MPP configuration register) + + - gMarvellTokenSpaceGuid.PcdChip0MppPinCount + (Defines how many MPP pins are available) + + - gMarvellTokenSpaceGuid.PcdChip0MppSel0 + - gMarvellTokenSpaceGuid.PcdChip0MppSel1 + - gMarvellTokenSpaceGuid.PcdChip0MppSel2 + (This registers defines functions of 10 pins in ascending order) + +Examples +-------- + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0= x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0= x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } + +Set pin 6 and 7 to 0xa function: + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0= x0, 0x0, 0x0, 0xa, 0xa, 0x0, 0x0 } + + +MarvellResetSystemLib configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +This simple library allows to mask given bits in given reg at UEFI 'reset' +command call. These variables are configurable through PCDs: + + - gMarvellTokenSpaceGuid.PcdResetRegAddress + - gMarvellTokenSpaceGuid.PcdResetRegMask + + +Ramdisk configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +There is one PCD available for Ramdisk configuration + + - gMarvellTokenSpaceGuid.PcdRamDiskSize + (Defines size of Ramdisk) --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel