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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v29sm194155ljv.27.2017.10.06.00.44.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 00:44:26 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::230; helo=mail-lf0-x230.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TQKx2+w+3QOlFvou1KtEKLxSmoaA95cF0M+2fV3n1jU=; b=y8c60D7YQMsyQvhT0WAkfZxOh+f/6o2GCyXtmVNDV2Q/AzjxNCv9Hnj8kQ/xK4PIoe L4jYX6m5jeOO8kUGVyB0OEusD3kXU1jTnY5fGJuznQYiKb3EYmEoNegf3tYIrCcpbV6o yNjDDE83eJ7ziVVo6xT4C5xkyNRPPR16CRNW5xvlnJqknfxYBPz1gDBSCeUbkNAWtQNa VnfiX6ZYzmOOBeCV2ZwzsKjzR04/r0Z7i3XXwqnF4K9GhzZikbuZ9iTV3mATEOAE04ST eKhWRlymS7TtTdm/q6fUauGeSlOe33PkeM4WD87gQ2jw/Oy/P9ODTahdM8j9kgO1/ETd jfng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TQKx2+w+3QOlFvou1KtEKLxSmoaA95cF0M+2fV3n1jU=; b=h8ZKWqX2qAiYu3aoD7Ddx32LK2VOmRcnFOVsyxS9fkKuGYx4ATEKL0aW8Z0DP1MmCM gQFyAXWbDnrN7gThB80ubiC20VQuZSweEhX6lJZFibzpvhnkMs5WYnriHwj22tfNMfcr srbsGDaF4aopikEyhW3Hf/IZpN0o5uHCD6vcG6WAxbYfYw/4CzOJf64ujPBnSw4mU3qc Cea//vCt2cSKLes9CM3oIHnc04+Y9GMPrJeYNcRJw6NGTbVRFj5HRKhS3FjoZHUQk1lP YmFDtbxEj5q/POud5lzs6DFSyG96guFcc/OwvaAMHXNsTsWfHsm7n2n8a0gowxJ5HiVR 37WQ== X-Gm-Message-State: AMCzsaW9S+eQPbHC4VVRmtdfm1lBTk1/wOAXW/Vnwjfhidwm9OFcDcE9 2Yda1bD2jq6mu5D+tTpLUgQ+blM+Mrc= X-Google-Smtp-Source: AOwi7QA+Cv1XgMxURPp1EXuRVu1oZMXAzVAsLDPLimUFHZFK/hLmG+Hc4THm1Ntl9ekjoVwBnKgQ1Q== X-Received: by 10.46.0.39 with SMTP id 39mr492051lja.13.1507275867617; Fri, 06 Oct 2017 00:44:27 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 6 Oct 2017 09:51:14 +0200 Message-Id: <1507276278-3608-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507276278-3608-1-git-send-email-mw@semihalf.com> References: <1507276278-3608-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 1/5] Marvell/Library: ComPhyLib: Remove PCD string parsing X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Simplify obtaining lane data, using arrays with direct enum values, rather than strings. This is another step to completely remove ParsePcdLib. This patch replaces string-based description of ComPhy lanes on Armada 70x0 DB with the enum values of type and speed. PortingGuide is updated accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 11 +++- Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 65 ++++---------------- Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 25 +++----- Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf | 1 - Silicon/Marvell/Documentation/PortingGuide.txt | 62 ++++++++++++++----- 5 files changed, 77 insertions(+), 87 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 467dfa3..7b03744 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -100,8 +100,15 @@ =20 #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1= ;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;= 5000" + # ComPhy0 + # 0: SGMII1 1.25 Gbps + # 1: USB3_HOST0 5 Gbps + # 2: SFI 10.31 Gbps + # 3: SATA1 5 Gbps + # 4: USB3_HOST1 5 Gbps + # 5: PCIE2 5 Gbps + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ 0xA, 0xE, 0x17, 0x6, 0xF, 0= x3 } + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x1, 0x6, 0xA, 0x6, 0x6, 0= x6 } =20 #UtmiPhy gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.c index 3eb5d9f..bf21dca 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c @@ -113,47 +113,6 @@ RegSetSilent16( MmioWrite16 (Addr, RegData); } =20 -/* This function returns enum with SerDesType */ -UINT32 -ParseSerdesTypeString ( - CHAR16* String - ) -{ - UINT32 i; - - if (String =3D=3D NULL) - return COMPHY_TYPE_INVALID; - - for (i =3D 0; i < COMPHY_TYPE_MAX; i++) { - if (StrCmp (String, TypeStringTable[i]) =3D=3D 0) { - return i; - } - } - - /* PCD string doesn't match any supported SerDes Type */ - return COMPHY_TYPE_INVALID; -} - -/* This function converts SerDes speed in MHz to enum with SerDesSpeed */ -UINT32 -ParseSerdesSpeed ( - UINT32 Value - ) -{ - UINT32 i; - UINT32 ValueTable [] =3D {0, 1250, 1500, 2500, 3000, 3125, - 5000, 5156, 6000, 6250, 10310}; - - for (i =3D 0; i < COMPHY_SPEED_MAX; i++) { - if (Value =3D=3D ValueTable[i]) { - return i; - } - } - - /* PCD SerDes speed value doesn't match any supported SerDes speed */ - return COMPHY_SPEED_INVALID; -} - CHAR16 * GetTypeString ( UINT32 Type @@ -182,7 +141,8 @@ GetSpeedString ( =20 VOID ComPhyPrint ( - IN CHIP_COMPHY_CONFIG *PtrChipCfg + IN CHIP_COMPHY_CONFIG *PtrChipCfg, + IN UINT8 Index ) { UINT32 Lane; @@ -191,7 +151,7 @@ ComPhyPrint ( for (Lane =3D 0; Lane < PtrChipCfg->LanesCount; Lane++) { SpeedStr =3D GetSpeedString(PtrChipCfg->MapData[Lane].Speed); TypeStr =3D GetTypeString(PtrChipCfg->MapData[Lane].Type); - DEBUG((DEBUG_ERROR, "Comphy-%d: %-13s %-10s\n", Lane, TypeStr, SpeedSt= r)); + DEBUG ((DEBUG_ERROR, "Comphy%d-%d: %-13s %-10s\n", Index, Lane, TypeSt= r, SpeedStr)); } =20 DEBUG((DEBUG_ERROR, "\n")); @@ -238,16 +198,16 @@ InitComPhyConfig ( */ switch (Id) { case 0: - GetComPhyPcd (ChipConfig, LaneData, 0); + GetComPhyPcd (LaneData, 0); break; case 1: - GetComPhyPcd (ChipConfig, LaneData, 1); + GetComPhyPcd (LaneData, 1); break; case 2: - GetComPhyPcd (ChipConfig, LaneData, 2); + GetComPhyPcd (LaneData, 2); break; case 3: - GetComPhyPcd (ChipConfig, LaneData, 3); + GetComPhyPcd (LaneData, 3); break; } } @@ -288,12 +248,9 @@ MvComPhyInit ( /* Get the count of the SerDes of the specific chip */ MaxComphyCount =3D PtrChipCfg->LanesCount; for (Lane =3D 0; Lane < MaxComphyCount; Lane++) { - /* Parse PCD with string indicating SerDes Type */ - PtrChipCfg->MapData[Lane].Type =3D - ParseSerdesTypeString (LaneData[Index].TypeStr[Lane]); - PtrChipCfg->MapData[Lane].Speed =3D - ParseSerdesSpeed (LaneData[Index].SpeedValue[Lane]); - PtrChipCfg->MapData[Lane].Invert =3D (UINT32)LaneData[Index].InvFlag= [Lane]; + PtrChipCfg->MapData[Lane].Type =3D LaneData[Index].Type[Lane]; + PtrChipCfg->MapData[Lane].Speed =3D LaneData[Index].SpeedValue[Lane]; + PtrChipCfg->MapData[Lane].Invert =3D LaneData[Index].InvFlag[Lane]; =20 if ((PtrChipCfg->MapData[Lane].Speed =3D=3D COMPHY_SPEED_INVALID) || (PtrChipCfg->MapData[Lane].Speed =3D=3D COMPHY_SPEED_ERROR) || @@ -311,7 +268,7 @@ MvComPhyInit ( return Status; } =20 - ComPhyPrint (PtrChipCfg); + ComPhyPrint (PtrChipCfg, Index); =20 /* PHY power UP sequence */ PtrChipCfg->Init (PtrChipCfg); diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marv= ell/Library/ComPhyLib/ComPhyLib.h index 3898978..5899a4a 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h @@ -43,7 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include =20 #define MAX_LANE_OPTIONS 10 =20 @@ -52,14 +51,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define GET_LANE_SPEED(id) PcdGetPtr(PcdChip##id##ComPhySpeeds) #define GET_LANE_INV(id) PcdGetPtr(PcdChip##id##ComPhyInvFlags) =20 -#define FillLaneMap(chip_struct, lane_struct, id) { \ - ParsePcdString((CHAR16 *) GET_LANE_TYPE(id), chip_struct[id].LanesCount,= NULL, lane_struct[id].TypeStr); \ - ParsePcdString((CHAR16 *) GET_LANE_SPEED(id), chip_struct[id].LanesCount= , lane_struct[id].SpeedValue, NULL); \ - ParsePcdString((CHAR16 *) GET_LANE_INV(id), chip_struct[id].LanesCount, = lane_struct[id].InvFlag, NULL); \ -} - -#define GetComPhyPcd(chip_struct, lane_struct, id) { \ - FillLaneMap(chip_struct, lane_struct, id); \ +#define GetComPhyPcd(lane_struct, id) { \ + lane_struct[id].Type =3D (UINT8 *)GET_LANE_TYPE(id); \ + lane_struct[id].SpeedValue =3D (UINT8 *)GET_LANE_SPEED(id); \ + lane_struct[id].InvFlag =3D (UINT8 *)GET_LANE_SPEED(id); \ } =20 /***** ComPhy *****/ @@ -573,15 +568,15 @@ typedef struct { } COMPHY_MUX_DATA; =20 typedef struct { - UINT32 Type; - UINT32 Speed; - UINT32 Invert; + UINT8 Type; + UINT8 Speed; + UINT8 Invert; } COMPHY_MAP; =20 typedef struct { - CHAR16 *TypeStr[MAX_LANE_OPTIONS]; - UINTN SpeedValue[MAX_LANE_OPTIONS]; - UINTN InvFlag[MAX_LANE_OPTIONS]; + UINT8 *Type; + UINT8 *SpeedValue; + UINT8 *InvFlag; } PCD_LANE_MAP; =20 typedef diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Platform/Ma= rvell/Library/ComPhyLib/ComPhyLib.inf index e0f4634..c223fe5 100644 --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf @@ -51,7 +51,6 @@ MemoryAllocationLib PcdLib IoLib - ParsePcdLib =20 [Sources.common] ComPhyLib.c diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 83ebe9d..47a667d 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -57,27 +57,59 @@ Every ComPhy PCD has part where stands for = chip ID (order is not important, but configuration will be set for first PcdComPhyChipCount chip= s). =20 Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes -settings for this chip. Their format is unicode string, containing settings -for up to 10 lanes. Setting for each one is separated with semicolon. -These PCDs together describe outputs of PHY integrated in simple cihp. -Below is example for the first chip (Chip0). +settings for this chip. Their format is array of up to 10 values reflecting +defined numbers for SPEED/TYPE/INVERT, whose description can be found in: =20 - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes - (Unicode string indicating PHY types. Currently supported are: + OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h =20 - { L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", - L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", - L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", - L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", - L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", - L"RXAUI1", L"KR" } ) + - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + (Array of types - currently supported are: + + COMPHY_TYPE_PCIE0 1 + COMPHY_TYPE_PCIE1 2 + COMPHY_TYPE_PCIE2 3 + COMPHY_TYPE_PCIE3 4 + COMPHY_TYPE_SATA0 5 + COMPHY_TYPE_SATA1 6 + COMPHY_TYPE_SATA2 7 + COMPHY_TYPE_SATA3 8 + COMPHY_TYPE_SGMII0 9 + COMPHY_TYPE_SGMII1 10 + COMPHY_TYPE_SGMII2 11 + COMPHY_TYPE_SGMII3 12 + COMPHY_TYPE_QSGMII 13 + COMPHY_TYPE_USB3_HOST0 14 + COMPHY_TYPE_USB3_HOST1 15 + COMPHY_TYPE_USB3_DEVICE 16 + COMPHY_TYPE_XAUI0 17 + COMPHY_TYPE_XAUI1 18 + COMPHY_TYPE_XAUI2 19 + COMPHY_TYPE_XAUI3 20 + COMPHY_TYPE_RXAUI0 21 + COMPHY_TYPE_RXAUI1 22 + COMPHY_TYPE_SFI 23 ) =20 - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds - (Indicates PHY speeds in MHz. Currently supported are: - { 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 1031 } ) + (Array of speeds - currently supported are: + + COMPHY_SPEED_1_25G 1 + COMPHY_SPEED_1_5G 2 + COMPHY_SPEED_2_5G 3 + COMPHY_SPEED_3G 4 + COMPHY_SPEED_3_125G 5 + COMPHY_SPEED_5G 6 + COMPHY_SPEED_5_15625G 7 + COMPHY_SPEED_6G 8 + COMPHY_SPEED_6_25G 9 + COMPHY_SPEED_10_3125G 10 ) =20 - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags - (Indicates lane polarity invert) + (Array of lane inversion types - currently supported are: + + COMPHY_POLARITY_NO_INVERT 0 + COMPHY_POLARITY_TXD_INVERT 1 + COMPHY_POLARITY_RXD_INVERT 2 + COMPHY_POLARITY_ALL_INVERT 3 ) =20 Example ------- --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 07:21:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507275876139494.1876437443623; Fri, 6 Oct 2017 00:44:36 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B907C21EA15DD; Fri, 6 Oct 2017 00:41:09 -0700 (PDT) Received: from mail-lf0-x231.google.com (mail-lf0-x231.google.com [IPv6:2a00:1450:4010:c07::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AA26E21EA15BB for ; Fri, 6 Oct 2017 00:41:07 -0700 (PDT) Received: by mail-lf0-x231.google.com with SMTP id d17so19439223lfe.2 for ; Fri, 06 Oct 2017 00:44:31 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v29sm194155ljv.27.2017.10.06.00.44.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 00:44:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::231; helo=mail-lf0-x231.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XUvtnYBwOorDrer6UiA56B/QOsqXd27ADjcURcjN7DQ=; b=FWdTRwiB6l4Gd5bNghmEcQevk/eCLrmkebsV2e5Y4WluC24/RovNobUicqze3p0Tok 3zT2SqeqEPo7SCsOLYWjzQ4VLRSAHy6xJiix6rC9PoF7UyS0NLdFuQ1nsZcW9dcMsL7F PtYyTXO0hoZ6AZ35tYCX+gj2P98gIVPacEcrCW3C/3KZV0fcCSh52LM1n8QW4kPX0SR/ viE0qBuCH+fzAsyW/pn1Cr79ycBmYuAo4xbUj9pScndMcj+5H2hm9ps3cxT1QrTw+V7f qrWgrRvMFI1fz2YKyMuQBiikrV4/UmMTzXOoy8fOGLfjyv6J5ouuiRaB8InpnWnU9A9B JAwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XUvtnYBwOorDrer6UiA56B/QOsqXd27ADjcURcjN7DQ=; b=OfhvtquNzHs49sabZlkko+RCboBRJViqnlDqca1EhQ2xwN2V5lnJ+3TGn9oPj0kr9B zqTaLTVmp6SRtc4JU33NUkid2cvsIe2gKjcUiGBoUV52lY7VWo3/tORiV6pLw3dh4EtP LUdzQeVloIOpv/16fMCaV53NsXbu5uPQ1vwXZOXBYNCI21O1wHNb0Us6MKExWjuq01To eb+afuYZ57j9RfWcIruLSoEYxRC9B7GjzVn0K6aW0F+Gki5sd40Uu3L9mEMw7UOyqHMa uCkgM9+ZeYfZs5wsm9C4j3JEqpSaTI/V6l6SDvbc1iunzrGytpnENzOmJ5YqT3NEcJAi n6rg== X-Gm-Message-State: AMCzsaUXP+35JUz3xmO0JVJXJPkUjc2iCuIwOqoQSc1XsBbGjyG/IqXn 2LTS3R8ANI9JhzDxsZbBwvWNZ5bjr+Y= X-Google-Smtp-Source: AOwi7QBxactB6YeezIZPxR2qZGEnVC3ceDFeRSjNBawHu128VIs9KF7v9a/JtSNkkOqL7hDyVei5RA== X-Received: by 10.46.99.199 with SMTP id s68mr491875lje.7.1507275869115; Fri, 06 Oct 2017 00:44:29 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 6 Oct 2017 09:51:15 +0200 Message-Id: <1507276278-3608-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507276278-3608-1-git-send-email-mw@semihalf.com> References: <1507276278-3608-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/5] Marvell/Drivers: MvI2cDxe: Move devices description to MvHwDescLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces I2c description, using the new structures and template in MvHwDescLib. This change enables more flexible addition of multiple I2c controllers and also allows for removal of string PCD parsing. Update Armada 70x0 DB description and PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 2 +- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c | 42 +++++++++++-------= -- Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf | 3 +- Platform/Marvell/Include/Library/MvHwDescLib.h | 25 ++++++++++++ Platform/Marvell/Marvell.dec | 2 +- Silicon/Marvell/Documentation/PortingGuide.txt | 4 +- 6 files changed, 54 insertions(+), 24 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 7b03744..d9d126d 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -78,7 +78,7 @@ # I2C gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60 } gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" + gMarvellTokenSpaceGuid.PcdI2cControllers|{ 0x1, 0x1 } gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 } gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c b/Platform/Ma= rvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c index fa79ebc..ff8006e 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.c @@ -42,12 +42,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #include #include #include -#include #include +#include #include =20 #include "MvI2cDxe.h" =20 +DECLARE_A7K8K_I2C_TEMPLATE; + STATIC MV_I2C_BAUD_RATE baud_rate; =20 STATIC MV_I2C_DEVICE_PATH MvI2cDevicePathProtocol =3D { @@ -172,35 +174,39 @@ MvI2cInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { + MVHW_I2C_DESC *Desc =3D &mA7k8kI2cDescTemplate; + UINT8 *I2cDeviceTable, Index; EFI_STATUS Status; - UINT32 BusCount; - EFI_PHYSICAL_ADDRESS I2cBaseAddresses[PcdGet32 (PcdI2cBusCount)]; - INTN i; =20 - BusCount =3D PcdGet32 (PcdI2cBusCount); - if (BusCount =3D=3D 0) - return EFI_SUCCESS; + /* Obtain table with enabled I2c devices */ + I2cDeviceTable =3D (UINT8 *)PcdGetPtr (PcdI2cControllers); + if (I2cDeviceTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Missing PcdI2cControllers\n")); + return EFI_INVALID_PARAMETER; + } =20 - Status =3D ParsePcdString ( - (CHAR16 *) PcdGetPtr (PcdI2cBaseAddresses), - BusCount, - I2cBaseAddresses, - NULL - ); - if (EFI_ERROR(Status)) - return Status; + if (PcdGetSize (PcdI2cControllers) > MVHW_MAX_I2C_DEVS) { + DEBUG ((DEBUG_ERROR, "Wrong PcdI2cControllers format\n")); + return EFI_INVALID_PARAMETER; + } + + /* Initialize enabled chips */ + for (Index =3D 0; Index < PcdGetSize (PcdI2cControllers); Index++) { + if (!MVHW_DEV_ENABLED (I2c, Index)) { + DEBUG ((DEBUG_ERROR, "Skip I2c chip %d\n", Index)); + continue; + } =20 - for (i =3D 0; i < BusCount; i++) { Status =3D MvI2cInitialiseController( ImageHandle, SystemTable, - I2cBaseAddresses[i] + Desc->I2cBaseAddresses[Index] ); if (EFI_ERROR(Status)) return Status; } =20 - return Status; + return EFI_SUCCESS; } =20 STATIC diff --git a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf b/Platform/= Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf index 16374ef..c453b4f 100755 --- a/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf +++ b/Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf @@ -55,7 +55,6 @@ UefiLib UefiDriverEntryPoint UefiBootServicesTableLib - ParsePcdLib =20 [Protocols] gEfiI2cMasterProtocolGuid @@ -66,7 +65,7 @@ [Pcd] gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses gMarvellTokenSpaceGuid.PcdI2cSlaveBuses - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses + gMarvellTokenSpaceGuid.PcdI2cControllers gMarvellTokenSpaceGuid.PcdI2cClockFrequency gMarvellTokenSpaceGuid.PcdI2cBaudRate gMarvellTokenSpaceGuid.PcdI2cBusCount diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marv= ell/Include/Library/MvHwDescLib.h index 6a86865..e029b50 100644 --- a/Platform/Marvell/Include/Library/MvHwDescLib.h +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h @@ -60,6 +60,16 @@ typedef struct { } MVHW_COMPHY_DESC; =20 // +// I2C devices description template definition +// +#define MVHW_MAX_I2C_DEVS 4 + +typedef struct { + UINT8 I2cDevCount; + UINTN I2cBaseAddresses[MVHW_MAX_I2C_DEVS]; +} MVHW_I2C_DESC; + +// // NonDiscoverable devices description template definition // #define MVHW_MAX_XHCI_DEVS 4 @@ -130,6 +140,21 @@ MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate =3D {\ } =20 // +// Platform description of I2C devices +// +#define MVHW_CP0_I2C0_BASE 0xF2701000 +#define MVHW_CP0_I2C1_BASE 0xF2701100 +#define MVHW_CP1_I2C0_BASE 0xF4701000 +#define MVHW_CP1_I2C1_BASE 0xF4701100 + +#define DECLARE_A7K8K_I2C_TEMPLATE \ +STATIC \ +MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ + 4,\ + { MVHW_CP0_I2C0_BASE, MVHW_CP0_I2C1_BASE, MVHW_CP1_I2C0_BASE, MVHW_CP1_I= 2C1_BASE }\ +} + +// // Platform description of NonDiscoverable devices // #define MVHW_CP0_XHCI0_BASE 0xF2500000 diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index fc00f1a..25a4258 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -113,7 +113,7 @@ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x3000184 gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x0 }|VOID*|0x3000050 gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0 }|VOID*|0x3000185 - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|{ 0x0 }|VOID*|0x3000047 + gMarvellTokenSpaceGuid.PcdI2cControllers|{ 0x0 }|VOID*|0x3000047 gMarvellTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x3000048 gMarvellTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x3000049 gMarvellTokenSpaceGuid.PcdI2cBusCount|0|UINT32|0x3000183 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 47a667d..1a30c46 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -188,8 +188,8 @@ In order to enable driver on a new platform, following = steps need to be taken: (buses to which accoring slaves are attached) - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 (number of SoC's I2C buses) - - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" - (base addresses of I2C controller buses) + - gMarvellTokenSpaceGuid.PcdI2cControllers|{ 0x1, 0x1 } + (array with used controllers) - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 (I2C host controller clock frequency) - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 07:21:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v29sm194155ljv.27.2017.10.06.00.44.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 00:44:29 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::232; helo=mail-lf0-x232.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JkCiPxhTsjaPh1tNi+OH/+o92hdEQVBobi4eTJvTh4o=; b=USvTJ9Gos3T0m6CiyoP/Fb6KMKJvALwUxSww2Kd2ZXaIfNKSV2nPCMel+5kLtMuMGH lj8t+Mw+rFbXCxG4oDiuMdnheDd7yB37VtjAE54ys8PHKmJtEXcUM7YdfwinqVYwohJ7 J9LZGg0sBmccUeyecPGsLZDrNSBui+D5Nk2bGym03WybqtXrhnzCzvJlUAz+hXi2A6TC MXCPk/y3wMjMWFLJbCq4Lsr9G3V3z1N+enmsQMtih1kVA2TMW0exsMzA8tupDjxM4v/Q rRvQomGYq8PS67La1TFHqz/dlqhAq2yvu+VjvNlmQccVVKRRWXo8nSFVYit4JV7QcGEF TFWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JkCiPxhTsjaPh1tNi+OH/+o92hdEQVBobi4eTJvTh4o=; b=nAq1qt6Zsnb+gwyN38LEG8FH2io9LnlK+VVJCR2dMJrfqKrmxzVKlN7f9ARo0prIB1 Yfl2OCQmeTV9x8JGsrpbCWX8ZGZa3m/azpIuJNSHEqwCRvAjOCuvnNrWrI612QGAovHJ 0r/f5W1MfarxMirfJ5y0Yu6s+iUQamXr9t8wzjpmxentUiRiJvfLDsR3Yj/Fgk622D+J 4cfAQ7w5SGInBTn+ARRounc2UGfLHbiqADpMz/xL6VqTN2RfeXUfNC6c+9Z/04o/3FKH FAraFj4q2JdD9B6QkiUUWexovUI/MQcCDLM4z5YANCnGxzPoz9m/OlMtk0a4xmAmD4up jvLw== X-Gm-Message-State: AMCzsaUmBXsGvooz0gADF9wowNl9BNbUtoC+H2VkIAgdjashIltWZFOr Gjzsl9ZXOIj7skZrw1Tlr9LkFd8Wni0= X-Google-Smtp-Source: AOwi7QBmM8rERTgRfIikWBqDu72XFhS3Q4Ac76CWyRz3oattF/rWVK0SccoyoawagXk20DAE3wiGXw== X-Received: by 10.46.66.22 with SMTP id p22mr496883lja.18.1507275870727; Fri, 06 Oct 2017 00:44:30 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 6 Oct 2017 09:51:16 +0200 Message-Id: <1507276278-3608-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507276278-3608-1-git-send-email-mw@semihalf.com> References: <1507276278-3608-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 3/5] Marvell/Library: UtmiLib: Move devices description to MvHwDescLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces UTMI description, using the new structures and template in MvHwDescLib. This change enables more flexible addition of multiple CP with UTMI PHY's and also significantly reduces amount of used PCD's for that purpose. Update PortingGuide documentation accordingly. This patch replaces string-based description of Utmi on Armada 70x0 DB with new, reduced format. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 7 +- Platform/Marvell/Include/Library/MvHwDescLib.h | 47 ++++++ Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 149 ++++++++++-------= --- Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 1 - Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf | 11 +- Platform/Marvell/Marvell.dec | 7 +- Silicon/Marvell/Documentation/PortingGuide.txt | 30 ++-- 7 files changed, 142 insertions(+), 110 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index d9d126d..04bdf7c 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -111,11 +111,8 @@ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ 0x1, 0x6, 0xA, 0x6, 0x6, 0= x6 } =20 #UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" + gMarvellTokenSpaceGuid.PcdUtmiControllers|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ 0x0, 0x1 } =20 #MDIO gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200 diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marv= ell/Include/Library/MvHwDescLib.h index e029b50..6ad1bc2 100644 --- a/Platform/Marvell/Include/Library/MvHwDescLib.h +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h @@ -117,6 +117,19 @@ typedef struct { } MVHW_RTC_DESC; =20 // +// UTMI PHY's description template definition +// + +typedef struct { + UINT8 UtmiDevCount; + UINT32 UtmiPhyId[MVHW_MAX_XHCI_DEVS]; + UINTN UtmiBaseAddresses[MVHW_MAX_XHCI_DEVS]; + UINTN UtmiConfigAddresses[MVHW_MAX_XHCI_DEVS]; + UINTN UtmiUsbConfigAddresses[MVHW_MAX_XHCI_DEVS]; + UINTN UtmiMuxBitCount[MVHW_MAX_XHCI_DEVS]; +} MVHW_UTMI_DESC; + +// // Platform description of CommonPhy devices // #define MVHW_CP0_COMPHY_BASE 0xF2441000 @@ -217,4 +230,38 @@ MVHW_RTC_DESC mA7k8kRtcDescTemplate =3D {\ { SIZE_4KB, SIZE_4KB }\ } =20 +// +// Platform description of UTMI PHY's +// +#define MVHW_CP0_UTMI0_BASE 0xF2580000 +#define MVHW_CP0_UTMI0_CFG_BASE 0xF2440440 +#define MVHW_CP0_UTMI0_USB_CFG_BASE 0xF2440420 +#define MVHW_CP0_UTMI0_ID 0x0 +#define MVHW_CP0_UTMI1_BASE 0xF2581000 +#define MVHW_CP0_UTMI1_CFG_BASE 0xF2440444 +#define MVHW_CP0_UTMI1_USB_CFG_BASE 0xF2440420 +#define MVHW_CP0_UTMI1_ID 0x1 +#define MVHW_CP1_UTMI0_BASE 0xF4580000 +#define MVHW_CP1_UTMI0_CFG_BASE 0xF4440440 +#define MVHW_CP1_UTMI0_USB_CFG_BASE 0xF4440420 +#define MVHW_CP1_UTMI0_ID 0x0 +#define MVHW_CP1_UTMI1_BASE 0xF4581000 +#define MVHW_CP1_UTMI1_CFG_BASE 0xF4440444 +#define MVHW_CP1_UTMI1_USB_CFG_BASE 0xF4440420 +#define MVHW_CP1_UTMI1_ID 0x1 + +#define DECLARE_A7K8K_UTMI_TEMPLATE \ +STATIC \ +MVHW_UTMI_DESC mA7k8kUtmiDescTemplate =3D {\ + 4,\ + { MVHW_CP0_UTMI0_ID, MVHW_CP0_UTMI1_ID,\ + MVHW_CP1_UTMI0_ID, MVHW_CP1_UTMI1_ID },\ + { MVHW_CP0_UTMI0_BASE, MVHW_CP0_UTMI1_BASE,\ + MVHW_CP1_UTMI0_BASE, MVHW_CP1_UTMI1_BASE },\ + { MVHW_CP0_UTMI0_CFG_BASE, MVHW_CP0_UTMI1_CFG_BASE,\ + MVHW_CP1_UTMI0_CFG_BASE, MVHW_CP1_UTMI1_CFG_BASE },\ + { MVHW_CP0_UTMI0_USB_CFG_BASE, MVHW_CP0_UTMI1_USB_CFG_BASE,\ + MVHW_CP1_UTMI0_USB_CFG_BASE, MVHW_CP1_UTMI1_USB_CFG_BASE }\ +} + #endif /* __MVHWDESCLIB_H__ */ diff --git a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Platform/Ma= rvell/Library/UtmiPhyLib/UtmiPhyLib.c index 95b5698..b07c038 100644 --- a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c +++ b/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c @@ -33,12 +33,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. **************************************************************************= *****/ =20 #include "UtmiPhyLib.h" +#include + +DECLARE_A7K8K_UTMI_TEMPLATE; =20 typedef struct { EFI_PHYSICAL_ADDRESS UtmiBaseAddr; EFI_PHYSICAL_ADDRESS UsbCfgAddr; EFI_PHYSICAL_ADDRESS UtmiCfgAddr; UINT32 UtmiPhyPort; + UINT32 PhyId; } UTMI_PHY_DATA; =20 STATIC @@ -236,48 +240,52 @@ UtmiPhyPowerUp ( STATIC VOID Cp110UtmiPhyInit ( - IN UINT32 UtmiPhyCount, IN UTMI_PHY_DATA *UtmiData ) { - UINT32 i; + EFI_STATUS Status; =20 - for (i =3D 0; i < UtmiPhyCount; i++) { - UtmiPhyPowerDown(i, UtmiData[i].UtmiBaseAddr, - UtmiData[i].UsbCfgAddr, UtmiData[i].UtmiCfgAddr, - UtmiData[i].UtmiPhyPort); - } + UtmiPhyPowerDown ( + UtmiData->PhyId, + UtmiData->UtmiBaseAddr, + UtmiData->UsbCfgAddr, + UtmiData->UtmiCfgAddr, + UtmiData->UtmiPhyPort + ); =20 /* Power down PLL */ DEBUG((DEBUG_INFO, "UtmiPhy: stage: PHY power down PLL\n")); - RegSet (UtmiData[0].UsbCfgAddr, 0x0 << UTMI_USB_CFG_PLL_OFFSET, - UTMI_USB_CFG_PLL_MASK); - - for (i =3D 0; i < UtmiPhyCount; i++) { - UtmiPhyConfig(i, UtmiData[i].UtmiBaseAddr, - UtmiData[i].UsbCfgAddr, UtmiData[i].UtmiCfgAddr, - UtmiData[i].UtmiPhyPort); + MmioAnd32 (UtmiData->UsbCfgAddr, ~UTMI_USB_CFG_PLL_MASK); + + UtmiPhyConfig ( + UtmiData->PhyId, + UtmiData->UtmiBaseAddr, + UtmiData->UsbCfgAddr, + UtmiData->UtmiCfgAddr, + UtmiData->UtmiPhyPort + ); + + Status =3D UtmiPhyPowerUp ( + UtmiData->PhyId, + UtmiData->UtmiBaseAddr, + UtmiData->UsbCfgAddr, + UtmiData->UtmiCfgAddr, + UtmiData->UtmiPhyPort + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "UtmiPhy: Failed to initialize UTMI PHY %d\n", Ut= miData->PhyId)); + return; } =20 - for (i =3D 0; i < UtmiPhyCount; i++) { - if (EFI_ERROR(UtmiPhyPowerUp(i, UtmiData[i].UtmiBaseAddr, - UtmiData[i].UsbCfgAddr, UtmiData[i].UtmiCfgAddr, - UtmiData[i].UtmiPhyPort))) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Failed to initialize UTMI PHY %d\n", i= )); - continue; - } - DEBUG((DEBUG_ERROR, "UTMI PHY %d initialized to ", i)); - - if (UtmiData[i].UtmiPhyPort =3D=3D UTMI_PHY_TO_USB_DEVICE0) - DEBUG((DEBUG_ERROR, "USB Device\n")); - else - DEBUG((DEBUG_ERROR, "USB Host%d\n", UtmiData[i].UtmiPhyPort)); - } + DEBUG ((DEBUG_ERROR, "UTMI PHY %d initialized to ", UtmiData->PhyId)); + if (UtmiData->UtmiPhyPort =3D=3D UTMI_PHY_TO_USB_DEVICE0) + DEBUG((DEBUG_ERROR, "USB Device\n")); + else + DEBUG((DEBUG_ERROR, "USB Host%d\n", UtmiData->UtmiPhyPort)); =20 /* Power up PLL */ DEBUG((DEBUG_INFO, "UtmiPhy: stage: PHY power up PLL\n")); - RegSet (UtmiData[0].UsbCfgAddr, 0x1 << UTMI_USB_CFG_PLL_OFFSET, - UTMI_USB_CFG_PLL_MASK); + MmioOr32 (UtmiData->UsbCfgAddr, UTMI_USB_CFG_PLL_MASK); } =20 EFI_STATUS @@ -285,69 +293,66 @@ UtmiPhyInit ( VOID ) { - EFI_STATUS Status; - UTMI_PHY_DATA UtmiData[PcdGet32 (PcdUtmiPhyCount)]; - EFI_PHYSICAL_ADDRESS RegUtmiUnit[PcdGet32 (PcdUtmiPhyCount)]; - EFI_PHYSICAL_ADDRESS RegUsbCfg[PcdGet32 (PcdUtmiPhyCount)]; - EFI_PHYSICAL_ADDRESS RegUtmiCfg[PcdGet32 (PcdUtmiPhyCount)]; - UINTN UtmiPort[PcdGet32 (PcdUtmiPhyCount)]; - UINTN i, Count; - - Count =3D PcdGet32 (PcdUtmiPhyCount); - if (Count =3D=3D 0) { + UTMI_PHY_DATA UtmiData; + UINT8 *UtmiDeviceTable, *XhciDeviceTable, *UtmiPortType, Index; + MVHW_UTMI_DESC *Desc =3D &mA7k8kUtmiDescTemplate; + + /* Obtain table with enabled Utmi PHY's*/ + UtmiDeviceTable =3D (UINT8 *)PcdGetPtr (PcdUtmiControllers); + if (UtmiDeviceTable =3D=3D NULL) { /* No UTMI PHY on platform */ return EFI_SUCCESS; } =20 - DEBUG((DEBUG_INFO, "UtmiPhy: Initialize USB UTMI PHYs\n")); - /* Parse UtmiPhy PCDs */ - Status =3D ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyRegUtmiUnit), - Count, RegUtmiUnit, NULL); - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyRegUtmiUnit format\n")); + if (PcdGetSize (PcdUtmiControllers) > MVHW_MAX_XHCI_DEVS) { + DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiControllers format\n")); return EFI_INVALID_PARAMETER; } =20 - Status =3D ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyRegUsbCfg), - Count, RegUsbCfg, NULL); - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyRegUsbCfg format\n")); + /* Make sure XHCI controllers table is present */ + XhciDeviceTable =3D (UINT8 *)PcdGetPtr (PcdPciEXhci); + if (XhciDeviceTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "UTMI: Missing PcdPciEXhci\n")); return EFI_INVALID_PARAMETER; } =20 - Status =3D ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyRegUtmiCfg), - Count, RegUtmiCfg, NULL); - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyRegUtmiCfg format\n")); + /* Obtain port type table */ + UtmiPortType =3D (UINT8 *)PcdGetPtr (PcdUtmiPortType); + if (UtmiPortType =3D=3D NULL || PcdGetSize (PcdUtmiPortType) !=3D PcdGet= Size (PcdUtmiControllers)) { + DEBUG ((DEBUG_ERROR, "UTMI: Wrong PcdUtmiPortType format\n")); return EFI_INVALID_PARAMETER; } =20 - Status =3D ParsePcdString ((CHAR16 *) PcdGetPtr (PcdUtmiPhyUtmiPort), - Count, UtmiPort, NULL); - if (EFI_ERROR(Status)) { - DEBUG((DEBUG_ERROR, "UtmiPhy: Wrong PcdUtmiPhyUtmiPort format\n")); - return EFI_INVALID_PARAMETER; - } + /* Initialize enabled chips */ + for (Index =3D 0; Index < PcdGetSize (PcdUtmiControllers); Index++) { + if (!MVHW_DEV_ENABLED (Utmi, Index)) { + continue; + } + + /* UTMI PHY without enabled XHCI controller is useless */ + if (!MVHW_DEV_ENABLED (Xhci, Index)) { + DEBUG ((DEBUG_ERROR, "UTMI: Disabled Xhci controller %d\n", Index)); + return EFI_INVALID_PARAMETER; + } =20 - for (i =3D 0 ; i < Count ; i++) { /* Get base address of UTMI phy */ - UtmiData[i].UtmiBaseAddr =3D RegUtmiUnit[i]; + UtmiData.UtmiBaseAddr =3D Desc->UtmiBaseAddresses[Index]; =20 /* Get usb config address */ - UtmiData[i].UsbCfgAddr =3D RegUsbCfg[i]; + UtmiData.UsbCfgAddr =3D Desc->UtmiUsbConfigAddresses[Index]; =20 /* Get UTMI config address */ - UtmiData[i].UtmiCfgAddr =3D RegUtmiCfg[i]; + UtmiData.UtmiCfgAddr =3D Desc->UtmiConfigAddresses[Index]; =20 - /* - * Get the usb port number, which will be used to check if - * the utmi connected to host or device - */ - UtmiData[i].UtmiPhyPort =3D UtmiPort[i]; - } + /* Get UTMI PHY ID */ + UtmiData.PhyId =3D Desc->UtmiPhyId[Index]; =20 - /* Currently only Cp110 is supported */ - Cp110UtmiPhyInit (Count, UtmiData); + /* Get the usb port type */ + UtmiData.UtmiPhyPort =3D UtmiPortType[Index]; + + /* Currently only Cp110 is supported */ + Cp110UtmiPhyInit (&UtmiData); + } =20 return EFI_SUCCESS; } diff --git a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Platform/Ma= rvell/Library/UtmiPhyLib/UtmiPhyLib.h index f9b4933..0d7d72e 100644 --- a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h +++ b/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h @@ -42,7 +42,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include -#include =20 #define UTMI_USB_CFG_DEVICE_EN_OFFSET 0 #define UTMI_USB_CFG_DEVICE_EN_MASK (0x1 << UTMI_USB_CFG_DEV= ICE_EN_OFFSET) diff --git a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf b/Platform/= Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf index f1e57f4..6e33cdd 100644 --- a/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf +++ b/Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf @@ -50,15 +50,12 @@ DebugLib IoLib MemoryAllocationLib - ParsePcdLib PcdLib =20 [Sources.common] UtmiPhyLib.c =20 -[FixedPcd] - gMarvellTokenSpaceGuid.PcdUtmiPhyCount - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort +[Pcd] + gMarvellTokenSpaceGuid.PcdUtmiControllers + gMarvellTokenSpaceGuid.PcdUtmiPortType + gMarvellTokenSpaceGuid.PcdPciEXhci diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 25a4258..00d99fa 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -156,11 +156,8 @@ gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags|{ 0x0 }|VOID*|0x30000177 =20 #UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiPhyCount|0|UINT32|0x30000205 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|{ 0x0 }|VOID*|0x30000206 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|{ 0x0 }|VOID*|0x30000207 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|{ 0x0 }|VOID*|0x30000208 - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|{ 0x0 }|VOID*|0x30000209 + gMarvellTokenSpaceGuid.PcdUtmiControllers|{ 0x0 }|VOID*|0x30000206 + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ 0x0 }|VOID*|0x30000207 =20 #MDIO gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0|UINT64|0x3000043 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 1a30c46..8a9f603 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -278,33 +278,23 @@ UTMI PHY configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D In order to configure UTMI, following PCDs are available: =20 - - gMarvellTokenSpaceGuid.PcdUtmiPhyCount - (Indicates how many UTMI PHYs are available on platform) - -Next four PCDs are in unicode string format containing settings for all de= vices -separated with semicolon. - - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit - (Indicates base address of the UTMI unit) - - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg - (Indicates address of USB Configuration register) + - gMarvellTokenSpaceGuid.PcdUtmiControllers + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) =20 - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg - (Indicates address of external UTMI configuration) + - gMarvellTokenSpaceGuid.PcdUtmiPortType + (Indicates type of the connected USB port: =20 - - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort - (Indicates type of the connected USB port) + UTMI_PHY_TO_USB_HOST0 0 + UTMI_PHY_TO_USB_HOST1 1 + UTMI_PHY_TO_USB_DEVICE0 2 ) =20 Example ------- =20 # UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444" - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" + gMarvellTokenSpaceGuid.PcdUtmiControllers|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ 0x0, 0x1 } =20 =20 SPI driver configuration --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 07:21:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id v29sm194155ljv.27.2017.10.06.00.44.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 00:44:31 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::231; helo=mail-lf0-x231.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zOFX++VRIU2IkVAQVtxDRPEmf/tmo+f5JhtLwqZ7Vzc=; b=oBIjO9KXJ8mC9YM0CBfNPyfd/naYfAhD679/hB9cracdQ8PcSKOQyc0H2VWZUryuMA AXdK/5uQ53MBidlikHuS8oE03t4/cPJGLqQ5Xsx/1zspyw/Xj9Eezk40IJW0slfSljN3 V4hJsTn6AtL9ehHhH3LuREaDyVioR2/fN6oXOPCYtAdDz4rHlXvkkMVTKn0gCUsR7Sep 7tF3HUzYLEUZaa7UlFOkPzS2GfpI5Vl2s/GCzJaY4/ND/dX47S+lZo80BSj5dyg2k+jT k16VUJXSszL3CJS5dR/T2+9BkojAdFu22nyFHzN8FuYMtl0OVaQKoJHp6pmdGgEFOYzi +ppg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zOFX++VRIU2IkVAQVtxDRPEmf/tmo+f5JhtLwqZ7Vzc=; b=IJ6Io17DpWmedQxCJhyYEOCNvDY+x/zpdhUgxhOy1GyxSPZlx1sIorhd3FdDvzZpB6 /Ma+QWKcAAczHJIOLDTXxgiyNvOwWwlIQsJ6teHtntcnlEpSSFWacZ6+Wc0brBnWsMVA Kj5qG8WStg0TVOxUbJ4HG9tpOttZiLG5IOxvGLN/AuNB9Mckodoq9ACoMe1gJBaTR1Yq P1zgJy+hrHZpA/x90Gg9ZlTs2r2BQI+Ce5fQCVZB35Uq50GxcSIMFeH4NS1pXx1+oLHg 0o47pcx5DtENM2lqMNa+JM8zITJ5fVcMiILKhuWtVaK1MwBsFndoJvSTNOFTNSis7CYp /aYQ== X-Gm-Message-State: AMCzsaVEAHH3iPAPtRdp1wFmrppqxiebEJdXjFF6qwpOW3831GvMiV9t QRbTFtzueSz3zxs+Bo4okJuAsY++p5E= X-Google-Smtp-Source: AOwi7QBuWOgcbeyEZL0EENZhyc6DfFCNGrbs6SDEXzRX4O/6PsS1pZZ3g/Ibqh6XrprmyJ6ZUd3PdA== X-Received: by 10.25.213.194 with SMTP id m185mr212412lfg.175.1507275872205; Fri, 06 Oct 2017 00:44:32 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 6 Oct 2017 09:51:17 +0200 Message-Id: <1507276278-3608-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507276278-3608-1-git-send-email-mw@semihalf.com> References: <1507276278-3608-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 4/5] Marvell/Drivers: Pp2Dxe: Rework PHY handling X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hitherto PHY handling in Pp2Dxe was not flexible. It allowed for using only single MDIO controller, which may not be true on Armada 80x0 SoCs. For this purpose introduce the MDIO description, using the new structures and template in MvHwDescLib. This change enables addition of multiple CP110 hardware blocks with MDIO controllers. This change required different PHY handling and obtaining data over desired MDIO bus. Now given Pp2 port is matched with the PHY via its index in gMarvellTokenSpaceGuid.PcdPhyDeviceIds. The PHY itself is mapped to the MDIO controller, using gMarvellTokenSpaceGuid.PcdPhy2MdioController. Also obtaining SMI addresses was moved to the PHY initialization routine. All above allow for much cleaner and logical PHY description in the .dsc file. Update PortingGuide documentation accordingly and Armada 70x0 DB NIC/PHY description. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 8 +- Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c | 35 ++++-- Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf | 3 - Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c | 122 ++++++++++++-= ------- Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h | 2 - Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf | 4 +- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 16 +-- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 2 +- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 4 +- Platform/Marvell/Include/Library/MvHwDescLib.h | 23 ++++ Platform/Marvell/Include/Protocol/Mdio.h | 6 + Platform/Marvell/Include/Protocol/MvPhy.h | 1 + Platform/Marvell/Marvell.dec | 8 +- Silicon/Marvell/Documentation/PortingGuide.txt | 50 ++++---- 14 files changed, 179 insertions(+), 105 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 04bdf7c..3b75381 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -115,18 +115,20 @@ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ 0x0, 0x1 } =20 #MDIO - gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200 + gMarvellTokenSpaceGuid.PcdMdioControllers|{ 0x1, 0x0 } =20 #PHY - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x8, 0x4, 0x0 } + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 #NET - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ 0x8, 0x4, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } diff --git a/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c b/Platform/= Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c index ae466d7..12aabad 100644 --- a/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c +++ b/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.c @@ -46,7 +46,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "MvMdioDxe.h" =20 -UINT64 MdioBase =3D 0; +DECLARE_A7K8K_MDIO_TEMPLATE; =20 STATIC EFI_STATUS @@ -70,7 +70,7 @@ MdioCheckParam ( STATIC EFI_STATUS MdioWaitReady ( - VOID + UINT32 MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -92,7 +92,7 @@ MdioWaitReady ( STATIC EFI_STATUS MdioWaitValid ( - VOID + UINT32 MdioBase ) { UINT32 Timeout =3D MVEBU_SMI_TIMEOUT; @@ -116,11 +116,13 @@ EFI_STATUS MdioOperation ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN BOOLEAN Write, IN OUT UINT32 *Data ) { + UINT32 MdioBase =3D This->BaseAddresses[MdioIndex]; UINT32 MdioReg; EFI_STATUS Status; =20 @@ -131,7 +133,7 @@ MdioOperation ( } =20 /* wait till the SMI is not busy */ - Status =3D MdioWaitReady (); + Status =3D MdioWaitReady (MdioBase); if (EFI_ERROR(Status)) { DEBUG((DEBUG_ERROR, "MdioDxe: MdioWaitReady error\n")); return Status; @@ -151,7 +153,7 @@ MdioOperation ( MdioRegWrite32 (MdioReg, MdioBase); =20 /* make sure that the write transaction is over */ - Status =3D Write ? MdioWaitReady () : MdioWaitValid (); + Status =3D Write ? MdioWaitReady (MdioBase) : MdioWaitValid (MdioBase); if (EFI_ERROR(Status)) { DEBUG((DEBUG_ERROR, "MdioDxe: MdioWaitReady error\n")); return Status; @@ -169,6 +171,7 @@ EFI_STATUS MvMdioRead ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN UINT32 *Data ) @@ -178,6 +181,7 @@ MvMdioRead ( Status =3D MdioOperation ( This, PhyAddr, + MdioIndex, RegOff, FALSE, Data @@ -190,6 +194,7 @@ EFI_STATUS MvMdioWrite ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN UINT32 Data ) @@ -197,6 +202,7 @@ MvMdioWrite ( return MdioOperation ( This, PhyAddr, + MdioIndex, RegOff, TRUE, &Data @@ -210,18 +216,27 @@ MvMdioDxeInitialise ( IN EFI_SYSTEM_TABLE *SystemTable ) { + MVHW_MDIO_DESC *Desc =3D &mA7k8kMdioDescTemplate; + UINT8 Index; MARVELL_MDIO_PROTOCOL *Mdio; EFI_STATUS Status; EFI_HANDLE Handle =3D NULL; =20 Mdio =3D AllocateZeroPool (sizeof (MARVELL_MDIO_PROTOCOL)); + if (Mdio =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "MdioDxe: Protocol allocation failed\n")); + return EFI_OUT_OF_RESOURCES; + } + + /* Obtain base addresses of all possible controllers */ + for (Index =3D 0; Index < Desc->MdioDevCount; Index++) { + Mdio->BaseAddresses[Index] =3D Desc->MdioBaseAddresses[Index]; + } + + Mdio->ControllerCount =3D Desc->MdioDevCount; Mdio->Read =3D MvMdioRead; Mdio->Write =3D MvMdioWrite; - MdioBase =3D PcdGet64 (PcdMdioBaseAddress); - if (MdioBase =3D=3D 0) { - DEBUG((DEBUG_ERROR, "MdioDxe: PcdMdioBaseAddress not set\n")); - return EFI_INVALID_PARAMETER; - } + Status =3D gBS->InstallMultipleProtocolInterfaces ( &Handle, &gMarvellMdioProtocolGuid, Mdio, diff --git a/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf b/Platfor= m/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf index faab1f7..d9878eb 100644 --- a/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf +++ b/Platform/Marvell/Drivers/Net/MvMdioDxe/MvMdioDxe.inf @@ -62,8 +62,5 @@ [Protocols] gMarvellMdioProtocolGuid =20 -[Pcd] - gMarvellTokenSpaceGuid.PcdMdioBaseAddress - [Depex] TRUE diff --git a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c b/Platfor= m/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c index aeb6f7a..5821885 100644 --- a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c +++ b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.c @@ -41,6 +41,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include #include #include #include @@ -51,6 +52,19 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. =20 STATIC MARVELL_MDIO_PROTOCOL *Mdio; =20 +// +// Table with available Mdio controllers +// +STATIC UINT8 * CONST MdioDeviceTable =3D PcdGetPtr (PcdMdioControllers); +// +// Table with PHY to Mdio controller mappings +// +STATIC UINT8 * CONST Phy2MdioController =3D PcdGetPtr (PcdPhy2MdioControll= er); +// +// Table with PHYs' SMI addresses +// +STATIC UINT8 * CONST PhySmiAddresses =3D PcdGetPtr (PcdPhySmiAddresses); + STATIC MV_PHY_DEVICE MvPhyDevices[] =3D { { MV_PHY_DEVICE_1512, MvPhyInit1512 }, { 0, NULL } @@ -64,18 +78,18 @@ MvPhyStatus ( =20 EFI_STATUS MvPhyReset ( - IN UINT32 PhyAddr + IN PHY_DEVICE *PhyDev ) { UINT32 Reg =3D 0; INTN timeout =3D TIMEOUT; =20 - Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); Reg |=3D BMCR_RESET; - Mdio->Write(Mdio, PhyAddr, MII_BMCR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg); =20 while ((Reg & BMCR_RESET) && timeout--) { - Mdio->Read(Mdio, PhyAddr, MII_BMCR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); gBS->Stall(1000); } =20 @@ -99,7 +113,7 @@ MvPhyM88e1111sConfig ( (PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII_ID) || (PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII_RXID) || (PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII_TXID)) { - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_CR, &Reg); =20 if ((PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII) || (PhyDev->Connection =3D=3D PHY_CONNECTION_RGMII_ID)) { @@ -112,9 +126,9 @@ MvPhyM88e1111sConfig ( Reg |=3D MIIM_88E1111_TX_DELAY; } =20 - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_CR, Reg); =20 - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_SR, &Reg); =20 Reg &=3D ~(MIIM_88E1111_HWCFG_MODE_MASK); =20 @@ -123,50 +137,50 @@ MvPhyM88e1111sConfig ( else Reg |=3D MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; =20 - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_SR, Reg); } =20 if (PhyDev->Connection =3D=3D PHY_CONNECTION_SGMII) { - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_SR, &Reg); =20 Reg &=3D ~(MIIM_88E1111_HWCFG_MODE_MASK); Reg |=3D MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; Reg |=3D MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; =20 - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_SR, Reg); } =20 if (PhyDev->Connection =3D=3D PHY_CONNECTION_RTBI) { - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_CR, &Reg); Reg |=3D (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_CR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_CR, Reg); =20 - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_SR, &Reg); Reg &=3D ~(MIIM_88E1111_HWCFG_MODE_MASK | MIIM_88E1111_HWCFG_FIBER_COPPER_RES); Reg |=3D 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_SR, Reg); =20 /* Soft reset */ - MvPhyReset(PhyDev->Addr); + MvPhyReset (PhyDev); =20 - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_EX= T_SR, &Reg); Reg &=3D ~(MIIM_88E1111_HWCFG_MODE_MASK | MIIM_88E1111_HWCFG_FIBER_COPPER_RES); Reg |=3D MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; - Mdio->Write(Mdio, PhyDev->Addr, MIIM_88E1111_PHY_EXT_SR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1111_PHY_E= XT_SR, Reg); } =20 - Mdio->Read(Mdio, PhyDev->Addr, MII_BMCR, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, &Reg); Reg |=3D (BMCR_ANENABLE | BMCR_ANRESTART); Reg &=3D ~BMCR_ISOLATE; - Mdio->Write(Mdio, PhyDev->Addr, MII_BMCR, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMCR, Reg); =20 /* Soft reset */ - MvPhyReset(PhyDev->Addr); + MvPhyReset (PhyDev); =20 - MvPhyReset(PhyDev->Addr); + MvPhyReset (PhyDev); =20 return EFI_SUCCESS; } @@ -179,7 +193,7 @@ MvPhyParseStatus ( UINT32 Data; UINT32 Speed; =20 - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_STAT= US, &Data); =20 if ((Data & MIIM_88E1xxx_PHYSTAT_LINK) && !(Data & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { @@ -196,7 +210,7 @@ MvPhyParseStatus ( if ((i++ % 1000) =3D=3D 0) DEBUG((DEBUG_ERROR, ".")); gBS->Stall(1000); - Mdio->Read(Mdio, PhyDev->Addr, MIIM_88E1xxx_PHY_STATUS, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MIIM_88E1xxx_PHY_= STATUS, &Data); } DEBUG((DEBUG_ERROR," done\n")); gBS->Stall(500000); @@ -241,7 +255,7 @@ MvPhyParseStatus ( STATIC VOID MvPhy1512WriteBits ( - IN UINT32 PhyAddr, + IN PHY_DEVICE *PhyDev, IN UINT8 RegNum, IN UINT16 Offset, IN UINT16 Len, @@ -254,19 +268,18 @@ MvPhy1512WriteBits ( else Mask =3D (1 << (Len + Offset)) - (1 << Offset); =20 - Mdio->Read(Mdio, PhyAddr, RegNum, &Reg); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, &Reg); =20 Reg &=3D ~Mask; Reg |=3D Data << Offset; =20 - Mdio->Write(Mdio, PhyAddr, RegNum, Reg); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, RegNum, Reg); } =20 STATIC EFI_STATUS MvPhyInit1512 ( IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN UINT32 PhyAddr, IN OUT PHY_DEVICE *PhyDev ) { @@ -278,28 +291,28 @@ MvPhyInit1512 ( * Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 Rev A0, * Errata Section 3.1 - needed in SGMII mode. */ - Mdio->Write(Mdio, PhyAddr, 22, 0x00ff); - Mdio->Write(Mdio, PhyAddr, 17, 0x214B); - Mdio->Write(Mdio, PhyAddr, 16, 0x2144); - Mdio->Write(Mdio, PhyAddr, 17, 0x0C28); - Mdio->Write(Mdio, PhyAddr, 16, 0x2146); - Mdio->Write(Mdio, PhyAddr, 17, 0xB233); - Mdio->Write(Mdio, PhyAddr, 16, 0x214D); - Mdio->Write(Mdio, PhyAddr, 17, 0xCC0C); - Mdio->Write(Mdio, PhyAddr, 16, 0x2159); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x00ff); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x214B); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2144); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0x0C28); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2146); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xB233); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x214D); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 17, 0xCC0C); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 16, 0x2159); =20 /* Reset page selection and select page 0x12 */ - Mdio->Write(Mdio, PhyAddr, 22, 0x0000); - Mdio->Write(Mdio, PhyAddr, 22, 0x0012); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0012); =20 /* Write HWCFG_MODE =3D SGMII to Copper */ - MvPhy1512WriteBits(PhyAddr, 20, 0, 3, 1); + MvPhy1512WriteBits(PhyDev, 20, 0, 3, 1); =20 /* Phy reset - necessary after changing mode */ - MvPhy1512WriteBits(PhyAddr, 20, 15, 1, 1); + MvPhy1512WriteBits(PhyDev, 20, 15, 1, 1); =20 /* Reset page selection */ - Mdio->Write(Mdio, PhyAddr, 22, 0x0000); + Mdio->Write (Mdio, PhyDev->Addr, PhyDev->MdioIndex, 22, 0x0000); gBS->Stall(100); } =20 @@ -309,7 +322,7 @@ MvPhyInit1512 ( if (!PcdGetBool (PcdPhyStartupAutoneg)) return EFI_SUCCESS; =20 - Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); =20 if ((Data & BMSR_ANEGCAPABLE) && !(Data & BMSR_ANEGCOMPLETE)) { =20 @@ -322,12 +335,12 @@ MvPhyInit1512 ( } =20 gBS->Stall(1000); /* 1 ms */ - Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); } PhyDev->LinkUp =3D TRUE; DEBUG((DEBUG_INFO, "MvPhyDxe: link up\n")); } else { - Mdio->Read(Mdio, PhyAddr, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); =20 if (Data & BMSR_LSTATUS) { PhyDev->LinkUp =3D TRUE; @@ -345,7 +358,7 @@ MvPhyInit1512 ( EFI_STATUS MvPhyInit ( IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN UINT32 PhyAddr, + IN UINT32 PhyIndex, IN PHY_CONNECTION PhyConnection, IN OUT PHY_DEVICE **OutPhyDev ) @@ -353,6 +366,7 @@ MvPhyInit ( EFI_STATUS Status; PHY_DEVICE *PhyDev; UINT8 *DeviceIds; + UINT8 MdioIndex; INTN i; =20 Status =3D gBS->LocateProtocol ( @@ -363,12 +377,20 @@ MvPhyInit ( if (EFI_ERROR(Status)) return Status; =20 + MdioIndex =3D Phy2MdioController[PhyIndex]; + + /* Verify correctness of PHY <-> MDIO assignment */ + if (!MVHW_DEV_ENABLED (Mdio, MdioIndex) || MdioIndex >=3D Mdio->Controll= erCount) { + DEBUG ((DEBUG_ERROR, "MvPhyDxe: Incorrect Mdio controller assignment f= or PHY#%d", PhyIndex)); + return EFI_INVALID_PARAMETER; + } + /* perform setup common for all PHYs */ PhyDev =3D AllocateZeroPool (sizeof (PHY_DEVICE)); - PhyDev->Addr =3D PhyAddr; + PhyDev->Addr =3D PhySmiAddresses[PhyIndex]; PhyDev->Connection =3D PhyConnection; DEBUG((DEBUG_INFO, "MvPhyDxe: PhyAddr is %d, connection %d\n", - PhyAddr, PhyConnection)); + PhyDev->Addr, PhyConnection)); *OutPhyDev =3D PhyDev; =20 DeviceIds =3D PcdGetPtr (PcdPhyDeviceIds); @@ -377,7 +399,7 @@ MvPhyInit ( if (MvPhyDevices[i].DevId =3D=3D DeviceIds[i]) { ASSERT (MvPhyDevices[i].DevInit !=3D NULL); /* proceed with PHY-specific initialization */ - return MvPhyDevices[i].DevInit(Snp, PhyAddr, PhyDev); + return MvPhyDevices[i].DevInit (Snp, PhyDev); } } =20 @@ -395,8 +417,8 @@ MvPhyStatus ( { UINT32 Data; =20 - Mdio->Read(Mdio, PhyDev->Addr, MII_BMSR, &Data); - Mdio->Read(Mdio, PhyDev->Addr, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); + Mdio->Read (Mdio, PhyDev->Addr, PhyDev->MdioIndex, MII_BMSR, &Data); =20 if ((Data & BMSR_LSTATUS) =3D=3D 0) { PhyDev->LinkUp =3D FALSE; diff --git a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h b/Platfor= m/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h index 6bd06c5..0c3d935 100644 --- a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h +++ b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.h @@ -174,7 +174,6 @@ typedef EFI_STATUS (*MV_PHY_DEVICE_INIT) ( IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN UINT32 PhyAddr, IN OUT PHY_DEVICE *PhyDev ); =20 @@ -187,7 +186,6 @@ STATIC EFI_STATUS MvPhyInit1512 ( IN CONST MARVELL_PHY_PROTOCOL *Snp, - IN UINT32 PhyAddr, IN OUT PHY_DEVICE *PhyDev ); =20 diff --git a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf b/Platf= orm/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf index c262ce4..f96cf35 100644 --- a/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf +++ b/Platform/Marvell/Drivers/Net/Phy/MvPhyDxe/MvPhyDxe.inf @@ -63,8 +63,10 @@ gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes + gMarvellTokenSpaceGuid.PcdMdioControllers + gMarvellTokenSpaceGuid.PcdPhy2MdioController gMarvellTokenSpaceGuid.PcdPhyDeviceIds + gMarvellTokenSpaceGuid.PcdPhySmiAddresses gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg =20 [Depex] diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 620bd5c..2827976 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -519,14 +519,14 @@ Pp2DxePhyInitialize ( return Status; } =20 - if (Pp2Context->Port.PhyAddr =3D=3D 0xff) { + if (Pp2Context->Port.PhyIndex =3D=3D 0xff) { /* PHY iniitalization not required */ return EFI_SUCCESS; } =20 Status =3D Pp2Context->Phy->Init( Pp2Context->Phy, - Pp2Context->Port.PhyAddr, + Pp2Context->Port.PhyIndex, Pp2Context->Port.PhyInterface, &Pp2Context->PhyDev ); @@ -1147,25 +1147,25 @@ Pp2DxeParsePortPcd ( IN INTN Index ) { - UINT8 *PortIds, *GopIndexes, *PhyConnectionTypes, *AlwaysUp, *Speed, *Ph= yAddresses; + UINT8 *PortIds, *GopIndexes, *PhyConnectionTypes, *AlwaysUp, *Speed, *Ph= yIndexes; =20 PortIds =3D PcdGetPtr (PcdPp2PortIds); GopIndexes =3D PcdGetPtr (PcdPp2GopIndexes); - PhyConnectionTypes =3D PcdGetPtr (PcdPhyConnectionTypes); - PhyAddresses =3D PcdGetPtr (PcdPhySmiAddresses); + PhyConnectionTypes =3D PcdGetPtr (PcdPp2PhyConnectionTypes); + PhyIndexes =3D PcdGetPtr (PcdPp2PhyIndexes); AlwaysUp =3D PcdGetPtr (PcdPp2InterfaceAlwaysUp); Speed =3D PcdGetPtr (PcdPp2InterfaceSpeed); =20 ASSERT (PcdGetSize (PcdPp2GopIndexes) =3D=3D PcdGetSize (PcdPp2PortIds)); - ASSERT (PcdGetSize (PcdPhyConnectionTypes) =3D=3D PcdGetSize (PcdPp2Port= Ids)); + ASSERT (PcdGetSize (PcdPp2PhyConnectionTypes) =3D=3D PcdGetSize (PcdPp2P= ortIds)); ASSERT (PcdGetSize (PcdPp2InterfaceAlwaysUp) =3D=3D PcdGetSize (PcdPp2Po= rtIds)); ASSERT (PcdGetSize (PcdPp2InterfaceSpeed) =3D=3D PcdGetSize (PcdPp2PortI= ds)); - ASSERT (PcdGetSize (PcdPhySmiAddresses) =3D=3D PcdGetSize (PcdPp2PortIds= )); + ASSERT (PcdGetSize (PcdPp2PhyIndexes) =3D=3D PcdGetSize (PcdPp2PortIds)); =20 Pp2Context->Port.Id =3D PortIds[Index]; Pp2Context->Port.GopIndex =3D GopIndexes[Index]; Pp2Context->Port.PhyInterface =3D PhyConnectionTypes[Index]; - Pp2Context->Port.PhyAddr =3D PhyAddresses[Index]; + Pp2Context->Port.PhyIndex =3D PhyIndexes[Index]; Pp2Context->Port.AlwaysUp =3D AlwaysUp[Index]; Pp2Context->Port.Speed =3D Speed[Index]; } diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.h index cde2995..60f40be 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h @@ -327,7 +327,7 @@ struct Pp2DxePort { UINT16 RxRingSize; =20 INT32 PhyInterface; - UINTN PhyAddr; + UINT32 PhyIndex; BOOLEAN Link; BOOLEAN Duplex; BOOLEAN AlwaysUp; diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index 752fcc0..b4568d8 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -71,12 +71,12 @@ gMarvellPhyProtocolGuid =20 [Pcd] - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes - gMarvellTokenSpaceGuid.PcdPhySmiAddresses gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes gMarvellTokenSpaceGuid.PcdPp2Port2Controller gMarvellTokenSpaceGuid.PcdPp2PortIds =20 diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marv= ell/Include/Library/MvHwDescLib.h index 6ad1bc2..9ae03d0 100644 --- a/Platform/Marvell/Include/Library/MvHwDescLib.h +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h @@ -70,6 +70,16 @@ typedef struct { } MVHW_I2C_DESC; =20 // +// MDIO devices description template definition +// +#define MVHW_MAX_MDIO_DEVS 2 + +typedef struct { + UINT8 MdioDevCount; + UINTN MdioBaseAddresses[MVHW_MAX_MDIO_DEVS]; +} MVHW_MDIO_DESC; + +// // NonDiscoverable devices description template definition // #define MVHW_MAX_XHCI_DEVS 4 @@ -168,6 +178,19 @@ MVHW_I2C_DESC mA7k8kI2cDescTemplate =3D {\ } =20 // +// Platform description of MDIO devices +// +#define MVHW_CP0_MDIO_BASE 0xF212A200 +#define MVHW_CP1_MDIO_BASE 0xF412A200 + +#define DECLARE_A7K8K_MDIO_TEMPLATE \ +STATIC \ +MVHW_MDIO_DESC mA7k8kMdioDescTemplate =3D {\ + 2,\ + { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ +} + +// // Platform description of NonDiscoverable devices // #define MVHW_CP0_XHCI0_BASE 0xF2500000 diff --git a/Platform/Marvell/Include/Protocol/Mdio.h b/Platform/Marvell/In= clude/Protocol/Mdio.h index 10acad4..d077a8f 100644 --- a/Platform/Marvell/Include/Protocol/Mdio.h +++ b/Platform/Marvell/Include/Protocol/Mdio.h @@ -35,6 +35,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #ifndef __MDIO_H__ #define __MDIO_H__ =20 +#include + #define MARVELL_MDIO_PROTOCOL_GUID { 0x40010b03, 0x5f08, 0x496a, { 0xa2, 0= x64, 0x10, 0x5e, 0x72, 0xd3, 0x71, 0xaa }} =20 typedef struct _MARVELL_MDIO_PROTOCOL MARVELL_MDIO_PROTOCOL; @@ -44,6 +46,7 @@ EFI_STATUS (EFIAPI *MARVELL_MDIO_READ) ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN UINT32 *Data ); @@ -53,6 +56,7 @@ EFI_STATUS (EFIAPI *MARVELL_MDIO_WRITE) ( IN CONST MARVELL_MDIO_PROTOCOL *This, IN UINT32 PhyAddr, + IN UINT32 MdioIndex, IN UINT32 RegOff, IN UINT32 Data ); @@ -60,6 +64,8 @@ EFI_STATUS struct _MARVELL_MDIO_PROTOCOL { MARVELL_MDIO_READ Read; MARVELL_MDIO_WRITE Write; + UINTN BaseAddresses[MVHW_MAX_MDIO_DEVS]; + UINTN ControllerCount; }; =20 extern EFI_GUID gMarvellMdioProtocolGuid; diff --git a/Platform/Marvell/Include/Protocol/MvPhy.h b/Platform/Marvell/I= nclude/Protocol/MvPhy.h index a91759a..99c75b3 100644 --- a/Platform/Marvell/Include/Protocol/MvPhy.h +++ b/Platform/Marvell/Include/Protocol/MvPhy.h @@ -62,6 +62,7 @@ typedef enum { =20 typedef struct { UINT32 Addr; + UINT8 MdioIndex; BOOLEAN LinkUp; BOOLEAN FullDuplex; BOOLEAN AutoNegotiation; diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 00d99fa..cd2f3ad 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -160,19 +160,21 @@ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ 0x0 }|VOID*|0x30000207 =20 #MDIO - gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0|UINT64|0x3000043 + gMarvellTokenSpaceGuid.PcdMdioControllers|{ 0x0 }|VOID*|0x3000043 =20 #PHY - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0 }|VOID*|0x3000044 + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }|VOID*|0x3000027 gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }|VOID*|0x3000095 + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024 gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE|BOOLEAN|0x3000070 =20 #NET - gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024 gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x0 }|VOID*|0x3000028 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029 gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ 0x0 }|VOID*|0x3000044 + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0x0 }|VOID*|0x3000045 gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0 }|VOID*|0x300002D gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C =20 diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marve= ll/Documentation/PortingGuide.txt index 8a9f603..52968ae 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -125,25 +125,15 @@ PHY Driver configuration MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. Currently only 1518 series PHYs are supported. Following PCDs are required: =20 - - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes - (list of values corresponding to PHY_CONNECTION enum) - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg (boolean - if true, driver waits for autonegotiation on startup) - gMarvellTokenSpaceGuid.PcdPhyDeviceIds (list of values corresponding to MV_PHY_DEVICE_ID enum) + - gMarvellTokenSpaceGuid.PcdPhySmiAddresses + (addresses of PHY devices) + - gMarvellTokenSpaceGuid.PcdPhy2MdioController + (Array specifying, which Mdio controller the PHY is attached to) =20 -PHY_CONNECTION enum type is defined as follows: - - typedef enum { - 0 PHY_CONNECTION_RGMII, - 1 PHY_CONNECTION_RGMII_ID, - 2 PHY_CONNECTION_RGMII_TXID, - 3 PHY_CONNECTION_RGMII_RXID, - 4 PHY_CONNECTION_SGMII, - 5 PHY_CONNECTION_RTBI, - 6 PHY_CONNECTION_XAUI, - 7 PHY_CONNECTION_RXAUI - } PHY_CONNECTION; =20 MV_PHY_DEVICE_ID: =20 @@ -152,11 +142,8 @@ MV_PHY_DEVICE_ID: } MV_PHY_DEVICE_ID; =20 It should be extended when adding support for other PHY models. -Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be: - - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 } =20 -with disabled autonegotiation: +Disable autonegotiation: =20 gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 @@ -170,8 +157,9 @@ MDIO configuration MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: =20 - - gMarvellTokenSpaceGuid.PcdMdioBaseAddress - (base address of SMI management register) + - gMarvellTokenSpaceGuid.PcdMdioControllers + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) =20 =20 I2C configuration @@ -248,8 +236,26 @@ are required to operate: - gMarvellTokenSpaceGuid.PcdPp2Port2Controller (Array specifying, to which controller the port belongs to) =20 - - gMarvellTokenSpaceGuid.PcdPhySmiAddresses - (Addresses of PHY devices) + - gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes + (List of values corresponding to PHY_CONNECTION enum, which + is defined as follows: + + typedef enum { + 0 PHY_CONNECTION_RGMII, + 1 PHY_CONNECTION_RGMII_ID, + 2 PHY_CONNECTION_RGMII_TXID, + 3 PHY_CONNECTION_RGMII_RXID, + 4 PHY_CONNECTION_SGMII, + 5 PHY_CONNECTION_RTBI, + 6 PHY_CONNECTION_XAUI, + 7 PHY_CONNECTION_RXAUI + } PHY_CONNECTION; ) + + - gMarvellTokenSpaceGuid.PcdPp2PhyIndexes + (Array specifying, to which PHY from + gMarvellTokenSpaceGuid.PcdPhyDeviceIds is used. If none, + e.g. in 10G SFI in-band link detection, 0xFF value must + be specified) =20 - gMarvellTokenSpaceGuid.PcdPp2PortIds (Identificators of PP2 ports) --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 07:21:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1507275885497832.4401951894878; Fri, 6 Oct 2017 00:44:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 815C92095B064; Fri, 6 Oct 2017 00:41:13 -0700 (PDT) Received: from mail-lf0-x234.google.com (mail-lf0-x234.google.com [IPv6:2a00:1450:4010:c07::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0BD2C21EA15BB for ; Fri, 6 Oct 2017 00:41:12 -0700 (PDT) Received: by mail-lf0-x234.google.com with SMTP id l23so12551465lfk.10 for ; Fri, 06 Oct 2017 00:44:35 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id v29sm194155ljv.27.2017.10.06.00.44.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 00:44:32 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2a00:1450:4010:c07::234; helo=mail-lf0-x234.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2dNcmvbC1ehcXvyOP2nq33iBKQIYxDsa8b6luaAWWcc=; b=ZA5bSJX7snrVLeFHb23GdwSM1qWDBWo+xCRsZp0ihgQSN04J4hxq1q3I+RmJkyvu3E eoQ0cE+kXHxjqk7f6pm5fbaLIXsopqVLH/emyaJMgexinB7UYlUMClN4bqB+6Z3uSFZZ E+Z2dETw6zCPRQB3N7EVQAIK80+VY6viWhZ/dZYzrXWDHFfxn1FefUSTduAJUmnw6o9G 2jmsbblT2De8hbBv8M346IxCLCw+HKBRrbkNQv/7MIxwTJ13SsU5x8LsMgkfuU4Q7QW2 +I1QyQX99420ziJZoQ9XX5lhzmH4RPqlUbecMpP5lIr5e5GB8aYEA3EwREuCFoeddmxI G/1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2dNcmvbC1ehcXvyOP2nq33iBKQIYxDsa8b6luaAWWcc=; b=LBPgfpNAOIvN7//aOQRitnKN7yV+ZuD4GYW1I4m3F97MlC8ecPCoi1i6W8WGdJsvOv D1X9Vfj5blGQH92r7L4VdTdw4qDGVitAYHx1/neVox0o5E6g6XXTLtWqUkCNfIsMzJZz kPftJdE7esIQanmy3NgwP8xZKWUMTDpzIRGcIHVdROw2SJnwVXdpV1p5P1HoK+6gTui7 aBT56Txki1vRHi6F6p6PTka/whR8HcHwStfsz/5rRlFT4yabRyUXiVkQmOoaVcb4L5qs ZGkgLNne3QVZdEyIRxABpYuJo5MpnqU0oRc6UuJ+jiOYBPHJ5UWH79ldkKi/p6sOQpy5 2xRA== X-Gm-Message-State: AMCzsaW5OjPWxiipzGGAjcO9pz9+MKZbZFs4S00dfm+qHXzOk/puQI81 fE70xo1wqTnoirTd1EzQ0u32h0xBAzU= X-Google-Smtp-Source: AOwi7QBrkO/tRZZRjpqYJOAqHmNI2ZphyDlI7xw7+ZjuU6e5M/nvm8HJPuf+TofMgpu3iPHtykK4/A== X-Received: by 10.25.148.217 with SMTP id o86mr461538lfk.254.1507275873384; Fri, 06 Oct 2017 00:44:33 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 6 Oct 2017 09:51:18 +0200 Message-Id: <1507276278-3608-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1507276278-3608-1-git-send-email-mw@semihalf.com> References: <1507276278-3608-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 5/5] Platform/Marvell/Armada: Remove ParsePcdLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Current PCD handling in libraries and drivers allow to get rid of this code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada.dsc.inc | 1 - Platform/Marvell/Include/Library/ParsePcdLib.h | 46 ---- Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.c | 228 ---------------= ----- Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.inf | 50 ----- 4 files changed, 325 deletions(-) diff --git a/Platform/Marvell/Armada/Armada.dsc.inc b/Platform/Marvell/Arma= da/Armada.dsc.inc index 9549091..679ba59 100644 --- a/Platform/Marvell/Armada/Armada.dsc.inc +++ b/Platform/Marvell/Armada/Armada.dsc.inc @@ -33,7 +33,6 @@ ArmPlatformLib|Platform/Marvell/Armada/Library/Armada70x0Lib/Armada70x0L= ib.inf ComPhyLib|Platform/Marvell/Library/ComPhyLib/ComPhyLib.inf MppLib|Platform/Marvell/Library/MppLib/MppLib.inf - ParsePcdLib|Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.inf UtmiPhyLib|Platform/Marvell/Library/UtmiPhyLib/UtmiPhyLib.inf =20 DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf diff --git a/Platform/Marvell/Include/Library/ParsePcdLib.h b/Platform/Marv= ell/Include/Library/ParsePcdLib.h deleted file mode 100644 index a255685..0000000 --- a/Platform/Marvell/Include/Library/ParsePcdLib.h +++ /dev/null @@ -1,46 +0,0 @@ -/*************************************************************************= ******* -Copyright (C) 2016 Marvell International Ltd. - -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute a= nd/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modific= ation, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -* Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -**************************************************************************= *****/ - -#ifndef __PARSEPCDLIB_H__ -#define __PARSEPCDLIB_H__ - -EFI_STATUS -ParsePcdString ( - IN CHAR16 *PcdString, - IN UINT8 Count, - OUT UINTN *ValueTable, - OUT CHAR16 **StrTable - ); - -#endif diff --git a/Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.c b/Platform/= Marvell/Library/ParsePcdLib/ParsePcdLib.c deleted file mode 100644 index 9a4be8e..0000000 --- a/Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.c +++ /dev/null @@ -1,228 +0,0 @@ -/*************************************************************************= ******* -Copyright (C) 2016 Marvell International Ltd. - -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute a= nd/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modific= ation, -are permitted provided that the following conditions are met: - -* Redistributions of source code must Retain the above copyright notice, - this list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -* Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS= " AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPL= IED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABL= E FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAM= AGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICE= S; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AN= D ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF T= HIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -**************************************************************************= *****/ -#define CHAR_NULL 0x0000 - -#include -#include -#include -#include - -STATIC -CHAR16 -CharToUpper ( - IN CHAR16 Char - ) -{ - - if (Char >=3D L'a' && Char <=3D L'z') { - return (CHAR16) (Char - (L'a' - L'A')); - } - - return Char; -} - -STATIC -BOOLEAN -IsDecimalDigitChar ( - IN CHAR16 Char - ) -{ - - return (BOOLEAN) (Char >=3D L'0' && Char <=3D L'9'); -} - - -STATIC -UINTN -HexCharToUintn ( - IN CHAR16 Char - ) -{ - if (IsDecimalDigitChar (Char)) { - return Char - L'0'; - } - - return (UINTN) (10 + CharToUpper (Char) - L'A'); -} - -STATIC -BOOLEAN -IsHexDigitCharacter ( - CHAR16 Char - ) -{ - - return (BOOLEAN) ((Char >=3D L'0' && Char <=3D L'9') || (Char >=3D L'A' = && - Char <=3D L'F') || (Char >=3D L'a' && Char <=3D L'f')); -} - -STATIC -UINTN -HexStrToUintn ( - CHAR16 *String - ) -{ - UINTN Result =3D 0; - - if (String =3D=3D NULL || StrSize(String) =3D=3D 0) { - return (UINTN)(-1); - } - - // Ignore spaces and tabs - while ((*String =3D=3D L' ') || (*String =3D=3D L'\t')) { - String++; - } - - // Ignore leading zeros after spaces - while (*String =3D=3D L'0') { - String++; - } - - if (CharToUpper (*String) !=3D L'X') { - return (UINTN)(-1); - } - - // Skip 'x' - String++; - - while (IsHexDigitCharacter (*String)) { - Result <<=3D 4; - Result +=3D HexCharToUintn (*String); - String++; - } - - return (UINTN) Result; -} - -STATIC -UINTN -DecimalStrToUintn ( - CHAR16 *String - ) -{ - UINTN Result =3D 0; - - while (IsDecimalDigitChar (*String)) { - Result =3D 10 * Result + (*String - L'0'); - String++; - } - - return Result; -} - -STATIC -UINTN -StrToUintn ( - CHAR16 *String - ) -{ - CHAR16 *Walker; - - // Chop off leading spaces - for (Walker =3D String; Walker !=3D NULL && *Walker !=3D CHAR_NULL && *W= alker =3D=3D L' '; Walker++); - - if (StrnCmp(Walker, L"0x", 2) =3D=3D 0 || StrnCmp(Walker, L"0X", 2) =3D= =3D 0) { - return HexStrToUintn (Walker); - } else { - return DecimalStrToUintn (Walker); - } -} - -EFI_STATUS -ParsePcdString ( - IN CHAR16 *PcdString, - IN UINT8 Count, - OUT UINTN *ValueTable, - OUT CHAR16 **StrTable - ) -{ - BOOLEAN ValueFlag =3D FALSE; - CHAR16 *Walker; - UINTN i, Tmp =3D 0; - - if (ValueTable !=3D NULL) { - ValueFlag =3D TRUE; - } - - // Set pointer at the end of PCD string - Walker =3D PcdString + StrLen (PcdString); - for (i =3D 0; i < Count; i++) { - while ((--Walker) >=3D PcdString) { - if (*Walker =3D=3D L';') { - // Cut off parsed chunk from PCD string by replacing ';' with - // null-terminator - *Walker =3D '\0'; - if (ValueFlag) { - Tmp =3D StrToUintn ((Walker + 1)); - if ((UINTN)(-1) =3D=3D Tmp) { - return EFI_INVALID_PARAMETER; - } - // Entry is parsed from the end to the beginning - // so fill table in the same manner - ValueTable[Count - (i + 1)] =3D Tmp; - } else { - StrTable[Count - (i + 1)] =3D Walker + 1; - } - Walker--; - break; - } - if (Walker =3D=3D PcdString) { - if (ValueFlag) { - Tmp =3D StrToUintn ((Walker)); - if (Tmp =3D=3D (UINTN)(-1)) { - return EFI_INVALID_PARAMETER; - } - } - // Last device's entry should be added to the table here. - // If not, return error - if (i !=3D (Count - 1)) { - DEBUG((DEBUG_ERROR, "ParsePcdLib: Please set PCD value for every= " - "device\n")); - return EFI_INVALID_PARAMETER; - } - // We parse from the end to the beginning - // so fill table in the same manner - if (ValueFlag) { - ValueTable[Count - (i + 1)] =3D Tmp; - } else { - StrTable[Count - (i + 1)] =3D Walker; - } - // End both loops - return EFI_SUCCESS; - } - } - } - - return EFI_SUCCESS; -} diff --git a/Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.inf b/Platfor= m/Marvell/Library/ParsePcdLib/ParsePcdLib.inf deleted file mode 100644 index b4db621..0000000 --- a/Platform/Marvell/Library/ParsePcdLib/ParsePcdLib.inf +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (C) 2016 Marvell International Ltd. -# -# Marvell BSD License Option -# -# If you received this File from Marvell, you may opt to use, redistribute= and/or -# modify this File under the following licensing terms. -# Redistribution and use in source and binary forms, with or without modif= ication, -# are permitted provided that the following conditions are met: -# -# * Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# * Neither the name of Marvell nor the names of its contributors may be -# used to endorse or promote products derived from this software without -# specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS = IS" AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IM= PLIED -# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIA= BLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL D= AMAGES -# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVI= CES; -# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED = AND ON -# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF= THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D ParsePcdLib - FILE_GUID =3D 698d85a0-a952-453e-b8a4-1d6ea338a38e - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D ParsePcdLib - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - -[LibraryClasses] - ArmLib - DebugLib - -[Sources.common] - ParsePcdLib.c --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel