From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506655612436130.7423454126772; Thu, 28 Sep 2017 20:26:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 171122095E519; Thu, 28 Sep 2017 20:23:36 -0700 (PDT) Received: from mail-pf0-x230.google.com (mail-pf0-x230.google.com [IPv6:2607:f8b0:400e:c00::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C29EF20945B68 for ; Thu, 28 Sep 2017 20:23:34 -0700 (PDT) Received: by mail-pf0-x230.google.com with SMTP id d187so53972pfg.11 for ; Thu, 28 Sep 2017 20:26:50 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.26.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:26:49 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::230; helo=mail-pf0-x230.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dMU2+Ul/FbJecpiRRVMr0Vs9SCrnmQAu/suuO/ovyfI=; b=NTlk/jdgUp0DwzY0JYx+3ty2JH4fcW1XT/XDHSR3qL9FXLMUbwWC/tfVSAEkaU+2wN 91R5BVUVMRmONLvoUfcz51Yz8mhvyW5PCNsyoh2yf4jtF/7NoOy+2ALPZXchWcbZ+83L C9ZbqKlKOdr1pItds8ZoF+SbQpnKWY1HRjkfk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dMU2+Ul/FbJecpiRRVMr0Vs9SCrnmQAu/suuO/ovyfI=; b=tb0AVajwUpRXMMAVxAbt7wAcZZkPoC2JNiaAVHqIS3cGpb641PVguAN7qSGtGkibow 2TfBOvFsc09rmkt2qKcQYPWqwAO5KFFlbQmmRg7294IWD78ELwcpyjFftgYqP2/fVO54 CxckouYvZyhsgSFAsAXQ8fFtNszuTp13ld1o5BOPJe2QvyVNSc32hh9EbZqSS+k95hzG twBSDZZ87iPF+JwjfQcHECU1PU2cRIFU15Vsk9J602EirSM641LryQ+qtZ4rDga/Dqpz PMb2xKkH0pWCBkGKYrFCrv+7DMzXBqRF4KVsCDQA8uEVBi5xD/HNDdemjBNW4SxbKcYX VMtA== X-Gm-Message-State: AHPjjUjgXvTJYbg4yD6YxXFAU0ifACmQASYVpZxEEIBv82DOMx9vISRe 1xJrrzO5D5Dx79MZSClehdL4Aw== X-Google-Smtp-Source: AOwi7QAhU4ekNMvew+BpG2qmWPMe49ZxsqKwHsdM5gYPcJqHO3zZQi0u/kqZz+RBJHMsq2d8s/myeg== X-Received: by 10.99.7.21 with SMTP id 21mr2825157pgh.130.1506655609866; Thu, 28 Sep 2017 20:26:49 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:40 +0800 Message-Id: <1506655190-56231-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 01/11] Hisilicon/D05: Modify dsc and fdf file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" 1. Add Drivers/SasPlatform; 2. Add Drivers/Net/SnpPlatform; Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D05/D05.dsc | 5 ----- Platform/Hisilicon/D05/D05.fdf | 4 +++- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 3cdb1b1..7cd5758 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -538,11 +538,6 @@ =20 Platform/Hisilicon/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf =20 - # - #network - # - Platform/Hisilicon/D05/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf - MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index b6d0e42..a5e6546 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -247,7 +247,8 @@ READ_LOCK_STATUS =3D TRUE #Network # =20 - INF Platform/Hisilicon/D05/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf + INF Platform/Hisilicon/D05/Drivers/Net/SnpPlatform/SnpPlatform.inf + INF Platform/Hisilicon/D05/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf =20 INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf @@ -292,6 +293,7 @@ READ_LOCK_STATUS =3D TRUE # INF Platform/Hisilicon/D05/Drivers/Sm750Dxe/UefiSmi.inf INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + INF Platform/Hisilicon/D05/Drivers/SasPlatform/SasPlatform.inf INF Platform/Hisilicon/D05/Drivers/Sas/SasDxeDriver.inf =20 # --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" 1. Add Drivers/SasPlatform; 2. Add Drivers/Net/SnpPlatform; Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D03/D03.dsc | 5 ----- Platform/Hisilicon/D03/D03.fdf | 4 +++- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index afea162..7e25ffb 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -418,11 +418,6 @@ =20 Platform/Hisilicon/D03/Drivers/Ipmi/ipmiInterfaceDxe/IpmiInterfaceDxe.inf =20 - # - #network - # - Platform/Hisilicon/D03/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf - MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index b62b908..37a7e28 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -242,7 +242,8 @@ READ_LOCK_STATUS =3D TRUE #Network # =20 - INF Platform/Hisilicon/D03/Drivers/Net/SnpPV660Dxe/SnpPV600Dxe.inf + INF Platform/Hisilicon/D03/Drivers/Net/SnpPlatform/SnpPlatform.inf + INF Platform/Hisilicon/D03/Drivers/Net/SnpPV600Dxe/SnpPV600Dxe.inf =20 INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf @@ -271,6 +272,7 @@ READ_LOCK_STATUS =3D TRUE # INF Platform/Hisilicon/D03/Drivers/Sm750Dxe/UefiSmi.inf =20 + INF Platform/Hisilicon/D03/Drivers/SasPlatform/SasPlatform.inf INF Platform/Hisilicon/D03/Drivers/Sas/SasDxeDriver.inf =20 # --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" The drivers build from separate sources, their GUID should be different. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf = | 2 +- Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf = | 2 +- Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf = | 2 +- Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf = | 2 +- Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf = | 2 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf = | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf = | 2 +- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf = | 2 +- Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf = | 2 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf = | 2 +- Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.in= f | 2 +- Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf = | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLib.inf = | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf = | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf b/P= latform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf index 5506a58..3f3f81c 100644 --- a/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf +++ b/Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D EarlyConfigPeim - FILE_GUID =3D A181AD33-E64A-4084-A54A-A69DF1FB0ABF + FILE_GUID =3D ECAE8400-9CCE-4BA5-9B44-74CAABE4DA79 MODULE_TYPE =3D PEIM VERSION_STRING =3D 1.0 ENTRY_POINT =3D EarlyConfigEntry diff --git a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf b/Plat= form/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf index c952414..e881899 100644 --- a/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf +++ b/Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D FdtUpdateLib - FILE_GUID =3D 02CF1727-E697-47fc-8CC2-5DCB81B26DD9 + FILE_GUID =3D 0F9ADE24-46B4-4506-8802-60C519B56133 MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D FdtUpdateLib diff --git a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.i= nf b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf index 4d2dbba..ab3b62b 100644 --- a/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D PlatformPciLib - FILE_GUID =3D 61b7276a-fc67-11e5-82fd-47ea9896dd5d + FILE_GUID =3D 128F1E1E-A921-4277-A796-A4A47B96B7D2 MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 =20 diff --git a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf b/P= latform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf index df5adf1..4c5955f 100644 --- a/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf +++ b/Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D OemNicConfig - FILE_GUID =3D 3A23A929-1F38-4d04-8A01-38AD993EB2CE + FILE_GUID =3D BF422A22-CA90-4C34-95B9-3D147AF09E70 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D OemNicConfigEntry diff --git a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf b= /Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf index 9569b91..2d9d53d 100755 --- a/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf +++ b/Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D FdtUpdateLib - FILE_GUID =3D 02CF1727-E697-47fc-8CC2-5DCB81B26DD9 + FILE_GUID =3D B80B9FF1-FAB9-4BE5-B602-5ABAA6B7A3D4 MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D FdtUpdateLib diff --git a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf = b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf index 9d8ea7e..0f6b68d 100644 --- a/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf +++ b/Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf @@ -17,7 +17,7 @@ [Defines] INF_VERSION =3D 0x00010019 BASE_NAME =3D EarlyConfigPeimD05 - FILE_GUID =3D A181AD33-E64A-4084-A54A-A69DF1FB0ABF + FILE_GUID =3D 13525B94-06F0-41AC-8CAF-724B149FD259 MODULE_TYPE =3D PEIM VERSION_STRING =3D 1.0 ENTRY_POINT =3D EarlyConfigEntry diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf= b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf index 4fe7ac6..bf44ff7 100644 --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010019 BASE_NAME =3D OemMiscLibHi1616Evb - FILE_GUID =3D B9CE7465-21A2-4ecd-B347-BBDDBD098CEE + FILE_GUID =3D 751C7627-D5F8-499C-AEEEE-C87858759612 MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D OemMiscLib diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.i= nf b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf index cd64193..21bb33a 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010019 BASE_NAME =3D PlatformPciLib - FILE_GUID =3D 61b7276a-fc67-11e5-82fd-47ea9896dd5d + FILE_GUID =3D B94B8A3A-AD7D-4F26-B140-1E699682176B MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 =20 diff --git a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf b/Sil= icon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf index 174e967..89447cc 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D IoInitDxe - FILE_GUID =3D e99c606a-5626-11e5-b09e-bb93f4e4c400 + FILE_GUID =3D 28C9B7DE-AAD6-4E9B-811B-050AD3DAB9A3 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 =20 diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf = b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index 686d041..ee9dbed 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -17,7 +17,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D PcieInitDxe - FILE_GUID =3D 2D53A704-A544-4A82-83DF-FFECF4B4AA97 + FILE_GUID =3D 8EB6E216-BA47-4B30-B68A-2B371F7232A6 MODULE_TYPE =3D DXE_DRIVER VERSION_STRING =3D 1.0 ENTRY_POINT =3D PcieInitEntry diff --git a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTim= eClockLib.inf b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231Real= TimeClockLib.inf index 6faefb1..17d59ee 100644 --- a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockL= ib.inf +++ b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockL= ib.inf @@ -20,7 +20,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D DS3231RealTimeClockLib - FILE_GUID =3D 470DFB96-E205-4515-A75E-2E60F853E79D + FILE_GUID =3D 5FD8127D-11E1-488F-8CF1-A143157D6BF0 MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D RealTimeClockLib diff --git a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPort= Lib.inf b/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib= .inf index d7957ea..df65d4b 100644 --- a/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf +++ b/Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf @@ -17,7 +17,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D Dw8250SerialPortLib - FILE_GUID =3D 16D53E86-7EA6-47bd-861F-511ED9B8ABE0 + FILE_GUID =3D 78337705-D2A8-4EA7-9C18-27FC4A8A2C6E MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D SerialPortLib diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf b/Silicon/Hisilico= n/Library/I2CLib/I2CLib.inf index 7f95124..9bca88f 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D I2CLib - FILE_GUID =3D FC5651CA-55D8-4fd2-B6D3-A284D993ABA2 + FILE_GUID =3D 162F2DF1-DBF8-41E6-9792-92A96ADEAB40 MODULE_TYPE =3D BASE VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D I2CLib diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf b/Silicon/H= isilicon/Library/I2CLib/I2CLibRuntime.inf index 4990072..1bb4f5c 100644 --- a/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf +++ b/Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf @@ -16,7 +16,7 @@ [Defines] INF_VERSION =3D 0x00010005 BASE_NAME =3D I2CLibRuntime - FILE_GUID =3D FC5651CA-55D8-4fd2-B6D3-A284D993ABA2 + FILE_GUID =3D 2E602B32-9203-44A4-BF28-1FF98BD89523 MODULE_TYPE =3D DXE_RUNTIME_DRIVER VERSION_STRING =3D 1.0 LIBRARY_CLASS =3D I2CLib --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506655621196986.1796714391245; Thu, 28 Sep 2017 20:27:01 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with 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1ujdocfKupj62Y6gdAReHmukC0wFxOBUkCNqyr7PM28WRg/wveow60JwFUphE45FkzUZ 970A== X-Gm-Message-State: AHPjjUhEuSSVOjStRpDwgq9LUu/jeKyKawSEGuoP51TJMAW1WVB6gCHP Sc+Z57QCWL6WfJ85er5oCih/Eg== X-Google-Smtp-Source: AOwi7QBy9wK9BxViS68HK9bUixPZJO/kBFnTICFjgu2ue5lbmIXulZMquJ3S77jNuuxtXXnOWmpf0g== X-Received: by 10.84.133.98 with SMTP id 89mr5674740plf.294.1506655618663; Thu, 28 Sep 2017 20:26:58 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:43 +0800 Message-Id: <1506655190-56231-5-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 04/11] Hisilicon D03/D05: get firmware version from FIRMWARE_VER X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , Ming Huang , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ming Huang Value of the environment variable FIRMWARE_VER is GIT SHA by default, and you can add the environment variable FIRMWARE_VER to EXTRA_OPTIONS at build time to specify something else, eg. "16.12-". Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D03/D03.dsc | 6 +++++- Platform/Hisilicon/D05/D05.dsc | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index 7e25ffb..fca6781 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -170,7 +170,11 @@ gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000 =20 =20 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D03 = UEFI 16.12 Release" + !ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_V= ER)" + !else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development = build base on Hisilicon D03 UEFI 17.10 Release" + !endif =20 gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" =20 diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 7cd5758..aa61c0e 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -188,7 +188,11 @@ =20 gHisiTokenSpaceGuid.PcdIsMPBoot|1 gHisiTokenSpaceGuid.PcdSocketMask|0x3 - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 = UEFI 16.12 Release" + !ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_V= ER)" + !else + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development = build base on Hisilicon D05 UEFI 17.10 Release" + !endif =20 gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18" =20 --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Io BAR should be based IoBase and Mem BAR should be based PciRegionBase. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 37 ++++++++= ++++-------- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 15 ++++++-- 2 files changed, 35 insertions(+), 17 deletions(-) diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/S= ilicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index a970da6..e3d3988 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -1410,9 +1410,8 @@ SetResource( Ptr->ResType =3D 1; Ptr->GenFlag =3D 0; Ptr->SpecificFlag =3D 0; - /* This is PCIE Device Bus which start address is the low 32bit of= mem base*/ - Ptr->AddrRangeMin =3D (RootBridgeInstance->ResAllocNode[Index].Bas= e - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE Device Iobar address should be based on IoBase */ + Ptr->AddrRangeMin =3D RootBridgeInstance->IoBase; Ptr->AddrRangeMax =3D 0; Ptr->AddrTranslationOffset =3D \ (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; @@ -1429,9 +1428,13 @@ SetResource( Ptr->GenFlag =3D 0; Ptr->SpecificFlag =3D 0; Ptr->AddrSpaceGranularity =3D 32; - /* This is PCIE Device Bus which start address is the low 32bit of= mem base*/ - Ptr->AddrRangeMin =3D (RootBridgeInstance->ResAllocNode[Index].Bas= e - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } + Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocNode[Index].Base= - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax =3D 0; Ptr->AddrTranslationOffset =3D \ (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; @@ -1448,9 +1451,13 @@ SetResource( Ptr->GenFlag =3D 0; Ptr->SpecificFlag =3D 6; Ptr->AddrSpaceGranularity =3D 32; - /* This is PCIE Device Bus which start address is the low 32bit of= mem base*/ - Ptr->AddrRangeMin =3D (RootBridgeInstance->ResAllocNode[Index].Bas= e - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFF); + /* PCIE device Bar should be based on PciRegionBase */ + if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { + DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n")); + return EFI_UNSUPPORTED; + } + Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocNode[Index].Base= - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax =3D 0; Ptr->AddrTranslationOffset =3D \ (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; @@ -1467,9 +1474,9 @@ SetResource( Ptr->GenFlag =3D 0; Ptr->SpecificFlag =3D 0; Ptr->AddrSpaceGranularity =3D 64; - /* This is PCIE Device Bus which start address is the low 32bit of= mem base*/ - Ptr->AddrRangeMin =3D (RootBridgeInstance->ResAllocNode[Index].Bas= e - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFF= FFFF); + /* PCIE device Bar should be based on PciRegionBase */ + Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocNode[Index].Base= - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax =3D 0; Ptr->AddrTranslationOffset =3D \ (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; @@ -1486,9 +1493,9 @@ SetResource( Ptr->GenFlag =3D 0; Ptr->SpecificFlag =3D 6; Ptr->AddrSpaceGranularity =3D 64; - /* This is PCIE Device Bus which start address is the low 32bit of= mem base*/ - Ptr->AddrRangeMin =3D (RootBridgeInstance->ResAllocNode[Index].Bas= e - RootBridgeInstance->MemBase) + - (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFF= FFFF); + /* PCIE device Bar should be based on PciRegionBase */ + Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocNode[Index].Base= - RootBridgeInstance->MemBase + + RootBridgeInstance->PciRegionBase; Ptr->AddrRangeMax =3D 0; Ptr->AddrTranslationOffset =3D \ (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b= /Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 03edcf1..10d766a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2301,8 +2301,19 @@ RootBridgeIoConfiguration ( PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); for (Index =3D 0; Index < TypeMax; Index++) { if (PrivateData->ResAllocNode[Index].Status =3D=3D ResAllocated) { - Configuration.SpaceDesp[Index].AddrRangeMin =3D PrivateData->ResAllo= cNode[Index].Base; - Configuration.SpaceDesp[Index].AddrRangeMax =3D PrivateData->ResAllo= cNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1; + switch (Index) { + case TypeIo: + Configuration.SpaceDesp[Index].AddrRangeMin =3D PrivateData->IoBas= e; + break; + case TypeBus: + Configuration.SpaceDesp[Index].AddrRangeMin =3D PrivateData->ResAl= locNode[Index].Base; + break; + default: + /* PCIE Device bar address should be base on PciRegionBase */ + Configuration.SpaceDesp[Index].AddrRangeMin =3D PrivateData->ResAllo= cNode[Index].Base - PrivateData->MemBase + + PrivateData->PciRegion= Base; + } + Configuration.SpaceDesp[Index].AddrRangeMax =3D Configuration.SpaceD= esp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1; Configuration.SpaceDesp[Index].AddrLen =3D PrivateData->ResAllo= cNode[Index].Length; } } --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506655627054413.3728349389643; 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Thu, 28 Sep 2017 20:27:04 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:45 +0800 Message-Id: <1506655190-56231-7-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 06/11] Hisilicon/D05/Pcie: fix bug of size definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ming Huang Fix bug of PcieRegion size definition and IO size definition. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D05/D05.dsc | 64 ++++++++++---------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index aa61c0e..01defe0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -310,37 +310,37 @@ gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000 =20 gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000 - gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000 - gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000 - gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000 - gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000 - gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff + gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000 gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000 - gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff + gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000 gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000 - gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff + gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000 gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000 - gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff + gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67f0000 gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000 - gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 - gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 - gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff + gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 - gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000 - gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff + gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbf0000 =20 gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000 gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000 @@ -377,52 +377,52 @@ gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000 =20 gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0 - gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K + gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0x10000 #64K =20 gHisiTokenSpaceGuid.Pcdsoctype|0x1610 =20 --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506655630042347.31059477706435; Thu, 28 Sep 2017 20:27:10 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 99F1D21F2AF65; Thu, 28 Sep 2017 20:23:52 -0700 (PDT) Received: from mail-pf0-x22d.google.com (mail-pf0-x22d.google.com [IPv6:2607:f8b0:400e:c00::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DC1FE20945BD0 for ; Thu, 28 Sep 2017 20:23:51 -0700 (PDT) Received: by mail-pf0-x22d.google.com with SMTP id l188so58877pfc.6 for ; Thu, 28 Sep 2017 20:27:07 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.27.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:06 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::22d; helo=mail-pf0-x22d.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SONwR6b3hI7RT3XsR+jXry8c29U1r5xWCBJ7Konsg0M=; b=FRlPxKHv8WiDiBAVUJMEf+pDKh+CBMsC/YGURfRl6eAA7ezqz+3kbroSfOkFHjb49j VggZ7AwfuJ38NN2Oddm1CNLPfk9rfq7+49tnqCMT0KC/nw33bquk6qt9i4iphIC/TVIY BZKiN7gVJ2dsZT8jveSbNrmhJ3Eok6uZ0F29o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SONwR6b3hI7RT3XsR+jXry8c29U1r5xWCBJ7Konsg0M=; b=pqeDG2TAK/yjgx4kQikvEklUpIQTOs+I/k5RP6QPDVOiQ82VKNUwDmzcxsBCMr+gfX gS1uc5YBpuSZyCpEw80Z4282oBXjCXwEXRHFTeWVesBv9xGNuDmyHxFqKSvU2aOMa8fc S1I1SbJBnATke19BTrDSpCKOlubR4Gsqp7f5pnsRR6kbTdX8x3pjxThGc5XDUP2Id3Gk AUP0Bhr7S6tfmFkmGU8NBxagNvMqEHfdHIknZsdJktAdls9CC/N8o3Zu8P6Gkh/yfQxK 8OZT8LEEP4AoKIoAjBrWnbm6bBd2KhB8dG8CoxH5XcDtkJp5qJG9KxLHPUvIMG6A+7Yt O4Qw== X-Gm-Message-State: AHPjjUgkDxwA+ZvVtzqy9Ygw0iz2ErM9ZHx79jPbvN/bLPlcPooDwHJI jxJwIXmlaTS1gFQC37DCcloL5QgZf5A= X-Google-Smtp-Source: AOwi7QDgjaGB2Zcs7LgMkavUFlvW76mwCJMEyt6CkhbFreU+LtbODPKDFofc6F7lFNzMhwM+4DrmIA== X-Received: by 10.98.18.199 with SMTP id 68mr6228368pfs.94.1506655626943; Thu, 28 Sep 2017 20:27:06 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:46 +0800 Message-Id: <1506655190-56231-8-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 07/11] D05/PCIe: Modify PcieRegionBase of secondary chip X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ming Huang On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are 0x20000000 and 0x30000000 based. These addresses overlap with the DDR memory range 0-1G. In this situation, on the inbound direction, our pcie will drop the DDR address access that are located in the pci range window and lead to a dataflow error. Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000 and decrease PciRegion Size accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D05/D05.dsc | 12 ++++++------ Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 ++++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index 01defe0..64101a7 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -329,12 +329,12 @@ gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbf0000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000 gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000 - gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xd0000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000 gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbf0000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000 - gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xc0000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x40000000 + gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000 gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xb0000000 gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000 @@ -352,9 +352,9 @@ gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000 gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000 gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000 - gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000 + gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65040000000 gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000 - gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000 + gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75040000000 gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000 gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000 gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000 diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silic= on/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl index 79267e5..55c7f50 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl @@ -646,10 +646,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x20000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x65000000000, // Translate - 0xd0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, @@ -766,10 +766,10 @@ Scope(_SB) Cacheable, ReadWrite, 0x0, // Granularity - 0x30000000, // Min Base Address + 0x40000000, // Min Base Address 0xefffffff, // Max Base Address 0x75000000000, // Translate - 0xc0000000 // Length + 0xb0000000 // Length ) QWordIO ( ResourceProducer, --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 28 Sep 2017 20:27:09 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::229; helo=mail-pf0-x229.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=axAqhG06bhdicOPruvqAk8NM/FW/iZgSUPSvmGntTrM=; b=Z/eK1ta0ktS3PNG4wd8mB4Ybks9LmoCTCOVfHj965o+/jhNjOxTfGigEAHKzNmM/bB KmaDT67le6CUYjRA1VdWql5eJS9x9TTMWMcKWuWhZ2dgogbdtejYMKGL44FemqTzzwm4 PZuYxlPYmqp+UVn//+BGFvH7WdPUxDuegJBV4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=axAqhG06bhdicOPruvqAk8NM/FW/iZgSUPSvmGntTrM=; b=gDTCYKPzL6LTRR6FJH6TlZs1Ks8vKq6ijQKblMRmAHcUXRjYClf9lu39LObPwJT/1B GIgiESdVid8bH03F6DnYjHI8ddZd1gMy+BYSg/ZWyQWRvhGREs/CVCg6B/Mh36TzjDO8 K7+SVSEhN5uWW11NvZuU2HXISzvVE7MUTxT/TX8PA9B3iF1aoWp1TQ5LrEaevOQnGc3v yfsOe/slRo7z5MN7uOHLkwNpLvKqGe+2EGIXh/rDEtHc2Sz7B18yt+2m9kGhlOmF/2k9 gK9Pa12bewqoL8vpsFLMb4lOAQ6FtEKz3/d3T8G6yv8yn1RGjddRxpldabwzteDAmjKg wV+A== X-Gm-Message-State: AHPjjUjxK+lCC2jv2R1d3E1EJbg1/lVCVHlTAy8sIA8IKlVnTbqvujhm eLUS309BYdkSeRqHKDxA8oufnA== X-Google-Smtp-Source: AOwi7QCsVZEuukZLYtnJLIME9Kz2A15Laot6mXLwFZ3FaYGDLQp0ssFQTTFytM/MMMtNqEON+sBMMA== X-Received: by 10.99.56.78 with SMTP id h14mr6039582pgn.192.1506655629864; Thu, 28 Sep 2017 20:27:09 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:47 +0800 Message-Id: <1506655190-56231-9-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 08/11] Hisilicon/D03: Disable the function of PerfTuning X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, Chenhui Sun , zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Chenhui Sun The PerTuning function is not stable, it will cause the LSI SAS 3008/3108 crash, disable this function first. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chenhui Sun Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Platform/Hisilicon/D03/D03.dsc | 1 - Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 1 - Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 50 -------= ------------- Silicon/Hisilicon/HisiPkg.dec | 1 - 4 files changed, 53 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc index fca6781..f2a120e 100644 --- a/Platform/Hisilicon/D03/D03.dsc +++ b/Platform/Hisilicon/D03/D03.dsc @@ -112,7 +112,6 @@ # It could be set FALSE to save size. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|TRUE =20 [PcdsFixedAtBuild.common] gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D03" diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf = b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf index ee9dbed..61b091f 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf @@ -55,7 +55,6 @@ =20 [FeaturePcd] gHisiTokenSpaceGuid.PcdIsItsSupported - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable =20 [depex] TRUE diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/= Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 8ab7fa3..f420c91 100644 --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -315,50 +315,6 @@ PcieEnableItssm ( =20 } =20 -STATIC EFI_STATUS PciPerfTuning(UINT32 soctype, UINT32 HostBridgeNum, UINT= 32 Port) -{ - UINT32 Value; - UINTN RegSegmentOffset; - - if (Port >=3D PCIE_MAX_ROOTBRIDGE) { - DEBUG((DEBUG_ERROR, "Invalid port number: %d\n", Port)); - return EFI_INVALID_PARAMETER; - } - - RegSegmentOffset =3D PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + P= CIE_SYS_REG_OFFSET; - - //Enable SMMU bypass for translation - RegRead(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); - //BIT13: controller master read SMMU bypass - //BIT12: controller master write SMMU bypass - //BIT10: SMMU bypass enable - Value |=3D (BIT13 | BIT12 | BIT10); - RegWrite(RegSegmentOffset + PCIE_SYS_CTRL13_REG, Value); - - //Switch strongly order (SO) to relaxed order (RO) for write transacti= on - RegRead(RegSegmentOffset + PCIE_CTRL_6_REG, Value); - //BIT13 | BIT12: Enable write merge and SMMU streaming ordered write a= cknowledge - Value |=3D (BIT13 | BIT12); - //BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17: Enable RO for= all types of write transaction - Value |=3D (BIT29 | BIT27 | BIT25 | BIT23 | BIT21 | BIT19 | BIT17); - RegWrite(RegSegmentOffset + PCIE_CTRL_6_REG, Value); - - //Force streamID for controller read operation - RegRead(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); - //Force using streamID in PCIE_SYS_CTRL54_REG - Value &=3D ~(BIT30); - //Set streamID to 0, bit[0:15] is for request ID and should be kept - Value &=3D ~(0xff << 16); - RegWrite(RegSegmentOffset + PCIE_SYS_CTRL54_REG, Value); - - //Enable read and write snoopy - RegRead(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); - Value |=3D (BIT30 | BIT28); - RegWrite(RegSegmentOffset + PCIE_SYS_CTRL19_REG, Value); - - return EFI_SUCCESS; -} - EFI_STATUS PcieDisableItssm(UINT32 soctype, UINT32 HostBridgeNum, UINT32 P= ort) { PCIE_CTRL_7_U pcie_ctrl7; @@ -1141,12 +1097,6 @@ PciePortInit ( DisableRcOptionRom (soctype, HostBridgeNum, PortIndex, PcieCfg->PortI= nfo.PortType); /* assert LTSSM enable */ (VOID)PcieEnableItssm (soctype, HostBridgeNum, PortIndex, PcieCfg); - if (FeaturePcdGet(PcdIsPciPerfTuningEnable)) { - //PCIe will still work even if performance tuning fails, - //and there is warning message inside the function to print - //detailed error if there is. - (VOID)PciPerfTuning(soctype, HostBridgeNum, PortIndex); - } =20 PcieConfigContextHi1610(soctype, HostBridgeNum, PortIndex); /* diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec index 2c02e14..81ba3be 100644 --- a/Silicon/Hisilicon/HisiPkg.dec +++ b/Silicon/Hisilicon/HisiPkg.dec @@ -274,7 +274,6 @@ =20 [PcdsFeatureFlag] gHisiTokenSpaceGuid.PcdIsItsSupported|FALSE|BOOLEAN|0x00000065 - gHisiTokenSpaceGuid.PcdIsPciPerfTuningEnable|FALSE|BOOLEAN|0x00000066 =20 =20 =20 --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506655636486631.837173041191; Thu, 28 Sep 2017 20:27:16 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1B49221F2AF6F; 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Thu, 28 Sep 2017 20:27:12 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:48 +0800 Message-Id: <1506655190-56231-10-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 09/11] D05/ACPI: Disable D05 SAS0 and SAS2 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ming Huang There is no interface from SAS0 or SAS2 controller on D05, so SAS0 and SAS2 can't be used. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Silic= on/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl index 93beb95..6455130 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl @@ -88,6 +88,11 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } + + Method (_STA, 0, NotSerialized) + { + Return (0x0) + } } =20 Device(SAS1) { @@ -239,6 +244,11 @@ Scope(_SB) Store(0x7ffff, CLK) Sleep(1) } + + Method (_STA, 0, NotSerialized) + { + Return (0x0) + } } =20 } --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150665563952347.90116704923662; Thu, 28 Sep 2017 20:27:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 551D121F2AF74; Thu, 28 Sep 2017 20:24:02 -0700 (PDT) Received: from mail-pg0-x234.google.com (mail-pg0-x234.google.com [IPv6:2607:f8b0:400e:c05::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 42E0020945B68 for ; Thu, 28 Sep 2017 20:24:00 -0700 (PDT) Received: by mail-pg0-x234.google.com with SMTP id j16so81519pga.1 for ; Thu, 28 Sep 2017 20:27:15 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.27.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:14 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::234; helo=mail-pg0-x234.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=osmWHjelq3fYM3lm8AbMvOO1rb3nAbS0MjB+HfsJ3b0=; b=NdIwH3iek/ahE7+886T3I97Xv8tnOWn0VcXoM9IqwXFijrNi0jrNjygQrRz9OCGOXD QNwrvk52z2NCkY7JtdRuSKLDoTVpJKLKtz6FOUn3iGaAHNSLHJV4nlrhg/rRmoS4Jylu PVq0ZuOJy+q5N8WZBANXGcBRvHJvt5TuYw5RM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=osmWHjelq3fYM3lm8AbMvOO1rb3nAbS0MjB+HfsJ3b0=; b=lN+rWUCm5vj9ZqoH53wUWpFHHaWPH3XRJZagJIMxjQjbIPcYuH7eVDGIV4Ly9blbn4 owRqWQHj1Fd64T8BgljmZJvJXW6mulBZW/o27kMKxFvxTG/Qlq9PKXeOt6hrl1HyJ1AQ ++rn2fcOf7VRnsjtGcTSPK1D0k6RI6/Tk4ekB/jPJWJZZaPzr2x8EtM62bhaMbGRG2Bk Eeu2yidsZo7r0P9hHWlNP3oZuNzyqnhWbuR2GGUxIplo0WXZSZSMt/cR4rw5evfnpEer L2TvSvH20ih0aGeIdUL5qQiyEr+HBiUvQ/sNp4qiXKmbSjzTly69im6J2AUJjwfMu3li jpNQ== X-Gm-Message-State: AHPjjUiClD6iri+8gTcEoRig45+2zvaCrst0OUEdiiiYVA2u2345UfRf WfqNPAxQQroN/Qg4mOJ4IUEqwg== X-Google-Smtp-Source: AOwi7QCeeXXr5vYeprRYeCuEj5WKdkpa3Ps9rp+bLb+xarH+qt7W8LonrVnKA0Y6teEYXWqUeHC6ZQ== X-Received: by 10.84.215.22 with SMTP id k22mr5527819pli.284.1506655635466; Thu, 28 Sep 2017 20:27:15 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:49 +0800 Message-Id: <1506655190-56231-11-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 10/11] D05/ACPI: Modify I2C device X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ming Huang 1. Disable I2C0 device avoiding access conflict in OS, for it is used by UEFI to access DS3231 RTC chip and provide time services; 2. Modify _HID of I2C2 for matching the string in OS driver; Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +-------------= ------ 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Silic= on/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl index eb906ef..3cc60d1 100644 --- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl +++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl @@ -18,26 +18,8 @@ =20 Scope(_SB) { - Device(I2C0) { - Name(_HID, "APMC0D0F") - Name(_CID, "APMC0D0F") - Name(_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000) - Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.= MBI6") { 705 } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () {"clock-frequency", 100000}, - Package () {"i2c-sda-falling-time-ns", 913}, - Package () {"i2c-scl-falling-time-ns", 303}, - Package () {"i2c-sda-hold-time-ns", 0x9c2}, - } - }) - } - Device(I2C2) { - Name(_HID, "APMC0D0F") + Name(_HID, "HISI02A1") Name(_CID, "APMC0D0F") Name(_CRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xd0100000, 0x10000) --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Tue May 7 17:24:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506655642864144.0266000396839; Thu, 28 Sep 2017 20:27:22 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9030B21F2AF7B; Thu, 28 Sep 2017 20:24:03 -0700 (PDT) Received: from mail-pg0-x234.google.com (mail-pg0-x234.google.com [IPv6:2607:f8b0:400e:c05::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 057EE20945B68 for ; Thu, 28 Sep 2017 20:24:03 -0700 (PDT) Received: by mail-pg0-x234.google.com with SMTP id 7so56159pgd.13 for ; Thu, 28 Sep 2017 20:27:18 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g16sm5094376pfd.6.2017.09.28.20.27.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 Sep 2017 20:27:17 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::234; helo=mail-pg0-x234.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/8+BkMy9JKfKxV6vpyiXMfkKWdMAmpdM/DYkQsbuOXU=; b=HFSOwsVb7XzZ7z+4xv1h+rrPQw1I6oGlMRXLbl0jULM2WGJrKwRPy/PZPn7IuJamWU pXpVuAn3UBl96mhWpbHg1htjE/A4zWMz3lgop/8s9LBDEb6RVgNzflLppvQW4VUa4UMR NkCgvFqtZtnjh3FFXXuAaqIl+UySwA7HnfAgE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/8+BkMy9JKfKxV6vpyiXMfkKWdMAmpdM/DYkQsbuOXU=; b=iDKM5LhkQwy83iuyYIYY1AO5hcPnXq5gB6xC39fsmNRVDIiLL+rdGXzGzf32Byt3YT 8cpGD06zt04np60GQiosMfQa4WfrmRxijUzdcTetLqOsl/oED1+7F2xDsQP9dDbf5FGK l6uhb5yd5ErlB6qz39ghFtv6oEqcleZMF7YtaE2HZE0NqquI9B6xmCYOjlpWCE38mJVo bSqMoiQbZbdXCzXsOMa6cNdXI3yXNvkXdO0Bvas22/Cku30gR2z32sdpeVrdj/bWNAib lWYaWKxlczfmQeZrljUTOxA0U0jNaRGuM/jsaf+0GyIaRTrrAFDCd0bck6PuAfjMg+/W Am7g== X-Gm-Message-State: AHPjjUiA7x1S48MrbTBloNQ2CVRhjme1tObXQPGiaWLwjY8EEkH4+1t8 +RZHsEEKoWcRo04XIwRhEJUmRA== X-Google-Smtp-Source: AOwi7QBEDNuuBNE/eVl1LOzPR0YKt5PdpSSEAMAHl4fVnKLHXHF9igdOskLqscjmLjacw8H4tLSwPQ== X-Received: by 10.159.234.68 with SMTP id c4mr2803727plr.3.1506655638263; Thu, 28 Sep 2017 20:27:18 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Fri, 29 Sep 2017 11:19:50 +0800 Message-Id: <1506655190-56231-12-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> Subject: [edk2] [PATCH edk2-platforms v5 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, ard.biesheuvel@linaro.org, zhangjinsong2@huawei.com, Heyi Guo , wanghuiqiang@huawei.com, guoheyi@huawei.com, waip23@126.com, mengfanrong@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Jason zhang 1. Because Hi161x chip doesn't support "ARI Forwarding Enable" function, BIOS will enumerate 32 same devices (Device Number 0~31) when a Non-ARI capable device attached in the RP. Hi161x chip will not fix it, need BIOS patch. 2. Just enlarge iatu for those root port with ARI capable device attached, Non-ARI capable device's RP, keep iatu limitation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason zhang Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 + Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++ Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 79 ++++++++= ++++++++++++ 3 files changed, 87 insertions(+) diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/S= ilicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index e3d3988..9fa3f84 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -839,6 +839,7 @@ NotifyPhase( =20 case EfiPciHostBridgeEndEnumeration: PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n"); + EnlargeAtuConfig0 (This); break; =20 case EfiPciHostBridgeBeginBusAllocation: diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/S= ilicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index cddda6b..c04361f 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -401,6 +401,9 @@ PreprocessController ( #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL =20 +#define INVALID_CAPABILITY_00 0x00 +#define INVALID_CAPABILITY_FF 0xFF +#define PCI_CAPABILITY_POINTER_MASK 0xFC =20 // // Driver Instance Data Prototypes @@ -518,4 +521,8 @@ RootBridgeConstructor ( IN UINT32 Seg ); =20 +VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ); #endif diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b= /Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 10d766a..b57bd51 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -14,6 +14,7 @@ **/ =20 #include "PciHostBridge.h" +#include #include #include #include @@ -2322,3 +2323,81 @@ RootBridgeIoConfiguration ( return EFI_SUCCESS; } =20 +BOOLEAN +PcieCheckAriFwdEn ( + UINTN PciBaseAddr + ) +{ + UINT8 PciPrimaryStatus; + UINT8 CapabilityOffset; + UINT8 CapId; + UINT8 TempData; + + PciPrimaryStatus =3D MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET= ); + + if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { + CapabilityOffset =3D MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OF= FSET); + CapabilityOffset &=3D PCI_CAPABILITY_POINTER_MASK; + + while ((CapabilityOffset !=3D INVALID_CAPABILITY_00) && (CapabilityOff= set !=3D INVALID_CAPABILITY_FF)) { + CapId =3D MmioRead8 (PciBaseAddr + CapabilityOffset); + if (CapId =3D=3D EFI_PCI_CAPABILITY_ID_PCIEXP) { + break; + } + CapabilityOffset =3D MmioRead8 (PciBaseAddr + CapabilityOffset + 1); + CapabilityOffset &=3D PCI_CAPABILITY_POINTER_MASK; + } + } else { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + if ((CapabilityOffset =3D=3D INVALID_CAPABILITY_FF) || (CapabilityOffset= =3D=3D INVALID_CAPABILITY_00)) { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + TempData =3D MmioRead16 (PciBaseAddr + CapabilityOffset + + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); + TempData &=3D EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; + + if (TempData =3D=3D EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWAR= DING) { + return TRUE; + } else { + return FALSE; + } +} + +VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ) +{ + UINTN RbPciBase; + UINT64 MemLimit; + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n"); + + HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List =3D HostBridgeInstance->Head.ForwardLink; + + while (List !=3D &HostBridgeInstance->Head) { + PCIE_DEBUG ("HostBridge has data.\n"); + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + + RbPciBase =3D RootBridgeInstance->RbPciBar; + + // Those ARI FWD Enable Root Bridge, need enlarge iatu window. + if (PcieCheckAriFwdEn (RbPciBase)) { + MemLimit =3D GetPcieCfgAddress (RootBridgeInstance->Ecam, + RootBridgeInstance->BusBase + 2, 0, 0,= 0) + - 1; + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT= 32) MemLimit); + } + List =3D List->ForwardLink; + } +} --=20 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel