From nobody Mon Apr 29 13:32:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506590122086222.74511322981186; Thu, 28 Sep 2017 02:15:22 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 05D5C21F2AF8C; Thu, 28 Sep 2017 02:12:05 -0700 (PDT) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D30A521F2AF85 for ; Thu, 28 Sep 2017 02:12:02 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP; 28 Sep 2017 02:15:12 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.57]) by orsmga005.jf.intel.com with ESMTP; 28 Sep 2017 02:15:11 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,449,1500966000"; d="scan'208";a="154305573" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 28 Sep 2017 17:15:06 +0800 Message-Id: <1506590107-7324-2-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1506590107-7324-1-git-send-email-eric.dong@intel.com> References: <1506590107-7324-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Combine INIT-SIPI-SIPI. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In S3 resume path, current implementation do 2 separate INIT-SIPI-SIPI, this is not necessary. This change combine these 2 INIT-SIPI-SIPI to 1 and add CpuPause between them. Cc: Jiewen Yao Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 51 ++++++++++++++++++++---------------= ---- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 9404501..ae4b516 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -39,6 +39,11 @@ typedef struct { // SPIN_LOCK *mMemoryMappedLock =3D NULL; =20 +// +// Signal that SMM BASE relocation is complete. +// +volatile BOOLEAN mInitApsAfterSmmBaseReloc; + /** Get starting address and size of the rendezvous entry for APs. Information for fixing a jump instruction in the code is also returned. @@ -342,17 +347,21 @@ SetProcessorRegister ( } } =20 + + /** - AP initialization before SMBASE relocation in the S3 boot path. + AP initialization before then after SMBASE relocation in the S3 boot pat= h. **/ VOID -EarlyMPRendezvousProcedure ( +MPRendezvousProcedure ( VOID ) { CPU_REGISTER_TABLE *RegisterTableList; UINT32 InitApicId; UINTN Index; + UINTN TopOfStack; + UINT8 Stack[128]; =20 LoadMtrrData (mAcpiCpuData.MtrrTable); =20 @@ -368,25 +377,18 @@ EarlyMPRendezvousProcedure ( } } =20 + // // Count down the number with lock mechanism. // InterlockedDecrement (&mNumberToFinish); -} =20 -/** - AP initialization after SMBASE relocation in the S3 boot path. -**/ -VOID -MPRendezvousProcedure ( - VOID - ) -{ - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - UINTN TopOfStack; - UINT8 Stack[128]; + // + // Wait for BSP to signal SMM Base relocation done. + // + while (!mInitApsAfterSmmBaseReloc) { + CpuPause (); + } =20 ProgramVirtualWireMode (); DisableLvtInterrupts (); @@ -500,7 +502,12 @@ EarlyInitializeCpu ( PrepareApStartupVector (mAcpiCpuData.StartupVector); =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; - mExchangeInfo->ApFunction =3D (VOID *) (UINTN) EarlyMPRendezvousProcedu= re; + mExchangeInfo->ApFunction =3D (VOID *) (UINTN) MPRendezvousProcedure; + + // + // Execute code for before SmmBaseReloc. Note: This flag is maintained a= cross S3 boots. + // + mInitApsAfterSmmBaseReloc =3D FALSE; =20 // // Send INIT IPI - SIPI to all APs @@ -538,17 +545,11 @@ InitializeCpu ( } =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; - // - // StackStart was updated when APs were waken up in EarlyInitializeCpu. - // Re-initialize StackAddress to original beginning address. - // - mExchangeInfo->StackStart =3D (VOID *) (UINTN) mAcpiCpuData.StackAddres= s; - mExchangeInfo->ApFunction =3D (VOID *) (UINTN) MPRendezvousProcedure; =20 // - // Send INIT IPI - SIPI to all APs + // Signal that SMM base relocation is complete and to continue initializ= ation. // - SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector); + mInitApsAfterSmmBaseReloc =3D TRUE; =20 while (mNumberToFinish > 0) { CpuPause (); --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 13:32:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506590124568241.5164013857352; Thu, 28 Sep 2017 02:15:24 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4078921F2AF8F; Thu, 28 Sep 2017 02:12:05 -0700 (PDT) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E0EE621F2AF86 for ; Thu, 28 Sep 2017 02:12:02 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP; 28 Sep 2017 02:15:13 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.57]) by orsmga005.jf.intel.com with ESMTP; 28 Sep 2017 02:15:12 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.31; helo=mga06.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,449,1500966000"; d="scan'208";a="154305578" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 28 Sep 2017 17:15:07 +0800 Message-Id: <1506590107-7324-3-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1506590107-7324-1-git-send-email-eric.dong@intel.com> References: <1506590107-7324-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Refine code to avoid duplicated code. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Refine code to avoid duplicate code to set processor register. Cc: Jiewen Yao Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 78 ++++++++++-------------------------= ---- 1 file changed, 20 insertions(+), 58 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index ae4b516..500a0e2 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -208,18 +208,28 @@ Returns: =20 This function programs registers for the calling processor. =20 - @param RegisterTable Pointer to register table of the running processor. + @param RegisterTableList Pointer to register table of the running p= rocessor. =20 **/ VOID SetProcessorRegister ( - IN CPU_REGISTER_TABLE *RegisterTable + IN CPU_REGISTER_TABLE *RegisterTableList ) { CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; UINTN Index; UINTN Value; SPIN_LOCK *MsrSpinLock; + UINT32 InitApicId; + CPU_REGISTER_TABLE *RegisterTable; + + InitApicId =3D GetInitialApicId (); + for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { + if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { + RegisterTable =3D &RegisterTableList[Index]; + break; + } + } =20 // // Traverse Register Table of this logical processor @@ -347,8 +357,6 @@ SetProcessorRegister ( } } =20 - - /** AP initialization before then after SMBASE relocation in the S3 boot pat= h. **/ @@ -357,26 +365,12 @@ MPRendezvousProcedure ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; UINTN TopOfStack; UINT8 Stack[128]; =20 LoadMtrrData (mAcpiCpuData.MtrrTable); =20 - // - // Find processor number for this CPU. - // - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } - + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable); =20 // // Count down the number with lock mechanism. @@ -393,14 +387,7 @@ MPRendezvousProcedure ( ProgramVirtualWireMode (); DisableLvtInterrupts (); =20 - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable); =20 // // Place AP into the safe code, count down the number with lock mechanis= m in the safe code. @@ -475,27 +462,13 @@ PrepareApStartupVector ( =20 **/ VOID -EarlyInitializeCpu ( +InitializeCpuBeforeRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - LoadMtrrData (mAcpiCpuData.MtrrTable); =20 - // - // Find processor number for this CPU. - // - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable); =20 ProgramVirtualWireMode (); =20 @@ -527,22 +500,11 @@ EarlyInitializeCpu ( =20 **/ VOID -InitializeCpu ( +InitializeCpuAfterRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable); =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; =20 @@ -660,7 +622,7 @@ SmmRestoreCpu ( // // First time microcode load and restore MTRRs // - EarlyInitializeCpu (); + InitializeCpuBeforeRebase (); } =20 // @@ -675,7 +637,7 @@ SmmRestoreCpu ( // // Restore MSRs for BSP and all APs // - InitializeCpu (); + InitializeCpuAfterRebase (); } =20 // --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel