From nobody Sun May 19 22:46:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506588555684596.7405904127254; Thu, 28 Sep 2017 01:49:15 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C746A21F2AF81; Thu, 28 Sep 2017 01:45:58 -0700 (PDT) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C277021F2AF7A for ; Thu, 28 Sep 2017 01:45:56 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP; 28 Sep 2017 01:49:10 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.57]) by orsmga005.jf.intel.com with ESMTP; 28 Sep 2017 01:49:09 -0700 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,449,1500966000"; d="scan'208";a="154297076" From: Eric Dong To: edk2-devel@lists.01.org Date: Thu, 28 Sep 2017 16:49:06 +0800 Message-Id: <1506588546-7636-1-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 Subject: [edk2] [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Combine INIT-SIPI-SIPI. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jiewen Yao MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In S3 resume path, current implementation do 2 separate INIT-SIPI-SIPI, this is not necessary. This change combine these 2 INIT-SIPI-SIPI to 1 and add CpuPause between them. Cc: Jiewen Yao Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 112 +++++++++++++++-------------------= ---- 1 file changed, 44 insertions(+), 68 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 9404501..6dc4886 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -39,6 +39,11 @@ typedef struct { // SPIN_LOCK *mMemoryMappedLock =3D NULL; =20 +// +// Signal that SMM BASE relocation is complete. +// +volatile BOOLEAN mInitApsAfterSmmBaseReloc; + /** Get starting address and size of the rendezvous entry for APs. Information for fixing a jump instruction in the code is also returned. @@ -343,62 +348,59 @@ SetProcessorRegister ( } =20 /** - AP initialization before SMBASE relocation in the S3 boot path. + Set registers for the current processor. + + @param RegisterTableList The input registers list. + **/ VOID -EarlyMPRendezvousProcedure ( - VOID +SetRegisters ( + IN CPU_REGISTER_TABLE *RegisterTableList ) { - CPU_REGISTER_TABLE *RegisterTableList; UINT32 InitApicId; UINTN Index; =20 - LoadMtrrData (mAcpiCpuData.MtrrTable); - - // - // Find processor number for this CPU. - // - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable; InitApicId =3D GetInitialApicId (); for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { SetProcessorRegister (&RegisterTableList[Index]); - break; + return; } } - - // - // Count down the number with lock mechanism. - // - InterlockedDecrement (&mNumberToFinish); } =20 /** - AP initialization after SMBASE relocation in the S3 boot path. + AP initialization before then after SMBASE relocation in the S3 boot pat= h. **/ VOID MPRendezvousProcedure ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; UINTN TopOfStack; UINT8 Stack[128]; =20 + LoadMtrrData (mAcpiCpuData.MtrrTable); + + SetRegisters ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegi= sterTable); + + // + // Count down the number with lock mechanism. + // + InterlockedDecrement (&mNumberToFinish); + + // + // Wait for BSP to signal SMM Base relocation done. + // + while (!mInitApsAfterSmmBaseReloc) { + CpuPause (); + } + ProgramVirtualWireMode (); DisableLvtInterrupts (); =20 - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetRegisters ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable); =20 // // Place AP into the safe code, count down the number with lock mechanis= m in the safe code. @@ -473,34 +475,25 @@ PrepareApStartupVector ( =20 **/ VOID -EarlyInitializeCpu ( +InitializeCpuBeforeRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - LoadMtrrData (mAcpiCpuData.MtrrTable); =20 - // - // Find processor number for this CPU. - // - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetRegisters ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegi= sterTable); =20 ProgramVirtualWireMode (); =20 PrepareApStartupVector (mAcpiCpuData.StartupVector); =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; - mExchangeInfo->ApFunction =3D (VOID *) (UINTN) EarlyMPRendezvousProcedu= re; + mExchangeInfo->ApFunction =3D (VOID *) (UINTN) MPRendezvousProcedure; + + // + // Execute code for before SmmBaseReloc. Note: This flag is maintained a= cross S3 boots. + // + mInitApsAfterSmmBaseReloc =3D FALSE; =20 // // Send INIT IPI - SIPI to all APs @@ -520,35 +513,18 @@ EarlyInitializeCpu ( =20 **/ VOID -InitializeCpu ( +InitializeCpuAfterRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetRegisters ((CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable); =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; - // - // StackStart was updated when APs were waken up in EarlyInitializeCpu. - // Re-initialize StackAddress to original beginning address. - // - mExchangeInfo->StackStart =3D (VOID *) (UINTN) mAcpiCpuData.StackAddres= s; - mExchangeInfo->ApFunction =3D (VOID *) (UINTN) MPRendezvousProcedure; =20 // - // Send INIT IPI - SIPI to all APs + // Signal that SMM base relocation is complete and to continue initializ= ation. // - SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector); + mInitApsAfterSmmBaseReloc =3D TRUE; =20 while (mNumberToFinish > 0) { CpuPause (); @@ -659,7 +635,7 @@ SmmRestoreCpu ( // // First time microcode load and restore MTRRs // - EarlyInitializeCpu (); + InitializeCpuBeforeRebase (); } =20 // @@ -674,7 +650,7 @@ SmmRestoreCpu ( // // Restore MSRs for BSP and all APs // - InitializeCpu (); + InitializeCpuAfterRebase (); } =20 // --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel