From nobody Fri May 3 02:28:23 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150605189618953.33502613640769; Thu, 21 Sep 2017 20:44:56 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 47C0121ECCB1C; Thu, 21 Sep 2017 20:41:47 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 165EF20945B6E for ; Thu, 21 Sep 2017 20:41:45 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2017 20:44:52 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.239.196.163]) by orsmga003.jf.intel.com with ESMTP; 21 Sep 2017 20:44:51 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,426,1500966000"; d="scan'208";a="1017219545" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 22 Sep 2017 11:44:43 +0800 Message-Id: <1506051885-21008-2-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1506051885-21008-1-git-send-email-jiewen.yao@intel.com> References: <1506051885-21008-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 1/3] IntelSiliconPkg/VTdDxe: Clean up DXE flush memory. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Make sure the context table are flush to memory. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao --- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 9 +++++++-- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 4 ++-- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/I= ntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c index ccecc95..cecb5d2 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c @@ -124,7 +124,6 @@ CreateContextEntry ( RootEntry->Bits.ContextTablePointerHi =3D (UINT32) RShiftU64 ((UINT= 64)(UINTN)Buffer, 32); RootEntry->Bits.Present =3D 1; Buffer =3D (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages); - FlushPageTableMemory (VtdIndex, (UINTN)RootEntry, sizeof(*RootEntry)= ); } =20 ContextEntryTable =3D (VTD_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(R= ootEntry->Bits.ContextTablePointerLo, RootEntry->Bits.ContextTablePointerHi= ) ; @@ -143,9 +142,10 @@ CreateContextEntry ( ContextEntry->Bits.AddressWidth =3D 0x2; break; } - FlushPageTableMemory (VtdIndex, (UINTN)ContextEntry, sizeof(*ContextEn= try)); } =20 + FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Roo= tEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); + return EFI_SUCCESS; } =20 @@ -196,6 +196,7 @@ CreateSecondLevelPagingEntryTable ( DEBUG ((DEBUG_ERROR,"Could not Alloc LVL4 PT. \n")); return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)SecondLevelPagingEntry, EFI_PAG= ES_TO_SIZE(1)); } =20 // @@ -219,6 +220,7 @@ CreateSecondLevelPagingEntryTable ( ASSERT(FALSE); return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)Lvl4PtEntry[Index4].Uint64, S= IZE_4KB); SetSecondLevelPagingEntryAttribute (&Lvl4PtEntry[Index4], EDKII_IOMM= U_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); } =20 @@ -239,6 +241,7 @@ CreateSecondLevelPagingEntryTable ( ASSERT(FALSE); return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)Lvl3PtEntry[Index3].Uint64,= SIZE_4KB); SetSecondLevelPagingEntryAttribute (&Lvl3PtEntry[Index3], EDKII_IO= MMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); } =20 @@ -542,6 +545,7 @@ GetSecondLevelPageTableEntry ( *PageAttribute =3D PageNone; return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)L4PageTable[Index4], SIZE_4KB); SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&= L4PageTable[Index4], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); FlushPageTableMemory (VtdIndex, (UINTN)&L4PageTable[Index4], sizeof(L4= PageTable[Index4])); } @@ -555,6 +559,7 @@ GetSecondLevelPageTableEntry ( *PageAttribute =3D PageNone; return NULL; } + FlushPageTableMemory (VtdIndex, (UINTN)L3PageTable[Index3], SIZE_4KB); SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&= L3PageTable[Index3], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); FlushPageTableMemory (VtdIndex, (UINTN)&L3PageTable[Index3], sizeof(L3= PageTable[Index3])); } diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c b= /IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c index 68b25a7..0b3006a 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c @@ -73,7 +73,6 @@ CreateExtContextEntry ( ExtRootEntry->Bits.UpperContextTablePointerLo =3D (UINT32) RShiftU6= 4 ((UINT64)(UINTN)Buffer, 12) + 1; ExtRootEntry->Bits.UpperContextTablePointerHi =3D (UINT32) RShiftU6= 4 (RShiftU64 ((UINT64)(UINTN)Buffer, 12) + 1, 20); ExtRootEntry->Bits.UpperPresent =3D 1; - FlushPageTableMemory (VtdIndex, (UINTN)ExtRootEntry, sizeof(*ExtRoot= Entry)); Buffer =3D (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages); } =20 @@ -93,9 +92,10 @@ CreateExtContextEntry ( ExtContextEntry->Bits.AddressWidth =3D 0x2; break; } - FlushPageTableMemory (VtdIndex, (UINTN)ExtContextEntry, sizeof(*ExtCon= textEntry)); } =20 + FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Ext= RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); + return EFI_SUCCESS; } =20 --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 02:28:23 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506051898613906.6692756588765; Thu, 21 Sep 2017 20:44:58 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 83A3621ECCB23; Thu, 21 Sep 2017 20:41:47 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1B30521ECCB13 for ; Thu, 21 Sep 2017 20:41:46 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2017 20:44:53 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.239.196.163]) by orsmga003.jf.intel.com with ESMTP; 21 Sep 2017 20:44:52 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,426,1500966000"; d="scan'208";a="1017219550" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 22 Sep 2017 11:44:44 +0800 Message-Id: <1506051885-21008-3-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1506051885-21008-1-git-send-email-jiewen.yao@intel.com> References: <1506051885-21008-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 2/3] IntelSiliconPkg/dec: Clarify VTdPolicy. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Clarify the VTdPolicy is for both PEI and DXE. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao --- IntelSiliconPkg/IntelSiliconPkg.dec | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec b/IntelSiliconPkg/IntelSil= iconPkg.dec index 941380a..b88630d 100644 --- a/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/IntelSiliconPkg/IntelSiliconPkg.dec @@ -48,8 +48,8 @@ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid|{ 0xa9, 0x2d,= 0x75, 0x56, 0x6b, 0xde, 0x95, 0x48, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x= 6c, 0x22 }|VOID*|0x00000001 =20 ## The mask is used to control VTd behavior.

- # BIT0: Enable IOMMU during boot. - # BIT1: Enable IOMMU on exit boot service. + # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If= VTD_INFO_PPI is installed in PEI.) + # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in no= rmal boot. EndOfPEI in S3) # @Prompt The policy for VTd driver behavior. gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x000000= 02 =20 --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 02:28:23 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1506051901693996.2645869812936; Thu, 21 Sep 2017 20:45:01 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C439D21ECCB27; Thu, 21 Sep 2017 20:41:50 -0700 (PDT) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1878C21ECCB19 for ; Thu, 21 Sep 2017 20:41:47 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2017 20:44:54 -0700 Received: from jyao1-mobl.ccr.corp.intel.com ([10.239.196.163]) by orsmga003.jf.intel.com with ESMTP; 21 Sep 2017 20:44:53 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,426,1500966000"; d="scan'208";a="1017219556" From: Jiewen Yao To: edk2-devel@lists.01.org Date: Fri, 22 Sep 2017 11:44:45 +0800 Message-Id: <1506051885-21008-4-git-send-email-jiewen.yao@intel.com> X-Mailer: git-send-email 2.7.4.windows.1 In-Reply-To: <1506051885-21008-1-git-send-email-jiewen.yao@intel.com> References: <1506051885-21008-1-git-send-email-jiewen.yao@intel.com> Subject: [edk2] [PATCH 3/3] IntelSiliconPkg/VTdPmrPei: Add EndOfPei callback for S3 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Star Zeng MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In S3 resume, before system transfer to waking vector, the VTdPrm need turn off VTd protection based upon VTdPolicy. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao --- IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c | 59 +++++++= ++++++++++++- IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf | 1 + 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c b/= IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c index e768274..3fe6d65 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c @@ -24,16 +24,18 @@ #include #include #include +#include =20 #include "IntelVTdPmrPei.h" =20 #define TOTAL_DMA_BUFFER_SIZE SIZE_4MB +#define TOTAL_DMA_BUFFER_SIZE_S3 SIZE_1MB =20 EFI_ACPI_DMAR_HEADER *mAcpiDmarTable; VTD_INFO *mVTdInfo; UINT64 mEngineMask; UINTN mDmaBufferBase; -UINTN mDmaBufferSize =3D TOTAL_DMA_BUFFER_SIZE; +UINTN mDmaBufferSize; UINTN mDmaBufferCurrentTop; UINTN mDmaBufferCurrentBottom; =20 @@ -544,6 +546,7 @@ InitDmaProtection ( } ASSERT (DmaBufferSize =3D=3D ALIGN_VALUE(DmaBufferSize, MemoryAlignment)= ); *DmaBufferBase =3D (UINTN)AllocateAlignedPages (EFI_SIZE_TO_PAGES(DmaBuf= ferSize), MemoryAlignment); + ASSERT (*DmaBufferBase !=3D 0); if (*DmaBufferBase =3D=3D 0) { DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); return EFI_OUT_OF_RESOURCES; @@ -1105,6 +1108,41 @@ ParseDmarAcpiTableRmrr ( } =20 /** + This function handles S3 resume task at the end of PEI + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this f= unction. + + @retval EFI_STATUS Always return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +S3EndOfPeiNotify( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *Ppi + ) +{ + UINT64 EngineMask; + + DEBUG((DEBUG_INFO, "VTdPmr S3EndOfPeiNotify\n")); + + if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT1) =3D=3D 0) { + EngineMask =3D LShiftU64 (1, mVTdInfo->VTdEngineCount) - 1; + DisableDmaProtection (EngineMask); + } + return EFI_SUCCESS; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gEfiEndOfPeiSignalPpiGuid, + S3EndOfPeiNotify +}; + +/** Initializes the Intel VTd PMR PEIM. =20 @param FileHandle Handle of the file being invoked. @@ -1122,11 +1160,14 @@ IntelVTdPmrInitialize ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; =20 if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT0) =3D=3D 0) { return EFI_UNSUPPORTED; } =20 + PeiServicesGetBootMode (&BootMode); + Status =3D PeiServicesLocatePpi ( &gEdkiiVTdInfoPpiGuid, 0, @@ -1150,6 +1191,13 @@ IntelVTdPmrInitialize ( // ParseDmarAcpiTableRmrr (); =20 + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + mDmaBufferSize =3D TOTAL_DMA_BUFFER_SIZE_S3; + } else { + mDmaBufferSize =3D TOTAL_DMA_BUFFER_SIZE; + } + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", mDmaBufferSize)); + // // Find a pre-memory in resource hob as DMA buffer // Mark PEI memory to be DMA protected. @@ -1160,7 +1208,6 @@ IntelVTdPmrInitialize ( } =20 DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", mDmaBufferBase)); - DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", mDmaBufferSize)); =20 mDmaBufferCurrentTop =3D mDmaBufferBase + mDmaBufferSize; mDmaBufferCurrentBottom =3D mDmaBufferBase; @@ -1171,6 +1218,14 @@ IntelVTdPmrInitialize ( Status =3D PeiServicesInstallPpi (&mIoMmuPpiList); ASSERT_EFI_ERROR(Status); =20 + // + // Register EndOfPei Notify for S3 to run FSP NotifyPhase + // + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + Status =3D PeiServicesNotifyPpi (&mS3EndOfPeiNotifyDesc); + ASSERT_EFI_ERROR (Status); + } + return Status; } =20 diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf = b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf index 86cd7d1..e1aa980 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf @@ -46,6 +46,7 @@ [Ppis] gEdkiiIoMmuPpiGuid ## PRODUCES gEdkiiVTdInfoPpiGuid ## CONSUMES + gEfiEndOfPeiSignalPpiGuid ## CONSUMES =20 [Pcd] gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask ## CONSUMES --=20 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel