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charset="utf-8" From: Nir Erez This patch introduces following improvements to the PortingGuide * Replace split documentation with single file * Align format to Doxygen constraints Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Documentation/Build.txt | 58 ++++ Platform/Marvell/Documentation/PortingGuide.txt | 371 +++++++++++++++++= ++++ .../Marvell/Documentation/PortingGuide/ComPhy.txt | 45 --- .../Marvell/Documentation/PortingGuide/I2c.txt | 20 -- .../Marvell/Documentation/PortingGuide/Mdio.txt | 7 - .../Marvell/Documentation/PortingGuide/Mpp.txt | 48 --- .../Documentation/PortingGuide/PciEmulation.txt | 31 -- .../Marvell/Documentation/PortingGuide/Phy.txt | 45 --- .../Marvell/Documentation/PortingGuide/Pp2.txt | 35 -- .../Marvell/Documentation/PortingGuide/Reset.txt | 7 - .../Marvell/Documentation/PortingGuide/Spi.txt | 16 - .../Documentation/PortingGuide/SpiFlash.txt | 23 -- .../Marvell/Documentation/PortingGuide/Utmi.txt | 35 -- 13 files changed, 429 insertions(+), 312 deletions(-) create mode 100644 Platform/Marvell/Documentation/Build.txt create mode 100644 Platform/Marvell/Documentation/PortingGuide.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/ComPhy.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/I2c.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/Mdio.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/Mpp.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/PciEmulatio= n.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/Phy.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/Pp2.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/Reset.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/Spi.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/SpiFlash.txt delete mode 100644 Platform/Marvell/Documentation/PortingGuide/Utmi.txt diff --git a/Platform/Marvell/Documentation/Build.txt b/Platform/Marvell/Do= cumentation/Build.txt new file mode 100644 index 0000000..1162e2e --- /dev/null +++ b/Platform/Marvell/Documentation/Build.txt @@ -0,0 +1,58 @@ +UEFI Build Instructions +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +For toolchain versions limitations please refer to edk2 wiki page: +https://github.com/tianocore/tianocore.github.io/wiki/Using-EDK-II-with-Na= tive-GCC + +Fully supported are gcc4.5 - gcc4.9, so possible {toolchain_name} are: + - GCC45 + - GCC46 + - GCC47 + - GCC48 + - GCC49 + - GCC5 + +Supported {platform} are: + - Armada70x0 + +Supported {target} are + - DEBUG + - RELEASE + +Build procedure +--------------- +1. Prerequisites: + + Clone into edk2 repositories and apply Marvell patches (Please refer to + Release notes for instructions). + +2. Prepare environment: + + 2.1 Several packages will be needed to fully set up an edk2 build environ= ment: + + # sudo apt-get install build-essential uuid-dev + # sudo apt-get install lib32stdc++6 lib32z1 + + 2.2 Set up EDK2 environment + + # source edksetup.sh + + 2.3 Build base tools + + # make -C BaseTools + + 2.4 Set {toolchain_name}_AARCH64_PREFIX to path to your cross compiler + + # export {toolchain_name}_AARCH64_PREFIX=3D/path/to/toolchain + + Example: + -------- + # export GCC5_AARCH64_PREFIX=3D/opt/gcc-linaro-5.3.1-2016.05-x86_64_aar= ch64-linux-gnu/bin/aarch64-linux-gnu- + +3. Build EDK2 for selected {platform}: + + # build -a AARCH64 -t {toolchain_name} -b {target} -p OpenPlatformPkg/P= latforms/Marvell/Armada/{platform}.dsc + + Example for building edk2 for Armada70x0 platform with GCC5 for DEBUG: + + # build -a AARCH64 -t GCC5 -b DEBUG -p OpenPlatformPkg/Platforms/Marvel= l/Armada/Armada70x0.dsc diff --git a/Platform/Marvell/Documentation/PortingGuide.txt b/Platform/Mar= vell/Documentation/PortingGuide.txt new file mode 100644 index 0000000..8c3579e --- /dev/null +++ b/Platform/Marvell/Documentation/PortingGuide.txt @@ -0,0 +1,371 @@ +UEFI Porting Guide +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This document provides instructions for adding support for new Marvell Arm= ada +board. For the sake of simplicity new Marvell board will be called "new_bo= ard". + +1. Create configuration files for new target + 1.1 Create FDF file for new board + + - Copy and rename PathToYourOpp/Platforms/Marvell/Armada/Armada70x0.fdf = to + PathToYourOpp/Platforms/Marvell/Armada/new_board.fdf + - Change the first no-comment line: + [FD.Armada70x0_EFI] to [FD.{new_board}_EFI] + + 1.2 Create DSC file for new board + + - Add new_board.dsc file to PathToYourOpp/Platforms/Marvell/Armada direc= tory + - Insert following [Defines] section to new_board.dsc: + + [Defines] + PLATFORM_NAME =3D {new_board} + PLATFORM_GUID =3D {newly_generated_GUID} + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010019 + OUTPUT_DIRECTORY =3D {output_directory} + SUPPORTED_ARCHITECTURES =3D AARCH64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D {path_to_fdf_file} + + - Add "!include Armada.dsc.inc" entry to new_board.dsc + +2. Driver support + - According to content of files from PathToYourOpp/Documentation/Marvell/= PortingGuide + insert PCD entries into new_board.dsc for every needed interface (as li= sted below). + +3. Compilation + - Refer to PathToYourOpp/Documentation/Marvell/Build.txt. Remember to cha= nge + {platform} to new_board in order to point build system to newly created= DSC file. + +4. Output file + - Output files (and among others FD file, which may be used by ATF) are + generated under directory pointed by "OUTPUT_DIRECTORY" entry (see poin= t 1.2). + + +COMPHY configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to configure ComPhy library, following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdComPhyDevices + +This array indicates, which ones of the ComPhy chips defined in +MVHW_COMPHY_DESC template will be configured. + +Every ComPhy PCD has part where stands for chip ID (order is n= ot +important, but configuration will be set for first PcdComPhyChipCount chip= s). + +Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes +settings for this chip. Their format is unicode string, containing settings +for up to 10 lanes. Setting for each one is separated with semicolon. +These PCDs together describe outputs of PHY integrated in simple cihp. +Below is example for the first chip (Chip0). + + - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + (Unicode string indicating PHY types. Currently supported are: + + { L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", + L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", + L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", + L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", + L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", + L"RXAUI1", L"KR" } ) + + - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds + (Indicates PHY speeds in MHz. Currently supported are: + { 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 1031 } ) + + - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags + (Indicates lane polarity invert) + +Example +------- + + #ComPhy + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SAT= A1;USB3_HOST1;PCIE2" + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;500= 0;5000" + + +PHY Driver configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. +Currently only 1518 series PHYs are supported. Following PCDs are required: + + - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes + (list of values corresponding to PHY_CONNECTION enum) + - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg + (boolean - if true, driver waits for autonegotiation on startup) + - gMarvellTokenSpaceGuid.PcdPhyDeviceIds + (list of values corresponding to MV_PHY_DEVICE_ID enum) + +PHY_CONNECTION enum type is defined as follows: + + typedef enum { + 0 PHY_CONNECTION_RGMII, + 1 PHY_CONNECTION_RGMII_ID, + 2 PHY_CONNECTION_RGMII_TXID, + 3 PHY_CONNECTION_RGMII_RXID, + 4 PHY_CONNECTION_SGMII, + 5 PHY_CONNECTION_RTBI, + 6 PHY_CONNECTION_XAUI, + 7 PHY_CONNECTION_RXAUI + } PHY_CONNECTION; + +MV_PHY_DEVICE_ID: + + typedef enum { + 0 MV_PHY_DEVICE_1512, + } MV_PHY_DEVICE_ID; + +It should be extended when adding support for other PHY models. +Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be: + + gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 } + +with disabled autonegotiation: + + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE + +assuming, that PHY models are 1512: + + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } + + +MDIO configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +MDIO driver provides access to network PHYs' registers via EFI_MDIO_READ a= nd +EFI_MDIO_WRITE functions (EFI_MDIO_PROTOCOL). Following PCD is required: + + - gMarvellTokenSpaceGuid.PcdMdioBaseAddress + (base address of SMI management register) + + +I2C configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to enable driver on a new platform, following steps need to be ta= ken: + - add following line to .dsc file: + OpenPlatformPkg/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf + - add following line to .fdf file: + INF OpenPlatformPkg/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf + - add PCDs with relevant values to .dsc file: + - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } + (addresses of I2C slave devices on bus) + - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } + (buses to which accoring slaves are attached) + - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 + (number of SoC's I2C buses) + - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" + (base addresses of I2C controller buses) + - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 + (I2C host controller clock frequency) + - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 + (baud rate used in I2C transmission) + + +PciEmulation configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +Installation of various NonDiscoverable devices via PciEmulation driver is= performed +via set of PCDs. Following are available: + + - gMarvellTokenSpaceGuid.PcdPciEXhci + (Indicates, which Xhci devices are used) + + - gMarvellTokenSpaceGuid.PcdPciEAhci + (Indicates, which Ahci devices are used) + + - gMarvellTokenSpaceGuid.PcdPciESdhci + (Indicates, which Sdhci devices are used) + +All above PCD's correspond to hardware description in a dedicated structur= e: + +STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate + +in Platforms/Marvell/PciEmulation/PciEmulation.c file. It comprises device +count, base addresses, register region size and DMA-coherency type. + +Example +------- + +Assuming we want to enable second XHCI port and one SDHCI port on Armada +70x0 board, following needs to be declared: + + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } + + +SATA configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +There is one additional PCD for AHCI: + + - gMarvellTokenSpaceGuid.PcdSataBaseAddress + (Base address of SATA controller register space - used in SATA ComPhy init + sequence) + + +Pp2Dxe configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs +are required to operate: + + - gMarvellTokenSpaceGuid.PcdPp2Controllers + (Array with used controllers + Set to 0x1 for enabled, 0x0 for disabled) + + - gMarvellTokenSpaceGuid.PcdPp2Port2Controller + (Array specifying, to which controller the port belongs to) + + - gMarvellTokenSpaceGuid.PcdPhySmiAddresses + (Addresses of PHY devices) + + - gMarvellTokenSpaceGuid.PcdPp2PortIds + (Identificators of PP2 ports) + + - gMarvellTokenSpaceGuid.PcdPp2GopIndexes + (Indexes used in GOP operation) + + - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp + (Set to 0x1 for always-up interface, 0x0 otherwise) + + - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed + (Values corresponding to PHY_SPEED enum. + PHY_SPEED is defined as follows: + + typedef enum { + 0 NO_SPEED, + 1 SPEED_10, + 2 SPEED_100, + 3 SPEED_1000, + 4 SPEED_2500, + 5 SPEED_10000 + } PHY_SPEED; + + +UTMI PHY configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +In order to configure UTMI, following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdUtmiPhyCount + (Indicates how many UTMI PHYs are available on platform) + +Next four PCDs are in unicode string format containing settings for all de= vices +separated with semicolon. + + - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit + (Indicates base address of the UTMI unit) + + - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg + (Indicates address of USB Configuration register) + + - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg + (Indicates address of external UTMI configuration) + + - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort + (Indicates type of the connected USB port) + +Example +------- + + # UtmiPhy + gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 + gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" + gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420" + gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444" + gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" + + +SPI driver configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Following PCDs are available for configuration of spi driver: + + - gMarvellTokenSpaceGuid.PcdSpiClockFrequency + (Frequency (in Hz) of SPI clock) + + - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency + (Max SCLK line frequency (in Hz) (max transfer frequency) ) + + - gMarvellTokenSpaceGuid.PcdSpiDefaultMode + (default SCLK mode (see SPI_MODE enum in file OpenPlatformPkg/Drivers/Spi= /MvSpi.h) ) + + +SpiFlash configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Folowing PCDs for spi flash driver configuration must be set properly: + + - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles + (Size of SPI flash address in bytes (3 or 4) ) + + - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize + (Size of minimal erase block in bytes) + + - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize + (Size of SPI flash page) + + - gMarvellTokenSpaceGuid.PcdSpiFlashId + (Id of SPI flash) + + - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd + (Spi flash polling flag) + + +MPP configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Multi-Purpose Ports (MPP) are configurable through platform PCDs. +In order to set desired pin multiplexing, .dsc file needs to be modified. +(OpenPlatformPkg/Platforms/Marvell/Armada/{platform_name}.dsc - please ref= er to +Documentation/Build.txt for currently supported {platftorm_name} ) +Following PCDs are available: + + - gMarvellTokenSpaceGuid.PcdMppChipCount + (Indicates how many different chips are placed on board. So far up to 4 c= hips + are supported) + +Every MPP PCD has part where + stands for chip ID (order is not important, but configuration will = be + set for first PcdMppChipCount chips). + +Below is example for the first chip (Chip0). + + - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag + (Indicates that register order is reversed. (Needs to be used only for AP= 806-Z1) ) + + - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress + (This is base address for MPP configuration register) + + - gMarvellTokenSpaceGuid.PcdChip0MppPinCount + (Defines how many MPP pins are available) + + - gMarvellTokenSpaceGuid.PcdChip0MppSel0 + - gMarvellTokenSpaceGuid.PcdChip0MppSel1 + - gMarvellTokenSpaceGuid.PcdChip0MppSel2 + (This registers defines functions of 10 pins in ascending order) + +Examples +-------- + + # APN806-A0 MPP SET + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 + gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, = 0x1, 0x1, 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, = 0x0, 0x0, 0x0, 0x0 } + +Set pin 6 and 7 to 0xa function: + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, = 0xa, 0xa, 0x0, 0x0 } + + +MarvellResetSystemLib configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +This simple library allows to mask given bits in given reg at UEFI 'reset' +command call. These variables are configurable through PCDs: + + - gMarvellTokenSpaceGuid.PcdResetRegAddress + - gMarvellTokenSpaceGuid.PcdResetRegMask + + +Ramdisk configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +There is one PCD available for Ramdisk configuration + + - gMarvellTokenSpaceGuid.PcdRamDiskSize + (Defines size of Ramdisk) diff --git a/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt b/Platf= orm/Marvell/Documentation/PortingGuide/ComPhy.txt deleted file mode 100644 index a96015e..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/ComPhy.txt +++ /dev/null @@ -1,45 +0,0 @@ -COMPHY configuration ---------------------------- -In order to configure ComPhy library, following PCDs are available: - - gMarvellTokenSpaceGuid.PcdComPhyDevices - -This array indicates, which ones of the ComPhy chips defined in -MVHW_COMPHY_DESC template will be configured. - -Every ComPhy PCD has part where stands for chip ID (order is n= ot -important, but configuration will be set for first PcdComPhyChipCount chip= s). - -Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes -settings for this chip. Their format is unicode string, containing settings -for up to 10 lanes. Setting for each one is separated with semicolon. -These PCDs together describe outputs of PHY integrated in simple cihp. -Below is example for the first chip (Chip0). - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes - -Unicode string indicating PHY types. Currently supported are: - -{ L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", -L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", -L"SGMII1", L"SGMII2", L"SGMII3", -L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", -L"RXAUI0", L"RXAUI1", L"SFI" } - - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds - -Indicates PHY speeds in MHz. Currently supported are: - -{ 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 10310 } - - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags - -Indicates lane polarity invert. - -Example -------- - #ComPhy - gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1= ;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;= 5000" - diff --git a/Platform/Marvell/Documentation/PortingGuide/I2c.txt b/Platform= /Marvell/Documentation/PortingGuide/I2c.txt deleted file mode 100644 index 020ffb4..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/I2c.txt +++ /dev/null @@ -1,20 +0,0 @@ -1. Porting I2C driver to a new SOC ----------------------------------- -In order to enable driver on a new platform, following steps need to be ta= ken: - - add following line to .dsc file: - Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - - add following line to .fdf file: - INF Platform/Marvell/Drivers/I2c/MvI2cDxe/MvI2cDxe.inf - - add PCDs with relevant values to .dsc file: - gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57 } - (addresses of I2C slave devices on bus) - gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } - (buses to which accoring slaves are attached) - gMarvellTokenSpaceGuid.PcdI2cBusCount|2 - (number of SoC's I2C buses) - gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" - (base addresses of I2C controller buses) - gMarvellTokenSpaceGuid.PcdI2cClockFrequency|200000000 - (I2C host controller clock frequency) - gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 - (baud rate used in I2C transmission) diff --git a/Platform/Marvell/Documentation/PortingGuide/Mdio.txt b/Platfor= m/Marvell/Documentation/PortingGuide/Mdio.txt deleted file mode 100644 index c341d9e..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Mdio.txt +++ /dev/null @@ -1,7 +0,0 @@ -MDIO driver configuration -------------------------- -MDIO driver provides access to network PHYs' registers via MARVELL_MDIO_RE= AD and -MARVELL_MDIO_WRITE functions (MARVELL_MDIO_PROTOCOL). Following PCD is req= uired: - - gMarvellTokenSpaceGuid.PcdMdioBaseAddress - (base address of SMI management register) diff --git a/Platform/Marvell/Documentation/PortingGuide/Mpp.txt b/Platform= /Marvell/Documentation/PortingGuide/Mpp.txt deleted file mode 100644 index 68f0e9d..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Mpp.txt +++ /dev/null @@ -1,48 +0,0 @@ -MPP configuration ------------------ -Multi-Purpose Ports (MPP) are configurable through platform PCDs. -In order to set desired pin multiplexing, .dsc file needs to be modified. -(Platform/Marvell/Armada/{platform_name}.dsc - please refer to -Documentation/Build.txt for currently supported {platftorm_name} ) -Following PCDs are available: - - gMarvellTokenSpaceGuid.PcdMppChipCount - -Indicates how many different chips are placed on board. So far up to 4 chi= ps -are supported. - -Every MPP PCD has part where - stands for chip ID (order is not important, but configuration will = be - set for first PcdMppChipCount chips). - -Below is example for the first chip (Chip0). - - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag - -Indicates that register order is reversed. (Needs to be used only for AP80= 6-Z1) - - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress - -This is base address for MPP configuration register. - - gMarvellTokenSpaceGuid.PcdChip0MppPinCount - -Defines how many MPP pins are available. - - gMarvellTokenSpaceGuid.PcdChip0MppSel0 - gMarvellTokenSpaceGuid.PcdChip0MppSel1 - gMarvellTokenSpaceGuid.PcdChip0MppSel2 - -This registers defines functions of 10 pins in ascending order. - -Examples --------- -#APN806-A0 MPP SET - gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE - gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 - gMarvellTokenSpaceGuid.PcdChip0MppRegCount|3 - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x= 1, 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x= 0, 0x0, 0x0, 0x0 } - -Set pin 6 and 7 to 0xa function: - gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x= a, 0xa, 0x0, 0x0 } diff --git a/Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt b= /Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt deleted file mode 100644 index ec1afbc..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/PciEmulation.txt +++ /dev/null @@ -1,31 +0,0 @@ -PciEmulation configuration --------------------------- -Installation of various NonDiscoverable devices via PciEmulation driver is= performed -via set of PCDs. Following are available: - - gMarvellTokenSpaceGuid.PcdPciEXhci - -Indicates, which Xhci devices are used. - - gMarvellTokenSpaceGuid.PcdPciEAhci - -Indicates, which Ahci devices are used. - - gMarvellTokenSpaceGuid.PcdPciESdhci - -Indicates, which Sdhci devices are used. - -All above PCD's correspond to hardware description in a dedicated structur= e: - -STATIC PCI_E_PLATFORM_DESC A70x0PlatDescTemplate - -in Platforms/Marvell/PciEmulation/PciEmulation.c file. It comprises device -count, base addresses, register region size and DMA-coherency type. - -Examples --------- -Assuming we want to enable second XHCI port and one SDHCI port on Armada -70x0 board, following needs to be declared: - - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 0x1 } - gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 } diff --git a/Platform/Marvell/Documentation/PortingGuide/Phy.txt b/Platform= /Marvell/Documentation/PortingGuide/Phy.txt deleted file mode 100644 index 69dae02..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Phy.txt +++ /dev/null @@ -1,45 +0,0 @@ -PHY driver configuration ------------------------- -MvPhyDxe provides basic initialization and status routines for Marvell PHY= s. -Currently only 1512 series PHYs are supported. Following PCDs are required: - - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes - (list of values corresponding to PHY_CONNECTION enum) - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg - (boolean - if true, driver waits for autonegotiation on startup) - gMarvellTokenSpaceGuid.PcdPhyDeviceIds - (list of values corresponding to MV_PHY_DEVICE_ID enum) - -PHY_CONNECTION enum type is defined as follows: - - typedef enum { -0 PHY_CONNECTION_RGMII, -1 PHY_CONNECTION_RGMII_ID, -2 PHY_CONNECTION_RGMII_TXID, -3 PHY_CONNECTION_RGMII_RXID, -4 PHY_CONNECTION_SGMII, -5 PHY_CONNECTION_RTBI, -6 PHY_CONNECTION_XAUI, -7 PHY_CONNECTION_RXAUI - } PHY_CONNECTION; - -MV_PHY_DEVICE_ID: - - typedef enum { -0 MV_PHY_DEVICE_1512, - } MV_PHY_DEVICE_ID; - -It should be extended when adding support for other PHY -models. - -Thus in order to set RGMII for 1st PHY and SGMII for 2nd, PCD should be: - - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x0, 0x4 } - -with disabled autonegotiation: - - gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE - -assuming, that PHY models are 1512: - - gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform= /Marvell/Documentation/PortingGuide/Pp2.txt deleted file mode 100644 index f05ba27..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt +++ /dev/null @@ -1,35 +0,0 @@ -Pp2Dxe porting guide --------------------- -Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs -are required to operate: - -Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled: - gMarvellTokenSpaceGuid.PcdPp2Controllers - -Array specifying, to which controller the port belongs to: - gMarvellTokenSpaceGuid.PcdPp2Port2Controller - -Addresses of PHY devices: - gMarvellTokenSpaceGuid.PcdPhySmiAddresses - -Identificators of PP2 ports: - gMarvellTokenSpaceGuid.PcdPp2PortIds - -Indexes used in GOP operation: - gMarvellTokenSpaceGuid.PcdPp2GopIndexes - -Set to 0x1 for always-up interface, 0x0 otherwise: - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp - -Values corresponding to PHY_SPEED enum: - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed - -PHY_SPEED (in Mbps) is defined as follows: - typedef enum { - 0 NO_SPEED, - 1 SPEED_10, - 2 SPEED_100, - 3 SPEED_1000, - 4 SPEED_2500, - 5 SPEED_10000 - } PHY_SPEED; diff --git a/Platform/Marvell/Documentation/PortingGuide/Reset.txt b/Platfo= rm/Marvell/Documentation/PortingGuide/Reset.txt deleted file mode 100644 index 30dec86..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Reset.txt +++ /dev/null @@ -1,7 +0,0 @@ -MarvellResetSystemLib configuration ------------------------------------ -This simple library allows to mask given bits in given reg at UEFI 'reset' -command call. These variables are configurable through PCDs: - - gMarvellTokenSpaceGuid.PcdResetRegAddress - gMarvellTokenSpaceGuid.PcdResetRegMask diff --git a/Platform/Marvell/Documentation/PortingGuide/Spi.txt b/Platform= /Marvell/Documentation/PortingGuide/Spi.txt deleted file mode 100644 index be498a6..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Spi.txt +++ /dev/null @@ -1,16 +0,0 @@ -Spi driver configuration ------------------------- -Following PCDs are available for configuration of spi driver: - - gMarvellTokenSpaceGuid.PcdSpiClockFrequency - -Frequency (in Hz) of SPI clock - - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency - -Max SCLK line frequency (in Hz) (max transfer frequency) - - gMarvellTokenSpaceGuid.PcdSpiDefaultMode - -default SCLK mode (see SPI_MODE enum in file -Platform/Marvell/Drivers/Spi/MvSpi.h) diff --git a/Platform/Marvell/Documentation/PortingGuide/SpiFlash.txt b/Pla= tform/Marvell/Documentation/PortingGuide/SpiFlash.txt deleted file mode 100644 index 226db40..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/SpiFlash.txt +++ /dev/null @@ -1,23 +0,0 @@ -SpiFlash driver configuration ------------------------------ -Folowing PCDs for spi flash driver configuration must be set properly: - - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - -Size of SPI flash address in bytes (3 or 4) - - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - -Size of minimal erase block in bytes - - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - -Size of SPI flash page - - gMarvellTokenSpaceGuid.PcdSpiFlashId - -Id of SPI flash - - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - -Spi flash polling flag diff --git a/Platform/Marvell/Documentation/PortingGuide/Utmi.txt b/Platfor= m/Marvell/Documentation/PortingGuide/Utmi.txt deleted file mode 100644 index cff4843..0000000 --- a/Platform/Marvell/Documentation/PortingGuide/Utmi.txt +++ /dev/null @@ -1,35 +0,0 @@ -UTMI PHY configuration ----------------------- -In order to configure UTMI, following PCDs are available: - - gMarvellTokenSpaceGuid.PcdUtmiPhyCount - -Indicates how many UTMI PHYs are available on platform. - -Next four PCDs are in unicode string format containing settings for all de= vices -separated with semicolon. - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit - -Indicates base address of the UTMI unit. - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg - -Indicates address of USB Configuration register. - - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg - -Indicates address of external UTMI configuration. - - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort - -Indicates type of the connected USB port. - -Example -------- -#UtmiPhy - gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420" - gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444" - gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504271072115508.68318961433056; Fri, 1 Sep 2017 06:04:32 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B9F0A20958BCC; Fri, 1 Sep 2017 06:01:43 -0700 (PDT) Received: from mail-lf0-x22a.google.com (mail-lf0-x22a.google.com [IPv6:2a00:1450:4010:c07::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 85C0D21EB88FB for ; Fri, 1 Sep 2017 06:01:41 -0700 (PDT) Received: by mail-lf0-x22a.google.com with SMTP id g18so621348lfl.2 for ; Fri, 01 Sep 2017 06:04:26 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:23 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ux0tQxXJa20adEzd2t6BReGKCZ+zo58362UTv3xAmLI=; b=pRHqOxb1Nu+zywer6E+z0xfjLiEZMy272JcIfzV2GEbFm60kumYdrz4IZgBRuyq54+ 4yY+9iu1tYNoRLG72EbNmaYLr3mpa6F+g21082u/yRZnMflX/0Ra/ijjbDljeswr9M9f ESnZ+1ggLcUwfOXCczK1PYfQpJd2FMSRx03w619YSFB5P0LWDgXg/VSBu5ynjxX5fgEB C+StHFxGVYM6Ta+eMPkx9wNytdYPls5+mRw3JX1jzNt+vSChtSknd8GoFW6Cw2eNhRWv y+EOc9JiUObejsnw8WDBUw1p2kCevrzqRMDtuGrCvb5fjl29ZzkcYP1t2z9NXJ3jTNIJ KjZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ux0tQxXJa20adEzd2t6BReGKCZ+zo58362UTv3xAmLI=; b=pX1pvxfngq/BbZWI7NUcw3RhW2hWU7EV7xMCmGC6sJzXa1OU3Mk/CE3guP3595mfof HeuHo3aInZpI3/zCuNlft/xTx3od46A6oL6/unmYPhUM64LM1i4owYyG5wjSBPfg3k88 Eyyy3L+zv+QVERLXTB1+mdlxUNWdl8MJg736XJv3+vZc+BszSAuRJc2mYaTo5qbVimDK xZJyHaN+nSdRA5dnky17KLvjXbrMR8WzWxDRfrQ6EiA3a3GcDO6IaS7EzUP25GTUtIPN KUzKUJNHnlRMzk8f86V0yXtsup+buuOF957ppUiCu86VeKWl6JROXBGLdxvPJVtrbiNn d8kw== X-Gm-Message-State: AHPjjUjXU1EbKWhth755oTakiwcAqPgs7r8Fh7hhfC9VP4TjKKtCpURC /j6HGP79figAGyMkQHd3ww== X-Google-Smtp-Source: ADKCNb4q+xfSFVr4mvUaM9SkxZSMw46gvYcQNV3qrlkzsahtI8iiVp1PaUw/KeSMBSjTaPI0xvBQaA== X-Received: by 10.25.225.155 with SMTP id l27mr756987lfk.1.1504271064106; Fri, 01 Sep 2017 06:04:24 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:14 +0200 Message-Id: <1504271303-1782-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> MIME-Version: 1.0 Subject: [edk2] [platforms: PATCH 02/11] Drivers/Spi/MvSpiDxe: Log and return correct error X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com, =?UTF-8?q?Piotr=20Kr=C3=B3l?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 From: Piotr Kr=C3=B3l Make log information clear where it came from and return correct code to be interpreted by caller. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Piotr Kr=C3=B3l Signed-off-by: Marcin Wojtas --- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index aab20fc..0872f61 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -240,7 +240,8 @@ MvSpiTransfer ( } =20 if (Iterator >=3D SPI_TIMEOUT) { - DEBUG ((DEBUG_ERROR, "Timeout\n")); + DEBUG ((DEBUG_ERROR, "EfiSpiTransfer: Timeout\n")); + return EFI_TIMEOUT; } } =20 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 150427107573773.93886190777721; Fri, 1 Sep 2017 06:04:35 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0B0832095AE58; Fri, 1 Sep 2017 06:01:46 -0700 (PDT) Received: from mail-lf0-x22d.google.com (mail-lf0-x22d.google.com [IPv6:2a00:1450:4010:c07::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EEC3B21EB88FC for ; Fri, 1 Sep 2017 06:01:42 -0700 (PDT) Received: by mail-lf0-x22d.google.com with SMTP id d17so659224lfe.1 for ; Fri, 01 Sep 2017 06:04:27 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:24 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AVwrV0b8BHxDGYjWxDhFH0idBwzD0dNq/TITHmV9FFU=; b=rwF5USf4uwjkoepjjEKzim1Lpyb8NyETkUKsLqzKqr3w+TbWBpLvwMb00/d+t787BG Nx8/vsbVOKft0AlwmxLaXrrxNnpuEGUGReLHCt8jg2VY1fpeDbng45dx6tUXodRSgBpJ NcEMrFQktpFY5CmrHKkogoGt9GLUz4G1iBVDdtm+7OMni0mpnMIYyr3WOIsnaHQkswqL 1WS6+i52tNjRJmz/hebqKGlgwQ5cEvt77j6XMwuP3QFQuxyAD2xz7jma/6U3ZU820gsl JBTdAg9Y92yVmfYtUPD5W+fpjeaU9f79Rq0lYx62uY2OzPtaz4FSSEoCJMZ++wuixqBh Ljwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AVwrV0b8BHxDGYjWxDhFH0idBwzD0dNq/TITHmV9FFU=; b=QbLa+kSyzVbla70KGsx8nVv50qIsnw8sdV8S1Jr+sitnb3sjy3nAVAvN/6W+DAd+X4 xBQjUU1xS+B1gAJ6oi6kC2bnZuCGx4Ye9YGv8RXrp+pRUDw689QFC9Xw3/WfaQGN4XAy zlrJggaNljv1UpigNz778J5HwcApt6yyE+ejscdAhD64ZWUqh+wDcP8Fo2cgYD45wJ7l Hr5MSbt+cR+C6csC9Zhmn9OX4Nw0AIsipnilvMg88WNMaNgqej60yuwsVtB6QILi+tXI Zb6+dvYq222o8juOkVkVPkrRacumNw+5247yQpMZwRI5aP7kG0GJApw8zdSFWI5DAJqr Un4g== X-Gm-Message-State: AHPjjUidnG92eV1n+OT2LDdVlgE0BIU+fCIqhsxHAKHmmcGYrzUa9o6h CSV+i51sJv4DoU1k1hi6Kg== X-Google-Smtp-Source: ADKCNb62p0Zh35Xx+846efgJx5B7qYoPKA9QTW7JaDHvg9Gp3La0B3BRF9y0516w/wFjyaJVjzXtHg== X-Received: by 10.25.190.84 with SMTP id o81mr964760lff.228.1504271065554; Fri, 01 Sep 2017 06:04:25 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:15 +0200 Message-Id: <1504271303-1782-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 03/11] Drivers/Spi/MvSpiDxe: Fix write bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, Joe Zhou , ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Joe Zhou This patch prevents possible NULL pointer dereference during SPI transfers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Joe Zhou Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Drivers/Spi/MvSpiDxe.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c b/Platform/Marvell/Dri= vers/Spi/MvSpiDxe.c index 0872f61..6ddfcf6 100755 --- a/Platform/Marvell/Drivers/Spi/MvSpiDxe.c +++ b/Platform/Marvell/Drivers/Spi/MvSpiDxe.c @@ -226,9 +226,8 @@ MvSpiTransfer ( // Wait for memory ready for (Iterator =3D 0; Iterator < SPI_TIMEOUT; Iterator++) { if (MmioRead32 (SpiRegBase + SPI_INT_CAUSE_REG)) { - *DataInPtr =3D MmioRead32 (SpiRegBase + SPI_DATA_IN_REG); - if (DataInPtr !=3D NULL) { + *DataInPtr =3D MmioRead32 (SpiRegBase + SPI_DATA_IN_REG); DataInPtr++; } if (DataOutPtr !=3D NULL) { --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504271078911686.1023187328768; Fri, 1 Sep 2017 06:04:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 486A321D2E62B; Fri, 1 Sep 2017 06:01:46 -0700 (PDT) Received: from mail-lf0-x22d.google.com (mail-lf0-x22d.google.com [IPv6:2a00:1450:4010:c07::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5BA2D21EB88EC for ; Fri, 1 Sep 2017 06:01:44 -0700 (PDT) Received: by mail-lf0-x22d.google.com with SMTP id g18so621872lfl.2 for ; Fri, 01 Sep 2017 06:04:28 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:26 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dpT/r35YYtFV1X6i+UbdOUlFPyiv567nh8DDi1pM87U=; b=LHWXnmlaiO0XzTsGVXmNH3qcqlA9La/HCwQFHHfZ1865fZAwrQi3TNzv0c5KOcxNrk MRhE5hySgHzr7h8XhXv3+jtvCGJ7FWsZMR4AqfG6k36rnSoGDm31QmZUk0dSDbXSWmrM WfxdcBI5z95vTLNSi01zOJFFY7HteuTUrPSXinfN0kRi/Nyq5qHgbgAu16FZ2SJ38GCX KmFvEtFLZYVXEan9zgIimvLjqHU4EsJzXeRNJrRkvD9wVAjAUYWyXQbQJW8m38vy53FQ gZzaaDpE0UM4BEOPcCFhjPkTexQUsR/CCKuqlwTLaaIhMSNRN2BA8gRTNoIJy4R3YEUP bN2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dpT/r35YYtFV1X6i+UbdOUlFPyiv567nh8DDi1pM87U=; b=IWLRZtBcnEEKUHqkhO9RbBVQCZIlWcRMAAdKN8SVJgbLkdfFEB2vCtvvU4ZaW10YlD dcErHcBx4TjTid3ZCFAhx3xVjNh+vZAHKZrRa0/gBpzyEZmQsQiCO5GG9YAMyTdmj7fK wL+xqjq8rCL5yjXUY6OaAc9yyK7QDUNH5p83JZJWJDP1UbMpqHCVRZVoUDccYnq3pOOD 7f4t7JAO8Zn4Zb73YsZnXqx8cqI7pnO1Vemtj3ckjlZuR3c+hGMorbj2iETc07+j4ZE2 W+QNXNsJPWD0wr45W0E1j9wqAZ45EtVHvjkN07tqRTpyyl7tjpeAkLU9IJzVZ4nC6ML3 MbrA== X-Gm-Message-State: AHPjjUhXZvd+N4d39A4cS6xC7WSIs2GJZlckOtEer5g6UUqFU2JBEawv m3rv0at3bMLeocnIYFx8NA== X-Google-Smtp-Source: ADKCNb5CkFRRHcqOvdimelEtBDZYbj/w/LCHDnkIhFMFDY7c9iZvEMj4xpvdbvnlZ5drgZYDvZyqiw== X-Received: by 10.25.72.3 with SMTP id v3mr895854lfa.102.1504271066949; Fri, 01 Sep 2017 06:04:26 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:16 +0200 Message-Id: <1504271303-1782-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 04/11] Applications/SpiTool: Enable configurable CS and SCLK mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Until now transfer SCLK mode and CS were fixed, when using shell 'sf' command. This patch enables their configuration. Update porting guide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 6 +++++- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf | 2 ++ Platform/Marvell/Documentation/PortingGuide.txt | 9 +++++---- Platform/Marvell/Marvell.dec | 2 ++ 4 files changed, 14 insertions(+), 5 deletions(-) diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index 184e3d7..b6dc54f 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -218,6 +218,7 @@ EFI_STATUS Status; CONST CHAR16 *LengthStr =3D NULL, *FileStr =3D NULL; BOOLEAN AddrFlag =3D FALSE, LengthFlag =3D TRUE, FileFlag = =3D FALSE; UINT8 Flag =3D 0, CheckFlag =3D 0; + UINT8 Mode, Cs; =20 Status =3D gBS->LocateProtocol ( &gMarvellSpiFlashProtocolGuid, @@ -283,8 +284,11 @@ EFI_STATUS Status; } } =20 + Mode =3D PcdGet32 (PcdSpiFlashMode); + Cs =3D PcdGet32 (PcdSpiFlashCs); + // Setup new spi device - Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, 0, 0); + Slave =3D SpiMasterProtocol->SetupDevice (SpiMasterProtocol, Cs, Mode); if (Slave =3D=3D NULL) { Print(L"sf: Cannot allocate SPI device!\n"); return SHELL_ABORTED; diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf b/Platfo= rm/Marvell/Applications/SpiTool/SpiFlashCmd.inf index 41b7b7c..c1ab770 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf @@ -66,6 +66,8 @@ =20 [Pcd] gMarvellTokenSpaceGuid.PcdSpiFlashId + gMarvellTokenSpaceGuid.PcdSpiFlashCs + gMarvellTokenSpaceGuid.PcdSpiFlashMode =20 [Protocols] gMarvellSpiFlashProtocolGuid diff --git a/Platform/Marvell/Documentation/PortingGuide.txt b/Platform/Mar= vell/Documentation/PortingGuide.txt index 8c3579e..3b79bd2 100644 --- a/Platform/Marvell/Documentation/PortingGuide.txt +++ b/Platform/Marvell/Documentation/PortingGuide.txt @@ -284,10 +284,6 @@ Following PCDs are available for configuration of spi = driver: - gMarvellTokenSpaceGuid.PcdSpiMaxFrequency (Max SCLK line frequency (in Hz) (max transfer frequency) ) =20 - - gMarvellTokenSpaceGuid.PcdSpiDefaultMode - (default SCLK mode (see SPI_MODE enum in file OpenPlatformPkg/Drivers/Spi= /MvSpi.h) ) - - SpiFlash configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Folowing PCDs for spi flash driver configuration must be set properly: @@ -307,6 +303,11 @@ Folowing PCDs for spi flash driver configuration must = be set properly: - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd (Spi flash polling flag) =20 + - gMarvellTokenSpaceGuid.PcdSpiFlashMode + (Default SCLK mode (see SPI_MODE enum in file OpenPlatformPkg/Drivers/Spi= /MvSpi.h)) + + - gMarvellTokenSpaceGuid.PcdSpiFlashCs + (Chip select used for communication with the Flash) =20 MPP configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 4e2dd6d..869e376 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -128,6 +128,8 @@ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 + gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 =20 #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x0 }|VOID*|0x30000098 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504271082112606.041319969804; Fri, 1 Sep 2017 06:04:42 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 80A2A21E2BE37; Fri, 1 Sep 2017 06:01:47 -0700 (PDT) Received: from mail-lf0-x22f.google.com (mail-lf0-x22f.google.com [IPv6:2a00:1450:4010:c07::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AC28D21EB88DB for ; Fri, 1 Sep 2017 06:01:45 -0700 (PDT) Received: by mail-lf0-x22f.google.com with SMTP id g18so622110lfl.2 for ; Fri, 01 Sep 2017 06:04:30 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:27 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QpsV58Qqt8qmVrn1MbKKIq5NMWrrYc89ZM8y9JIseeo=; b=Gsze7PceJiKXLGrhGSgph/4D/3CeJetHIl85yjuNHyYKR8aTdsXDGLbL0wOxkq2M1x JkAc29zE6RJ2IhvPgq/7ZtsmB1KgDTK1RNiJSqTW9qDXVcb2mW4OEi82TpcNr9FqEqb5 tQLMeqc1fh8VklzKRDcKFA8Cnr1e5iMu6slPcIn3XVJFWRU9f6sM8vtsuA0w7Xm+GO2w mCnL+gUEtnOwUPytftGUoH9WTl2MWPEeSGzyubrxFdE67ti+W1JnIvIM+lKVBnjXIuo9 BJKL13QVZVqgwEtU2AT6ghyst1TjYpEg64I8c1ikGhTj29diIBWiWn1Pw/SrN+pW7/bU 1HWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QpsV58Qqt8qmVrn1MbKKIq5NMWrrYc89ZM8y9JIseeo=; b=RdoZm+sLuXSm2MMfQ8DtQzVVMTROw5EF83Fu+8IyxVuLAHJlcb80PBqQwJAksopQ++ 7UkGyMpl7b87BnY8MpdpnPLb1RcTp8pDCwJbHSmRG6vZKcIVXRvaiEvMHPYCvqRC9vnX LuNs0dN6bD8xt2gd6KNtvlwU15WhV/AW1TMJvqxoyh/ITtjpKOPvVcKza6OIhaH3fIOL n8SJ5KeTApgq2XnAtS+PxnL5LVYmnoqgxQKIv/iUSbsVLx9Bx7wcfkQQNCXrTtfK9ufG gP6aglsM8kusEvq1jIxxOFzCC7V/57r35E2atxj+/FYckUsV126eMM7dFXDtYwPP7eUY ml5g== X-Gm-Message-State: AHPjjUj0SbOvdnODNF+0LDXQsqg6DmtxpU4AsCo+yu4dQjcBcOB2hvjw 4WDQvEivikDCDLe5pSDKYg== X-Google-Smtp-Source: ADKCNb7LGTDFs0Nk8JTiVU16yWgSDXEC3wKXdHYHr09c2Zxntv1inK+rq5caAwod5I5uRrMR9MPXzA== X-Received: by 10.25.1.214 with SMTP id 205mr754745lfb.68.1504271068234; Fri, 01 Sep 2017 06:04:28 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:17 +0200 Message-Id: <1504271303-1782-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 05/11] Platform/Marvell/Armada70x0: set CS and SCLK Mode for SPI flash X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch makes use of recently added SPI configuration PCDs and sets CS with SCLK mode on Armada 7040 DB. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Armada/Armada70x0.dsc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index f519196..df2ebdb 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -98,6 +98,8 @@ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256 gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18 + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 =20 #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504271085987388.7837177354197; Fri, 1 Sep 2017 06:04:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id B955E21E2BE3E; Fri, 1 Sep 2017 06:01:48 -0700 (PDT) Received: from mail-lf0-x235.google.com (mail-lf0-x235.google.com [IPv6:2a00:1450:4010:c07::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0CADF21D1E2E7 for ; Fri, 1 Sep 2017 06:01:47 -0700 (PDT) Received: by mail-lf0-x235.google.com with SMTP id a126so691969lfa.0 for ; Fri, 01 Sep 2017 06:04:31 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oHhmTu8pdge4mIH+mWlIXF4ZczpC53TcHkV+Jsz5sOg=; b=yf1vdVv0J9PRPdWdT7ukuB1OSjJHEJ+aAAyKy2Iws5j6zgw9EslK3T+yGkQ+ytk0V+ opyWP7y8d1om9ntY0aMNr6/mnWdNlRtrBIAt83qj/3d/loXEoQ/x91grP9L7gq2VNPZT zjWdf2MD+ELTnqChT/p/1tB0Ygih9/ikJVjXqpZqPDXw2etSny6umv7bJrEasWEZz4uq pUStJIIs9ONsNxfXYXlUBe5xrvyKEvf1Lkm20Ue/AgmshReMbRGUWgy/P1G/Wkf6R7W6 MNcq+qDK6CXxvVNYR3/fQLXGdmyTwls7X5COOlEsEWAX8I3FfRYDhqBuT3jHhCocZeJc 4oMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oHhmTu8pdge4mIH+mWlIXF4ZczpC53TcHkV+Jsz5sOg=; b=qw3kyYDSY7l98hsUzrAr0Svf4O47ubG7L/UzGN8/xU21vCljsTndEZ03nxdnwocRWf 3ymvtcDRHdVnCjT52DJsz4ShPq8930lVq45KrvgXPBaFJJPra7igCMqj28cVm69L7f6W Nd1UNmcVVcYnhG6ffFZp6OWV86BQmyRKxlYMejmwo+5gULruwDWLXYphsvjeV4DU890s 1sbDai1ZQSlb3DQQzpMr0f3EBnSn9cXIHDUQ69sb3G8byBjjkAKmz1beBMDg/Z7DSkLB Xp8uofLopGxyGY+u6GOdbzGJnfUsMuDthyVEPKe8OZffl7e0Fu4nIRI1qRKB2fP3hTQq vm2Q== X-Gm-Message-State: AHPjjUiS5lkE6xFTBqXE9pO4Cc4AYqZ6oIbWBOG+RcHAm/tJ2Qat1dql xw8ep804Ir5R0jsbqu/D8w== X-Google-Smtp-Source: ADKCNb6XlR4bCNQehhxQaTHD2pY6pjfKmOPbFhdyvOODyOEneZC/lJ5oy2ZDsKq1VE0gp7rlIVOGjQ== X-Received: by 10.25.228.84 with SMTP id b81mr764016lfh.26.1504271069504; Fri, 01 Sep 2017 06:04:29 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:18 +0200 Message-Id: <1504271303-1782-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 06/11] Applications/SpiTool: Fix bug in error test X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Fix a misplaced closing parenthesis. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index b6dc54f..e6e1007 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -378,7 +378,7 @@ EFI_STATUS Status; FilePath =3D (CHAR16 *) FileStr; Status =3D ShellIsFile (FilePath); // When read file into flash, file doesn't have to exist - if (EFI_ERROR(Status && !(Flag & READ_FILE))) { + if (EFI_ERROR (Status) && !(Flag & READ_FILE)) { Print (L"sf: Wrong FilePath parameter!\n"); return SHELL_ABORTED; } --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504271089115832.6820597493042; Fri, 1 Sep 2017 06:04:49 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 01EDE21E62BA0; Fri, 1 Sep 2017 06:01:50 -0700 (PDT) Received: from mail-lf0-x22f.google.com (mail-lf0-x22f.google.com [IPv6:2a00:1450:4010:c07::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5133C21E11D25 for ; Fri, 1 Sep 2017 06:01:48 -0700 (PDT) Received: by mail-lf0-x22f.google.com with SMTP id d202so557139lfd.5 for ; Fri, 01 Sep 2017 06:04:32 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:30 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=h06660dwlWHHSH7YQcU/Z4bWewYIwED8BdU0volT4Uo=; b=Fp1ihyQZjA4KFjn9YuKrJXGHcm6IcEn6dFIyyNtfaqjIOEeeEAoN+R1m6uUfJL8CVv Vm+LqU7Dfawp0+vVG2WuuSex2fFPGtfecCjBeOUxuERbzb7RDBrZMJIgKZe2SxSAqbE/ xx36xE/AS22XQb9oZKVDaufsDfT3s6OQg4Pfh/WusHfn++Y3xYUuAOTA5OLr1kzXOPr8 jWlBFkQVI5SmrcfN9wP8r/wl7BYtibkhtCROII91TkBpCdSvo5LApyV23rwViQRxj7kC kw+w+vuxnUi4s7V2c2D/8s7lqLj+15OlY2J55v9HuBgMJRpgGKyvdSrom3vuSK4P1XAx NxOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=h06660dwlWHHSH7YQcU/Z4bWewYIwED8BdU0volT4Uo=; b=kxTKZPeiDhBr+36Lk1kHxwfAkYZjAw+uFybDtD9lSLQ5ek2pDDX5ehVKCYq3OzXRtg bHj/PnWV2Cvcu6A6L16yVHP5ZRE3C4ktvTXXn1tic2REi81u6B1q1Y/5kP5kkJ85VDi3 nkXdAOuuR/HJ0A3sl6fYyOrZl3eh33UuFR86kh3n5Mrp9YngypBnm7d/XVqbvA2z6OeL 1zxFLlo02W1bbJqQhgcA1ewustoOXWGY6bs825ty3XUCo29vmhuJyF3tHeNOcN7RV9XS RD6hF3t0QZXEq2oSWs+jvP0VK8pmvvWvxkmeXA4VoMyzrB67vJGvcxkaPnJNJAC3tAqO cO5A== X-Gm-Message-State: AHPjjUiU6VqhoUYsXEejJFTKdPA3KypuJjFMfS/eg24BRCdUoh4ZBVG3 16j3IYrRajlFIhoZjsRkUA== X-Google-Smtp-Source: ADKCNb6SNKTA5bq1qp/DUcDGLXnixMomq5JwTvGyADOC5r8bq5TQvARqx0Cl2frzzNduzzGDRASvGw== X-Received: by 10.25.163.74 with SMTP id m71mr930780lfe.63.1504271070916; Fri, 01 Sep 2017 06:04:30 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:19 +0200 Message-Id: <1504271303-1782-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 07/11] Applications/FirmwareUpdate: Fix 32-bit issues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Fix casting and related issues to make this code build for 32-bit ARM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas --- Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c b/Platf= orm/Marvell/Applications/FirmwareUpdate/FUpdate.c index edb6986..0951734 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c @@ -172,6 +172,7 @@ PrepareFirmwareImage ( EFI_STATUS Status; UINT64 OpenMode; UINTN *Buffer; + UINT64 Size; =20 // Parse string from commandline FileStr =3D ShellCommandLineGetRawValue (CheckPackage, 1); @@ -195,11 +196,13 @@ PrepareFirmwareImage ( return EFI_DEVICE_ERROR; } =20 - Status =3D FileHandleGetSize (*FileHandle, FileSize); + Status =3D FileHandleGetSize (*FileHandle, &Size); if (EFI_ERROR (Status)) { Print (L"%s: Cannot get Image file size\n", CMD_NAME_STRING); } =20 + *FileSize =3D (UINTN)Size; + // Read Image header into buffer Buffer =3D AllocateZeroPool (*FileSize); =20 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504271093011417.54424179990565; Fri, 1 Sep 2017 06:04:53 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3A46021E62BA4; Fri, 1 Sep 2017 06:01:50 -0700 (PDT) Received: from mail-lf0-x230.google.com (mail-lf0-x230.google.com [IPv6:2a00:1450:4010:c07::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8036821EB88FB for ; Fri, 1 Sep 2017 06:01:49 -0700 (PDT) Received: by mail-lf0-x230.google.com with SMTP id d202so557363lfd.5 for ; Fri, 01 Sep 2017 06:04:34 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:31 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZkV+ijcaTgpaKjaOvIVyEUCautJuJbAagknAWTA1AyY=; b=c7Hi5NpIDwicF+qoYxK8ZcBvj/JSG9CGmGD8GJCkVHAeYrn3B1xNMFi78iDmfGnRZi Ccy38p1JAr0cUYloU9KwOXr1j8xV42zMnUATHWPez7fZV3xzAf6Sqy21XPzxrOL15Xz6 dGom9TkPT330vN6J0fvhkVHMXce1iDoGAo6plY5twzh6ESSEtlKcvqeoZrAFqJqJs9tt MhqhvDrvjtaxsWmBsFF2lNP005gwjH+xpYS6R0ozE3UGJfIi+DMnPYQ38BRIFKTT1/oK jlNGzlLjQyNuBjJaZ0/J/X4s0tglt4MZdrBqA1I/djy1ejFCdpSz5ZfxW5JscvL45dxA +jMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZkV+ijcaTgpaKjaOvIVyEUCautJuJbAagknAWTA1AyY=; b=sP55RYrP1m8fKq4tMxl1QHUaRpBHnCBBSkn58dVXiJo0DfwJ38thKktORxKZ+/YSFF 4/RWoBU8Yv/qvkomKNiu8JklAl3P0wd+0OgTuRVN3YMw98i+Qg2Zj3m2fw2lxmDLMKiJ lVWGl3L2EmIi0Bw9aAGKSXXhHFn5oImTZXXHtBJPRu9J1CGpx6NSWosq3hxSaxkqx5Yj 8LtDQrX7hIAKZkjozKZodBcg2J9NRR7+FE0DGgxEsmsTM0DFL6kzzWvl0k1adu0mgwbY tXx7gbeDJMfo50m2VZ8axbM8/iv6WE6MabWMXnK6UU6hlI5pzfSOmB8JANZ8UpdllbmV Y9Wg== X-Gm-Message-State: AHPjjUhi5MGCpEKdKPlSdFUY+ycZ6sL2rTNSiVIRxKFTHWXfCKm3N2jO IdkrcpZCiSubSbDnevMpQA== X-Google-Smtp-Source: ADKCNb53vhCKuNh9yfgyp051sUuSYouOxhH/CZo0ATA8Yb8LSnqyW89t/VP/YnvxMRhzC8HxV6alAQ== X-Received: by 10.25.84.136 with SMTP id b8mr906588lfl.9.1504271072143; Fri, 01 Sep 2017 06:04:32 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:20 +0200 Message-Id: <1504271303-1782-9-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 08/11] Applications/SpiTool: Fix 32-bit issues X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Ard Biesheuvel Fix casting and related issues to make this code build for 32-bit ARM. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm --- Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index e6e1007..ee14270 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -418,7 +418,7 @@ EFI_STATUS Status; } } =20 - Buffer =3D (UINT8 *) Address; + Buffer =3D (UINT8 *)(UINTN)Address; if (FileFlag) { Buffer =3D FileBuffer; } --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504271096574792.0863400361479; Fri, 1 Sep 2017 06:04:56 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 723C221EB88FB; Fri, 1 Sep 2017 06:01:52 -0700 (PDT) Received: from mail-lf0-x22b.google.com (mail-lf0-x22b.google.com [IPv6:2a00:1450:4010:c07::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E1FE921EB88EC for ; Fri, 1 Sep 2017 06:01:50 -0700 (PDT) Received: by mail-lf0-x22b.google.com with SMTP id y128so570863lfd.4 for ; Fri, 01 Sep 2017 06:04:35 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:32 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QQdm0v8wJNqvsSeMGwBeLfBhYVUDF4+R9nmu2cYDt0Q=; b=rFlJLXTtgfVByfgk5YHLcDWr8bsIQTLIgB/NSBjc7P1/ON6d4XkLspXNvYRn8uJ5zO CJLw1eeJTMV758/OOcGQ7bzbeVi/vyafqzN0+MlTG2P5Oo0TUKYoXuMYwhwrgUmKP7Uy CnPSS6QnP3XXhvRz8QMn2sMGrrNVqHJ7M8v3sXj0xVpLWMm0MZuNbLr3QawRtIGlkHQB sPfC2tA5JGnxUoCOzJualKdvViGgtWKBHlzKmWahMDTrmEcmyM9Dxi2GW0KOIW7X8LNG 5GE7Z67M7vaso3cG4t0LbK1Qup/Dh24QOllBgyIedElH8XEZ723EIcsvWfLzs/uee0S0 j3JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QQdm0v8wJNqvsSeMGwBeLfBhYVUDF4+R9nmu2cYDt0Q=; b=crTOb8nxAQZEI4dWb2Sm+H/VN5MtwPTCsNbDEqWQkonMVOaLCKCmn+0bmzS+T/fFdR sF2iTJJJPasJsDL8/fWhhynoaYeEfsM3X+3NqmaghhWC9mXkkPXnRMwpo+Db/ckl8R5K 3qhWhlgMbh3cAp7CO22x3PNkQPNVTNPRWLajGv418NKEhftyFX//KHRCsam/gbWtPpRf +LauLLdB/WwHy9J2kIhP3wIZeEUmQtE/+McA0IAslosdRgNMOR1aAWUhKJsZL37+efVN WkN7SRWoKCoGfHkwv9l6X8gkWDBz6DICw0meZgl3ArRAOEGZK+Mzu9fHFAtGzCODqtRm RZFg== X-Gm-Message-State: AHPjjUiZlteRe83ZHDMlruwrauO7kKHUGDJIfOLZXHXeheDGkP7FvdKs MzO32JLUHx+ocpCm4zTNWw== X-Google-Smtp-Source: ADKCNb6HnHKMvHGCa+d4TTC4Lny0vtidG9w94V5Q/QPVqzZs2uXrlETV68VytzyjP09vHCOQgrBXfQ== X-Received: by 10.25.32.3 with SMTP id g3mr924100lfg.162.1504271073437; Fri, 01 Sep 2017 06:04:33 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:21 +0200 Message-Id: <1504271303-1782-10-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 09/11] Drivers/Spi/Devices/MvSpiFlash: Fix usage of erase size parameter X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Although, hitherto support allowed for using configurable EraseSize, the erase command was fixed to CMD_ERASE_64K. Also it was assumed that EraseSize equals SectorSize, which is not true for some flash devices. Fix both issues by adding new PCD (gMarvellTokenSpaceGuid.PcdSpiFlashPageSize) and using this parameter properly in MvSpiFlashUpdate routine instead of the EraseSize. Also erase command is adjusted to the settings. Update PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Documentation/PortingGuide.txt | 3 +++ Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 26 +++++++++++++++++-= ---- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 6 +++++ .../Marvell/Drivers/Spi/Devices/MvSpiFlash.inf | 1 + Platform/Marvell/Marvell.dec | 1 + 5 files changed, 31 insertions(+), 6 deletions(-) diff --git a/Platform/Marvell/Documentation/PortingGuide.txt b/Platform/Mar= vell/Documentation/PortingGuide.txt index 3b79bd2..f637fee 100644 --- a/Platform/Marvell/Documentation/PortingGuide.txt +++ b/Platform/Marvell/Documentation/PortingGuide.txt @@ -297,6 +297,9 @@ Folowing PCDs for spi flash driver configuration must b= e set properly: - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize (Size of SPI flash page) =20 + - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize + (Size of SPI flash sector, 65536 bytes by default) + - gMarvellTokenSpaceGuid.PcdSpiFlashId (Id of SPI flash) =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index 9a04493..f3fdba4 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -191,7 +191,21 @@ MvSpiFlashErase ( return EFI_DEVICE_ERROR; } =20 - Cmd[0] =3D CMD_ERASE_64K; + switch (EraseSize) { + case SPI_ERASE_SIZE_4K: + Cmd[0] =3D CMD_ERASE_4K; + break; + case SPI_ERASE_SIZE_32K: + Cmd[0] =3D CMD_ERASE_32K; + break; + case SPI_ERASE_SIZE_64K: + Cmd[0] =3D CMD_ERASE_64K; + break; + default: + DEBUG ((DEBUG_ERROR, "MvSpiFlash: Invalid EraseSize parameter\n")); + return EFI_INVALID_PARAMETER; + } + while (Length) { EraseAddr =3D Offset; =20 @@ -353,14 +367,14 @@ MvSpiFlashUpdate ( ) { EFI_STATUS Status; - UINT64 EraseSize, ToUpdate, Scale =3D 1; + UINT64 SectorSize, ToUpdate, Scale =3D 1; UINT8 *TmpBuf, *End; =20 - EraseSize =3D PcdGet64 (PcdSpiFlashEraseSize); + SectorSize =3D PcdGet64 (PcdSpiFlashSectorSize); =20 End =3D Buf + ByteCount; =20 - TmpBuf =3D (UINT8 *)AllocateZeroPool (EraseSize); + TmpBuf =3D (UINT8 *)AllocateZeroPool (SectorSize); if (TmpBuf =3D=3D NULL) { DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); return EFI_OUT_OF_RESOURCES; @@ -370,9 +384,9 @@ MvSpiFlashUpdate ( Scale =3D (End - Buf) / 100; =20 for (; Buf < End; Buf +=3D ToUpdate, Offset +=3D ToUpdate) { - ToUpdate =3D MIN((UINT64)(End - Buf), EraseSize); + ToUpdate =3D MIN((UINT64)(End - Buf), SectorSize); Print (L" \rUpdating, %d%%", 100 - (End - Buf) / Scale); - Status =3D MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf= , EraseSize); + Status =3D MvSpiFlashUpdateBlock (Slave, Offset, ToUpdate, Buf, TmpBuf= , SectorSize); =20 if (EFI_ERROR (Status)) { DEBUG((DEBUG_ERROR, "SpiFlash: Error while updating\n")); diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.h index 3889643..646598a 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h @@ -57,6 +57,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_READ_ARRAY_FAST 0x0b #define CMD_PAGE_PROGRAM 0x02 #define CMD_BANK_WRITE 0xc5 +#define CMD_ERASE_4K 0x20 +#define CMD_ERASE_32K 0x52 #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 @@ -66,6 +68,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #define SPI_TRANSFER_BEGIN 0x01 // Assert CS before transfer #define SPI_TRANSFER_END 0x02 // Deassert CS after transfe= rs =20 +#define SPI_ERASE_SIZE_4K 4096 +#define SPI_ERASE_SIZE_32K 32768 +#define SPI_ERASE_SIZE_64K 65536 + #define SPI_FLASH_16MB_BOUN 0x1000000 =20 typedef enum { diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf b/Platform= /Marvell/Drivers/Spi/Devices/MvSpiFlash.inf index d035d47..4519b02 100644 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf @@ -58,6 +58,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize gMarvellTokenSpaceGuid.PcdSpiFlashPageSize gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd + gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize =20 [Protocols] gMarvellSpiMasterProtocolGuid diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 869e376..fc00f1a 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -127,6 +127,7 @@ gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|0|UINT32|0x3000053 gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 + gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize|65536|UINT64|0x3000059 gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:34 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u05YnLAlA2l4kwQiBHAMoYhJsh/82B1+wBwVSyamlUE=; b=PAr/8dIlN117AKdIMOort3wDQVXTRypPdoIL+Zd9oh2nc5WsUD3SYC2J623YJwyigl VReae0MzzYkXCD6tsx3UBXeSafV/tiJSSrjmxWG3JMzIrvor4zLeVd7SWoYiRuARAKD+ Ot99htj0VKffzflQlEVDw+ZmFvDmD6/VIt1HpiaHnC+8BsoCPX54qkVO4vKPVEtj5hO0 75+COtL8jjEaMmbi4YbUoF0gq2D1zbKBpuQfITAa9lhmP1938BfPFXvRyIn2ywkZQEjk wqZdeP55Kf1VC3DBjbjbTfJoJuuXbwWf5moP91oKimGaBq8S32VMwhUcE89xPRTfIQia lEow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u05YnLAlA2l4kwQiBHAMoYhJsh/82B1+wBwVSyamlUE=; b=qWFKPRCTotHR4YlVEhR7fbhC1Q08uOQyjW04M/LeASo2DfpiPqFH9OTTKWiQEpQEqZ CB8Q8vjEnp1itKL1bz3QnpSHyP8Rdo7ia6GSG/lVjyB0V2IpUV2PmFRbgaJnLBVo0KC6 e8ZICdgWZW5rS6DBYII6tQySzZ7V9AowfUsiEfOeExOPZtDGNSnVtKjw10MTy7exliKh pi+WPr6k/10VR1XrH56rcXinrny/3V9wDHZwzD7sV7tWAmXAk1drIhhEKOj1yFCGwAmN 4Qq2ujkuCDsscOAq/+jyZbu/KPWjDQskwejzYdVhz+DkhgZEa9ps7OskIFv/u8O/FtwQ T+pg== X-Gm-Message-State: AHPjjUiINY/+cuw01NaxYyvc+EJKRfkCbD4TnNoEC41iBsv1L5DeD77g r0fgMZ4o2x8btifjzmP17A== X-Google-Smtp-Source: ADKCNb4DEJpHwo2iJD30WARnt0dFgnKFYgjM2mUa7zoRMm/vBQUUYuuyR1FCquHLomnJ5k7ykBm1gw== X-Received: by 10.25.32.85 with SMTP id g82mr749126lfg.113.1504271074797; Fri, 01 Sep 2017 06:04:34 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:22 +0200 Message-Id: <1504271303-1782-11-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 10/11] Drivers/Spi/Devices/MvSpiFlash: Enable dynamic SPI Flash detection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Hitherto mechanism of fixing SPI flash model in the PCDs, occured to be very inefficient and problematic. Enable dynamic detection by reworking MvSpiFlashReadId() command, which now reads the Id and goes through newly added table with JEDEC compliant devices and their description. On the occasion fix the ReadId process by using master's ReadWrite routine instead of pure Transfer - no longer swapping and byte shifting is needed. Simplify code by using local array instead of dynamic allocation. Also reduced number of ReadId arguments allowed for cleaning Fupdate and Sf shell commands probe routines. Additionally, use SpiFlashInfo fields instead of PCDs, and configure needed settings in MvSpiFlashInit. Update PortingGuide documentation accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- .../Marvell/Applications/FirmwareUpdate/FUpdate.c | 23 +- .../Applications/FirmwareUpdate/FUpdate.inf | 3 - .../Marvell/Applications/SpiTool/SpiFlashCmd.c | 36 +-- .../Marvell/Applications/SpiTool/SpiFlashCmd.inf | 1 - Platform/Marvell/Armada/Armada70x0.dsc | 5 - Platform/Marvell/Documentation/PortingGuide.txt | 18 -- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 267 +++++++++++++++++= ---- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 2 + .../Marvell/Drivers/Spi/Devices/MvSpiFlash.inf | 7 - Platform/Marvell/Include/Protocol/Spi.h | 37 +++ Platform/Marvell/Include/Protocol/SpiFlash.h | 4 +- Platform/Marvell/Marvell.dec | 6 - 12 files changed, 271 insertions(+), 138 deletions(-) diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c b/Platf= orm/Marvell/Applications/FirmwareUpdate/FUpdate.c index 0951734..b0e94bc 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.c @@ -94,32 +94,17 @@ SpiFlashProbe ( ) { EFI_STATUS Status; - UINT32 IdBuffer, Id, RefId; - - Id =3D PcdGet32 (PcdSpiFlashId); - - IdBuffer =3D CMD_READ_ID & 0xff; =20 // Read SPI flash ID - SpiFlashProtocol->ReadId (Slave, sizeof (UINT32), (UINT8 *)&IdBuffer); - - // Swap and extract 3 bytes of the ID - RefId =3D SwapBytes32 (IdBuffer) >> 8; - - if (RefId =3D=3D 0) { - Print (L"%s: No SPI flash detected"); - return EFI_DEVICE_ERROR; - } else if (RefId !=3D Id) { - Print (L"%s: Unsupported SPI flash detected with ID=3D%2x\n", CMD_NAME= _STRING, RefId); - return EFI_DEVICE_ERROR; + Status =3D SpiFlashProtocol->ReadId (Slave); + if (EFI_ERROR (Status)) { + return SHELL_ABORTED; } =20 - Print (L"%s: Detected supported SPI flash with ID=3D%3x\n", CMD_NAME_STR= ING, RefId); - Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, Slave); if (EFI_ERROR(Status)) { Print (L"%s: Cannot initialize flash device\n", CMD_NAME_STRING); - return EFI_DEVICE_ERROR; + return SHELL_ABORTED; } =20 return EFI_SUCCESS; diff --git a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf b/Pla= tform/Marvell/Applications/FirmwareUpdate/FUpdate.inf index 92c3333..43cac42 100644 --- a/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf +++ b/Platform/Marvell/Applications/FirmwareUpdate/FUpdate.inf @@ -64,9 +64,6 @@ UefiLib UefiRuntimeServicesTableLib =20 -[Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashId - [Protocols] gMarvellSpiFlashProtocolGuid gMarvellSpiMasterProtocolGuid diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c b/Platform= /Marvell/Applications/SpiTool/SpiFlashCmd.c index ee14270..b5db8b5 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.c @@ -166,37 +166,21 @@ FlashProbe ( ) { EFI_STATUS Status; - UINT8 IdBuffer[4]; - UINT32 Id, RefId; =20 - Id =3D PcdGet32 (PcdSpiFlashId); - - IdBuffer[0] =3D CMD_READ_ID; - - SpiFlashProtocol->ReadId ( - Slave, - 4, - IdBuffer - ); - - RefId =3D (IdBuffer[0] << 16) + (IdBuffer[1] << 8) + IdBuffer[2]; + Status =3D SpiFlashProtocol->ReadId (Slave); + if (EFI_ERROR (Status)) { + return SHELL_ABORTED; + } =20 - if (RefId =3D=3D Id) { - Print (L"sf: Detected supported SPI flash with ID=3D%3x\n", RefId); - Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, Slave); - if (EFI_ERROR(Status)) { - Print (L"sf: Cannot initialize flash device\n"); - return SHELL_ABORTED; - } - InitFlag =3D 0; - return EFI_SUCCESS; - } else if (RefId !=3D 0) { - Print (L"sf: Unsupported SPI flash detected with ID=3D%2x\n", RefId); + Status =3D SpiFlashProtocol->Init (SpiFlashProtocol, Slave); + if (EFI_ERROR (Status)) { + Print (L"sf: Cannot initialize flash device\n"); return SHELL_ABORTED; } =20 - Print (L"sf: No SPI flash detected"); - return SHELL_ABORTED; + InitFlag =3D 0; + + return SHELL_SUCCESS; } =20 SHELL_STATUS diff --git a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf b/Platfo= rm/Marvell/Applications/SpiTool/SpiFlashCmd.inf index c1ab770..343d5b5 100644 --- a/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf +++ b/Platform/Marvell/Applications/SpiTool/SpiFlashCmd.inf @@ -65,7 +65,6 @@ FileHandleLib =20 [Pcd] - gMarvellTokenSpaceGuid.PcdSpiFlashId gMarvellTokenSpaceGuid.PcdSpiFlashCs gMarvellTokenSpaceGuid.PcdSpiFlashMode =20 diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index df2ebdb..4633e32 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -93,11 +93,6 @@ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0x70 - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|3 - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536 - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256 - gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18 gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 =20 diff --git a/Platform/Marvell/Documentation/PortingGuide.txt b/Platform/Mar= vell/Documentation/PortingGuide.txt index f637fee..3ac35a0 100644 --- a/Platform/Marvell/Documentation/PortingGuide.txt +++ b/Platform/Marvell/Documentation/PortingGuide.txt @@ -288,24 +288,6 @@ SpiFlash configuration =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Folowing PCDs for spi flash driver configuration must be set properly: =20 - - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - (Size of SPI flash address in bytes (3 or 4) ) - - - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - (Size of minimal erase block in bytes) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - (Size of SPI flash page) - - - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize - (Size of SPI flash sector, 65536 bytes by default) - - - gMarvellTokenSpaceGuid.PcdSpiFlashId - (Id of SPI flash) - - - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - (Spi flash polling flag) - - gMarvellTokenSpaceGuid.PcdSpiFlashMode (Default SCLK mode (see SPI_MODE enum in file OpenPlatformPkg/Drivers/Spi= /MvSpi.h)) =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index f3fdba4..bfb8fa3 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -36,6 +36,136 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol; SPI_FLASH_INSTANCE *mSpiFlashInstance; =20 +#define INFO(JedecId, ExtId, SecSize, NSectors, FlashFlags) \ + .Id =3D { \ + ((JedecId) >> 16) & 0xff, \ + ((JedecId) >> 8) & 0xff, \ + (JedecId) & 0xff, \ + ((ExtId) >> 8) & 0xff, \ + (ExtId) & 0xff, \ + }, \ + .IdLen =3D (!(JedecId) ? 0 : (3 + ((ExtId) ? 2 : 0))), \ + .SectorSize =3D (SecSize), \ + .SectorCount =3D (NSectors), \ + .PageSize =3D 256, \ + .Flags =3D (FlashFlags), + +static SPI_FLASH_INFO SpiFlashIds[] =3D { + /* ATMEL */ + {L"at45db011d", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) }, + {L"at45db021d", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) }, + {L"at45db041d", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) }, + {L"at45db081d", INFO(0x1f2500, 0x0, 64 * 1024, 16, SECT_4K) }, + {L"at45db161d", INFO(0x1f2600, 0x0, 64 * 1024, 32, SECT_4K) }, + {L"at45db321d", INFO(0x1f2700, 0x0, 64 * 1024, 64, SECT_4K) }, + {L"at45db641d", INFO(0x1f2800, 0x0, 64 * 1024, 128, SECT_4K) }, + {L"at25df321a", INFO(0x1f4701, 0x0, 64 * 1024, 64, SECT_4K) }, + {L"at25df321", INFO(0x1f4700, 0x0, 64 * 1024, 64, SECT_4K) }, + {L"at26df081a", INFO(0x1f4501, 0x0, 64 * 1024, 16, SECT_4K) }, + /* EON */ + {L"en25q32b", INFO(0x1c3016, 0x0, 64 * 1024, 64, 0) }, + {L"en25q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {L"en25q128b", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) }, + {L"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) }, + /* GIGADEVICE */ + {L"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) }, + {L"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) }, + /* ISSI */ + {L"is25lp032", INFO(0x9d6016, 0x0, 64 * 1024, 64, 0) }, + {L"is25lp064", INFO(0x9d6017, 0x0, 64 * 1024, 128, 0) }, + {L"is25lp128", INFO(0x9d6018, 0x0, 64 * 1024, 256, 0) }, + /* MACRONIX */ + {L"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) }, + {L"mx25l4005", INFO(0xc22013, 0x0, 64 * 1024, 8, 0) }, + {L"mx25l8005", INFO(0xc22014, 0x0, 64 * 1024, 16, 0) }, + {L"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024, 32, 0) }, + {L"mx25l3205d", INFO(0xc22016, 0x0, 64 * 1024, 64, 0) }, + {L"mx25l6405d", INFO(0xc22017, 0x0, 64 * 1024, 128, 0) }, + {L"mx25l12805", INFO(0xc22018, 0x0, 64 * 1024, 256, RD_FULL | W= R_QPP) }, + {L"mx25l25635f", INFO(0xc22019, 0x0, 64 * 1024, 512, RD_FULL | W= R_QPP | ADDR_CYC_4) }, + {L"mx25l51235f", INFO(0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL | W= R_QPP) }, + {L"mx25l12855e", INFO(0xc22618, 0x0, 64 * 1024, 256, RD_FULL | W= R_QPP) }, + {L"mx66u51235f", INFO(0xc2253a, 0x0, 64 * 1024, 1024, RD_FULL | W= R_QPP) }, + {L"mx66l1g45g", INFO(0xc2201b, 0x0, 64 * 1024, 2048, RD_FULL | W= R_QPP) }, + /* SPANSION */ + {L"s25fl008a", INFO(0x010213, 0x0, 64 * 1024, 16, 0) }, + {L"s25fl016a", INFO(0x010214, 0x0, 64 * 1024, 32, 0) }, + {L"s25fl032a", INFO(0x010215, 0x0, 64 * 1024, 64, 0) }, + {L"s25fl064a", INFO(0x010216, 0x0, 64 * 1024, 128, 0) }, + {L"s25fl116k", INFO(0x014015, 0x0, 64 * 1024, 128, 0) }, + {L"s25fl164k", INFO(0x014017, 0x0140, 64 * 1024, 128, 0) }, + {L"s25fl128p_256k", INFO(0x012018, 0x0300, 256 * 1024, 64, RD_FULL= | WR_QPP) }, + {L"s25fl128p_64k", INFO(0x012018, 0x0301, 64 * 1024, 256, RD_FULL= | WR_QPP) }, + {L"s25fl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, RD_FULL= | WR_QPP) }, + {L"s25fl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, RD_FULL= | WR_QPP) }, + {L"s25fl128s_256k", INFO(0x012018, 0x4d00, 256 * 1024, 64, RD_FULL= | WR_QPP) }, + {L"s25fl128s_64k", INFO(0x012018, 0x4d01, 64 * 1024, 256, RD_FULL= | WR_QPP) }, + {L"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024, 128, RD_FULL= | WR_QPP) }, + {L"s25fl256s_64k", INFO(0x010219, 0x4d01, 64 * 1024, 512, RD_FULL= | WR_QPP) }, + {L"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024, 256, RD_FULL= | WR_QPP) }, + {L"s25fl512s_64k", INFO(0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL= | WR_QPP) }, + {L"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024, 256, RD_FULL= | WR_QPP) }, + /* STMICRO */ + {L"m25p10", INFO(0x202011, 0x0, 32 * 1024, 4, 0) }, + {L"m25p20", INFO(0x202012, 0x0, 64 * 1024, 4, 0) }, + {L"m25p40", INFO(0x202013, 0x0, 64 * 1024, 8, 0) }, + {L"m25p80", INFO(0x202014, 0x0, 64 * 1024, 16, 0) }, + {L"m25p16", INFO(0x202015, 0x0, 64 * 1024, 32, 0) }, + {L"m25pE16", INFO(0x208015, 0x1000, 64 * 1024, 32, 0) }, + {L"m25pX16", INFO(0x207115, 0x1000, 64 * 1024, 32, RD_QUAD | R= D_DUAL) }, + {L"m25p32", INFO(0x202016, 0x0, 64 * 1024, 64, 0) }, + {L"m25p64", INFO(0x202017, 0x0, 64 * 1024, 128, 0) }, + {L"m25p128", INFO(0x202018, 0x0, 256 * 1024, 64, 0) }, + {L"m25pX64", INFO(0x207117, 0x0, 64 * 1024, 128, SECT_4K) }, + {L"n25q016a", INFO(0x20bb15, 0x0, 64 * 1024, 32, SECT_4K) }, + {L"n25q32", INFO(0x20ba16, 0x0, 64 * 1024, 64, RD_FULL | = WR_QPP | SECT_4K) }, + {L"n25q32a", INFO(0x20bb16, 0x0, 64 * 1024, 64, RD_FULL | = WR_QPP | SECT_4K) }, + {L"n25q64", INFO(0x20ba17, 0x0, 64 * 1024, 128, RD_FULL | = WR_QPP | SECT_4K) }, + {L"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL | = WR_QPP | SECT_4K) }, + {L"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL | = WR_QPP) }, + {L"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL | = WR_QPP) }, + {L"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL | = WR_QPP | SECT_4K) }, + {L"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL | = WR_QPP | SECT_4K) }, + {L"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL | = WR_QPP | E_FSR | SECT_4K) }, + {L"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL | = WR_QPP | E_FSR | SECT_4K) }, + {L"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL | = WR_QPP | E_FSR | SECT_4K | ADDR_CYC_4) }, + {L"n25q1024a", INFO(0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL | = WR_QPP | E_FSR | SECT_4K) }, + {L"mt25qu02g", INFO(0x20bb22, 0x0, 64 * 1024, 4096, RD_FULL | = WR_QPP | E_FSR | SECT_4K) }, + {L"mt25ql02g", INFO(0x20ba22, 0x0, 64 * 1024, 4096, RD_FULL | = WR_QPP | E_FSR | SECT_4K) }, + /* SST */ + {L"sst25vf040b", INFO(0xbf258d, 0x0, 64 * 1024, 8, SECT_4K | = SST_WR) }, + {L"sst25vf080b", INFO(0xbf258e, 0x0, 64 * 1024, 16, SECT_4K | = SST_WR) }, + {L"sst25vf016b", INFO(0xbf2541, 0x0, 64 * 1024, 32, SECT_4K | = SST_WR) }, + {L"sst25vf032b", INFO(0xbf254a, 0x0, 64 * 1024, 64, SECT_4K | = SST_WR) }, + {L"sst25vf064c", INFO(0xbf254b, 0x0, 64 * 1024, 128, SECT_4K) }, + {L"sst25wf512", INFO(0xbf2501, 0x0, 64 * 1024, 1, SECT_4K | = SST_WR) }, + {L"sst25wf010", INFO(0xbf2502, 0x0, 64 * 1024, 2, SECT_4K | = SST_WR) }, + {L"sst25wf020", INFO(0xbf2503, 0x0, 64 * 1024, 4, SECT_4K | = SST_WR) }, + {L"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K | = SST_WR) }, + {L"sst25wf040b", INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) }, + {L"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024, 16, SECT_4K | = SST_WR) }, + /* WINBOND */ + {L"w25p80", INFO(0xef2014, 0x0, 64 * 1024, 16, 0) }, + {L"w25p16", INFO(0xef2015, 0x0, 64 * 1024, 32, 0) }, + {L"w25p32", INFO(0xef2016, 0x0, 64 * 1024, 64, 0) }, + {L"w25x40", INFO(0xef3013, 0x0, 64 * 1024, 8, SECT_4K) }, + {L"w25x16", INFO(0xef3015, 0x0, 64 * 1024, 32, SECT_4K) }, + {L"w25x32", INFO(0xef3016, 0x0, 64 * 1024, 64, SECT_4K) }, + {L"w25x64", INFO(0xef3017, 0x0, 64 * 1024, 128, SECT_4K) }, + {L"w25q80bl", INFO(0xef4014, 0x0, 64 * 1024, 16, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q16cl", INFO(0xef4015, 0x0, 64 * 1024, 32, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q32bv", INFO(0xef4016, 0x0, 64 * 1024, 64, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q64cv", INFO(0xef4017, 0x0, 64 * 1024, 128, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q128bv", INFO(0xef4018, 0x0, 64 * 1024, 256, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q256", INFO(0xef4019, 0x0, 64 * 1024, 512, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q80bw", INFO(0xef5014, 0x0, 64 * 1024, 16, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q16dw", INFO(0xef6015, 0x0, 64 * 1024, 32, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q32dw", INFO(0xef6016, 0x0, 64 * 1024, 64, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q64dw", INFO(0xef6017, 0x0, 64 * 1024, 128, RD_FULL | = WR_QPP | SECT_4K) }, + {L"w25q128fw", INFO(0xef6018, 0x0, 64 * 1024, 256, RD_FULL | = WR_QPP | SECT_4K) }, + {}, /* Empty entry to terminate the list */ +}; + STATIC VOID SpiFlashFormatAddress ( @@ -104,13 +234,13 @@ MvSpiFlashWriteCommon ( UINT8 CmdStatus =3D CMD_READ_STATUS; UINT8 State; UINT32 Counter =3D 0xFFFFF; - UINT8 poll_bit =3D STATUS_REG_POLL_WIP; - UINT8 check_status =3D 0x0; + UINT8 PollBit =3D STATUS_REG_POLL_WIP; + UINT8 CheckStatus =3D 0x0; =20 - CmdStatus =3D (UINT8)PcdGet32 (PcdSpiFlashPollCmd); - if (CmdStatus =3D=3D CMD_FLAG_STATUS) { - poll_bit =3D STATUS_REG_POLL_PEC; - check_status =3D poll_bit; + if (Slave->Info->Flags & E_FSR) { + CmdStatus =3D CMD_FLAG_STATUS; + PollBit =3D STATUS_REG_POLL_PEC; + CheckStatus =3D STATUS_REG_POLL_PEC; } =20 // Send command @@ -127,7 +257,7 @@ MvSpiFlashWriteCommon ( SpiMasterProtocol->Transfer (SpiMasterProtocol, Slave, 1, NULL, &State, 0); Counter--; - if ((State & poll_bit) =3D=3D check_status) + if ((State & PollBit) =3D=3D CheckStatus) break; } while (Counter > 0); if (Counter =3D=3D 0) { @@ -181,8 +311,19 @@ MvSpiFlashErase ( UINTN EraseSize; UINT8 Cmd[5]; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); - EraseSize =3D PcdGet64 (PcdSpiFlashEraseSize); + if (Slave->Info->Flags & ADDR_CYC_4) { + AddrSize =3D 4; + } else { + AddrSize =3D 3; + } + + if (Slave->Info->Flags & SECT_4K) { + Cmd[0] =3D CMD_ERASE_4K; + EraseSize =3D SPI_ERASE_SIZE_4K; + } else { + Cmd[0] =3D CMD_ERASE_64K; + EraseSize =3D Slave->Info->SectorSize; + } =20 // Check input parameters if (Offset % EraseSize || Length % EraseSize) { @@ -191,21 +332,6 @@ MvSpiFlashErase ( return EFI_DEVICE_ERROR; } =20 - switch (EraseSize) { - case SPI_ERASE_SIZE_4K: - Cmd[0] =3D CMD_ERASE_4K; - break; - case SPI_ERASE_SIZE_32K: - Cmd[0] =3D CMD_ERASE_32K; - break; - case SPI_ERASE_SIZE_64K: - Cmd[0] =3D CMD_ERASE_64K; - break; - default: - DEBUG ((DEBUG_ERROR, "MvSpiFlash: Invalid EraseSize parameter\n")); - return EFI_INVALID_PARAMETER; - } - while (Length) { EraseAddr =3D Offset; =20 @@ -239,7 +365,11 @@ MvSpiFlashRead ( UINT32 AddrSize, ReadAddr, ReadLength, RemainLength; UINTN BankSel =3D 0; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); + if (Slave->Info->Flags & ADDR_CYC_4) { + AddrSize =3D 4; + } else { + AddrSize =3D 3; + } =20 Cmd[0] =3D CMD_READ_ARRAY_FAST; =20 @@ -282,8 +412,13 @@ MvSpiFlashWrite ( UINT32 WriteAddr; UINT8 Cmd[5], AddrSize; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); - PageSize =3D PcdGet32 (PcdSpiFlashPageSize); + if (Slave->Info->Flags & ADDR_CYC_4) { + AddrSize =3D 4; + } else { + AddrSize =3D 3; + } + + PageSize =3D Slave->Info->PageSize; =20 Cmd[0] =3D CMD_PAGE_PROGRAM; =20 @@ -370,7 +505,7 @@ MvSpiFlashUpdate ( UINT64 SectorSize, ToUpdate, Scale =3D 1; UINT8 *TmpBuf, *End; =20 - SectorSize =3D PcdGet64 (PcdSpiFlashSectorSize); + SectorSize =3D Slave->Info->SectorSize; =20 End =3D Buf + ByteCount; =20 @@ -400,38 +535,66 @@ MvSpiFlashUpdate ( return EFI_SUCCESS; } =20 +STATIC +VOID +MvPrintFlashInfo ( + IN SPI_FLASH_INFO *Info + ) +{ + UINTN EraseSize; + + if (Info->Flags & SECT_4K) { + EraseSize =3D SPI_ERASE_SIZE_4K; + } else { + EraseSize =3D Info->SectorSize; + } + + DEBUG ((DEBUG_ERROR, + "Detected %s SPI flash with page size %d B, erase size %d KB, total %d= MB\n", + Info->Name, + Info->PageSize, + EraseSize / 1024, + (Info->SectorSize * Info->SectorCount) / 1024 / 1024)); +} + EFI_STATUS EFIAPI MvSpiFlashReadId ( - IN SPI_DEVICE *SpiDev, - IN UINT32 DataByteCount, - IN OUT UINT8 *Buffer + IN SPI_DEVICE *SpiDev ) { + SPI_FLASH_INFO *Info; EFI_STATUS Status; - UINT8 *DataOut; - - DataOut =3D (UINT8 *) AllocateZeroPool (DataByteCount); - if (DataOut =3D=3D NULL) { - DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); - return EFI_OUT_OF_RESOURCES; - } - Status =3D SpiMasterProtocol->Transfer (SpiMasterProtocol, SpiDev, - DataByteCount, Buffer, DataOut, SPI_TRANSFER_BEGIN | SPI_TRANSFER_END); - if (EFI_ERROR(Status)) { - FreePool (DataOut); - DEBUG((DEBUG_ERROR, "SpiFlash: Spi transfer error\n")); + UINT8 Id[SPI_FLASH_MAX_ID_LEN]; + UINT8 Cmd; + + Cmd =3D CMD_READ_ID; + Status =3D SpiMasterProtocol->ReadWrite (SpiMasterProtocol, + SpiDev, + &Cmd, + SPI_CMD_LEN, + NULL, + Id, + SPI_FLASH_MAX_ID_LEN); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ReadId: Spi transfer error\n")); return Status; } =20 - // Bytes 1,2 and 3 contain SPI flash ID - Buffer[0] =3D DataOut[1]; - Buffer[1] =3D DataOut[2]; - Buffer[2] =3D DataOut[3]; + Info =3D SpiFlashIds; + for (; Info->Name !=3D NULL; Info++) { + if (Info->IdLen !=3D 0) { + if (CompareMem (Info->Id, Id, Info->IdLen) =3D=3D 0) { + SpiDev->Info =3D Info; + MvPrintFlashInfo (Info); + return EFI_SUCCESS; + } + } + } =20 - FreePool (DataOut); + DEBUG ((DEBUG_ERROR, "ReadId: Unrecognized JEDEC Id bytes: 0x%02x%02x%02= x\n", Id[0], Id[1], Id[2])); =20 - return EFI_SUCCESS; + return EFI_NOT_FOUND; } =20 EFI_STATUS @@ -445,7 +608,11 @@ MvSpiFlashInit ( UINT8 Cmd, StatusRegister; UINT32 AddrSize; =20 - AddrSize =3D PcdGet32 (PcdSpiFlashAddressCycles); + if (Slave->Info->Flags & ADDR_CYC_4) { + AddrSize =3D 4; + } else { + AddrSize =3D 3; + } =20 if (AddrSize =3D=3D 4) { // Set 4 byte address mode diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.h index 646598a..b876966 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h @@ -62,6 +62,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_ERASE_64K 0xd8 #define CMD_4B_ADDR_ENABLE 0xb7 =20 +#define SPI_CMD_LEN 1 + #define STATUS_REG_POLL_WIP (1 << 0) #define STATUS_REG_POLL_PEC (1 << 7) =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf b/Platform= /Marvell/Drivers/Spi/Devices/MvSpiFlash.inf index 4519b02..f82c6e0 100644 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.inf @@ -53,13 +53,6 @@ DebugLib MemoryAllocationLib =20 -[FixedPcd] - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize - [Protocols] gMarvellSpiMasterProtocolGuid gMarvellSpiFlashProtocolGuid diff --git a/Platform/Marvell/Include/Protocol/Spi.h b/Platform/Marvell/Inc= lude/Protocol/Spi.h index ae78a31..73f0d80 100644 --- a/Platform/Marvell/Include/Protocol/Spi.h +++ b/Platform/Marvell/Include/Protocol/Spi.h @@ -38,6 +38,42 @@ extern EFI_GUID gMarvellSpiMasterProtocolGuid; =20 typedef struct _MARVELL_SPI_MASTER_PROTOCOL MARVELL_SPI_MASTER_PROTOCOL; =20 +#define SPI_FLASH_MAX_ID_LEN 6 + +typedef struct { + /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */ + UINT16 *Name; + + /* + * This array stores the ID bytes. + * The first three bytes are the JEDIC ID. + * JEDEC ID zero means "no ID" (mostly older chips). + */ + UINT8 Id[SPI_FLASH_MAX_ID_LEN]; + UINT8 IdLen; + + /* + * The size listed here is what works with SPINOR_OP_SE, which isn't + * necessarily called a "sector" by the vendor. + */ + UINT32 SectorSize; + UINT32 SectorCount; + + UINT16 PageSize; + + UINT16 Flags; +#define SECT_4K 1 << 0 /* CMD_ERASE_4K works uniformly */ +#define E_FSR 1 << 1 /* use flag status register for */ +#define SST_WR 1 << 2 /* use SST byte/word programming */ +#define WR_QPP 1 << 3 /* use Quad Page Program */ +#define RD_QUAD 1 << 4 /* use Quad Read */ +#define RD_DUAL 1 << 5 /* use Dual Read */ +#define RD_QUADIO 1 << 6 /* use Quad IO Read */ +#define RD_DUALIO 1 << 7 /* use Dual IO Read */ +#define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO) +#define ADDR_CYC_4 1 << 8 /* use 4 byte addressing format */ +} SPI_FLASH_INFO; + typedef enum { SPI_MODE0, // CPOL =3D 0 & CPHA =3D 0 SPI_MODE1, // CPOL =3D 0 & CPHA =3D 1 @@ -49,6 +85,7 @@ typedef struct { INTN Cs; INTN MaxFreq; SPI_MODE Mode; + SPI_FLASH_INFO *Info; } SPI_DEVICE; =20 typedef diff --git a/Platform/Marvell/Include/Protocol/SpiFlash.h b/Platform/Marvel= l/Include/Protocol/SpiFlash.h index 743bb87..e12f55b 100644 --- a/Platform/Marvell/Include/Protocol/SpiFlash.h +++ b/Platform/Marvell/Include/Protocol/SpiFlash.h @@ -61,9 +61,7 @@ EFI_STATUS typedef EFI_STATUS (EFIAPI *MV_SPI_FLASH_READ_ID) ( - IN SPI_DEVICE *SpiDev, - IN UINT32 DataByteCount, - IN OUT UINT8 *Buffer + IN SPI_DEVICE *SpiDev ); =20 typedef diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index fc00f1a..418d960 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -123,12 +123,6 @@ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|0|UINT32|0x30000052 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|0|UINT32|0x30000053 =20 - gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0|UINT32|0x3000052 - gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|0|UINT32|0x3000053 - gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|0|UINT64|0x3000054 - gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|0|UINT32|0x3000055 - gMarvellTokenSpaceGuid.PcdSpiFlashSectorSize|65536|UINT64|0x3000059 - gMarvellTokenSpaceGuid.PcdSpiFlashId|0|UINT32|0x3000056 gMarvellTokenSpaceGuid.PcdSpiFlashCs|0|UINT32|0x3000057 gMarvellTokenSpaceGuid.PcdSpiFlashMode|0|UINT32|0x3000058 =20 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Mon Apr 29 07:44:13 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id m129sm21754lfg.26.2017.09.01.06.04.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 Sep 2017 06:04:35 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u8gIICXSSajUhtvQ3RNTcCk/T6DmLmWgV9PVsRoau8A=; b=cF4AzHP1UWtcDYYE4WPEmWBgwTTiE5TPdAfA6stvK9xuy2XSHfJ/NN/IAhl0f1WVAU UWLgqzVTiqQ0lp3CLesUhhdn01Dqvvdh5aXubX0sr3FpoZcUnUrBidx+2EjoWo4Bo7xu ETmJoh2NPsvkegyMfHi7zZSHPphBzFHLLp5MHJI5CfbJ4quqCgb09yRPcuM8pgoV4lcG TveWCJgGLwOJEDDWO1ML3BG6MC8sBAcHEI/+32URaJZGy8y02qXmsS4SW+mCRk33ombl /Snv1lYY+J0l7947CADNXVHP9DnFUCInXGWzgVxpOpGQBB5cpGPzXmmoLC7jvHLXnbc1 fuWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u8gIICXSSajUhtvQ3RNTcCk/T6DmLmWgV9PVsRoau8A=; b=OIrbOXTie4bye6stqv0/8cZXnfIY4RpL3XxXhVp/J1VSxz95TSJqkzdOjld5rJQxbt 1DDkmDNv2J+ruks0OqDOy2nxAPl4CGSfZb2Ho85S6IieDafcyZWFS4rNDKzwBp30PJd0 RZ47AV82GeukvwpRq+FWKkj84OPSjCLhmaHfGK6VrYglcUQXHEMYM0e/B/eEXtEeKbG+ dg/kLknD1ZOcCO1zAYkcbGvH4QVFuzuPtYrdxJB0ZIx3cVAZptSLkFQRslIUgoIGRk9j TZvHJdAxJL0XjDrCreMML72q79+ECdsfq/C/PgQ2GUyOmrsLFsxZJSAOjXcoRi0Qvf2h zbrw== X-Gm-Message-State: AHPjjUiJ+rhr5PCJuNs9ZpSWMR7jOghCHd43nc1x83PdD1vfnc39ECUt pmSN4khtgvIHLZepsMXoFA== X-Google-Smtp-Source: ADKCNb7aZdA153bgQ8FjKEgspPEbdkGdNFKc5TuENaixTLUdY1cGLEZa9QdGd8XmENrQyj+pWb4Uzw== X-Received: by 10.25.215.169 with SMTP id q41mr921900lfi.120.1504271076454; Fri, 01 Sep 2017 06:04:36 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 15:08:23 +0200 Message-Id: <1504271303-1782-12-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504271303-1782-1-git-send-email-mw@semihalf.com> References: <1504271303-1782-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 11/11] Drivers/Spi/Devices/MvSpiFlash: Fix bank selection for Spansion X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Spansion SPI flash devices use different command for bank selection. Update it, basing on the first byte of flash ID. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas --- Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c | 5 +++++ Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h | 1 + 2 files changed, 6 insertions(+) diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.c index bfb8fa3..4c15513 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.c @@ -280,6 +280,11 @@ SpiFlashCmdBankaddrWrite ( { UINT8 Cmd =3D CMD_BANK_WRITE; =20 + /* Update bank selection command for Spansion */ + if (Slave->Info->Id[0] =3D=3D 0x01) { + Cmd =3D CMD_BANKADDR_BRWR; + } + MvSpiFlashWriteCommon (Slave, &Cmd, 1, &BankSel, 1); } =20 diff --git a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h b/Platform/M= arvell/Drivers/Spi/Devices/MvSpiFlash.h index b876966..d44c56f 100755 --- a/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h +++ b/Platform/Marvell/Drivers/Spi/Devices/MvSpiFlash.h @@ -57,6 +57,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #define CMD_READ_ARRAY_FAST 0x0b #define CMD_PAGE_PROGRAM 0x02 #define CMD_BANK_WRITE 0xc5 +#define CMD_BANKADDR_BRWR 0x17 #define CMD_ERASE_4K 0x20 #define CMD_ERASE_32K 0x52 #define CMD_ERASE_64K 0xd8 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel