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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5sm263439lfe.72.2017.08.31.19.33.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 19:33:28 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8rNvoJ3PU/gENZbdvkDLE1LYgN4I8SRmLl8Oyfs3sZA=; b=fQ1zXFavHfJKys3Ztlv/bSkQ+W/ZDAaVEN5aYIxVsC/EWjiMq9cXC7nata4AxUZVBK pnu2SwtzaWrUWdRFFw0qN2ePuan9qY1r2a122YkkEQRlFQnLjXJp+xQiW+Oozkcmi5Xs 9l6JQ9iMgp+N/J2ZmK2MCW4KKLqM+209vP3mEDKeq7fECZkh/8yxatDfDxFGclHI60Vd wZB8bK/Ez39x4cJhicPeIL8AVYhwfY4ZyOugNfGEGRJEPhI6HZXuQ1vWKFB9FqRVTW88 R/bXRILRMx26XWq16YFCT3oQ9SRJNoxxjuQgnD+uzd5gsFtXEpqKg83+MhkN/rxCBv3g eDmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8rNvoJ3PU/gENZbdvkDLE1LYgN4I8SRmLl8Oyfs3sZA=; b=ovx3P9jSBZ444wBT6307W8WC5H6bUa/L6veX1NIZYbLVG/VX6OsgF1TRl1VZsDgxnn +YKhvD6yE4EH7HCyU+qrWnyhsTeEj4M8tVXxLBH+OTJIebxcBMPTKzithXJoernAXw22 2yj5wd9MyqW+6VmMHmmQuhjBu+ah2KX1s6q8U4sGrg7NEeyupkbS08VW+mNO/AdsKWA9 RJ2B84SQW7qxvZ/Ul+tz1pLS0BDB/Oe8CZiXGr++8nNw2vPGwZJzvd51LIdad5f/g5Dl FvDRrPJhmifHNkPS3Y0FPr6daU3ySBKZ+Hyu5xyYZLqmukfulOp2GwICBUR1YP6QSDi5 ID6A== X-Gm-Message-State: AHPjjUgalprcT7NfI1McW6Qyuv2WQ5o7MdZbFofdqYuLOpZrqPX+pCAR 19AnQ44EMq4QzaN9/DTiZw== X-Google-Smtp-Source: ADKCNb6ctwKbz1N109xXDgeAcgo8Bb5v5tMqdFkolqqLBc/lpQoQlSHifJh4gnSOp68qzzS4Humblw== X-Received: by 10.25.16.96 with SMTP id f93mr146541lfi.143.1504233209830; Thu, 31 Aug 2017 19:33:29 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 04:37:25 +0200 Message-Id: <1504233451-6455-2-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504233451-6455-1-git-send-email-mw@semihalf.com> References: <1504233451-6455-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 1/7] Drivers/Net/Pp2Dxe: Move registers' description to macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Registers' offset are constant for each PP2 controller instance, so use macros with relative addresses for their description. This allowed to remove 5 PCD's and will ease enabling second controller on Armada8k. Update PortingGuide accordingly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 6 ------ Platform/Marvell/Documentation/PortingGuide/Pp2.txt | 21 -----------------= ---- Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h | 10 ++++++++++ Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 12 ++++++------ Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 6 ------ Platform/Marvell/Marvell.dec | 6 ------ 6 files changed, 16 insertions(+), 45 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index ccfd43c..d77e0b6 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -122,18 +122,12 @@ #NET gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333 - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0xf2130e00 - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0x1000 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 } gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 } gMarvellTokenSpaceGuid.PcdPp2NumPorts|3 gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0xf2441000 gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000 - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0xf212A200 - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0xf2130f00 - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0x1000 =20 #PciEmulation gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 } diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform= /Marvell/Documentation/PortingGuide/Pp2.txt index c1554a6..3c2f418 100644 --- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt +++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt @@ -34,26 +34,5 @@ PHY_SPEED (in Mbps) is defined as follows: Base address of shared register space of PP2: gMarvellTokenSpaceGuid.PcdPp2SharedAddress =20 -Spacing between consecutive GMAC register spaces: - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize - -Base address of GMAC: - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress - -Spacing between consecutive XLG register spaces: - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize - -Base address of XLG: - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress - -Base address of RFU1: - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress - -Base address of SMI: - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress - TCLK frequency in Hz: gMarvellTokenSpaceGuid.PcdPp2ClockFrequency - -GMAC and XLG addresses are computed as follows: - address =3D base_address + dev_size * gop_index diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Ma= rvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h index f283db2..868be53 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h @@ -39,6 +39,16 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAM= AGE. #define BIT(nr) (1 << (nr)) #endif =20 +/* PP2v2 registers offsets */ +#define MVPP22_SMI_OFFSET 0x12a200 +#define MVPP22_MPCS_OFFSET 0x130000 +#define MVPP22_XPCS_OFFSET 0x130400 +#define MVPP22_GMAC_OFFSET 0x130e00 +#define MVPP22_GMAC_REG_SIZE 0x1000 +#define MVPP22_XLG_OFFSET 0x130f00 +#define MVPP22_XLG_REG_SIZE 0x1000 +#define MVPP22_RFU1_OFFSET 0x441000 + /* RX Fifo Registers */ #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (por= t)) #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (por= t)) diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 1e2ccd0..d53f3b7 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -1141,10 +1141,6 @@ Pp2DxeParsePortPcd ( Pp2Context->Port.PhyInterface =3D PhyConnectionTypes[Pp2Context->Instanc= e]; Pp2Context->Port.AlwaysUp =3D AlwaysUp[Pp2Context->Instance]; Pp2Context->Port.Speed =3D Speed[Pp2Context->Instance]; - Pp2Context->Port.GmacBase =3D PcdGet64 (PcdPp2GmacBaseAddress) + - PcdGet32 (PcdPp2GmacDevSize) * Pp2Context->P= ort.GopIndex; - Pp2Context->Port.XlgBase =3D PcdGet64 (PcdPp2XlgBaseAddress) + - PcdGet32 (PcdPp2XlgDevSize) * Pp2Context->Por= t.GopIndex; } =20 EFI_STATUS @@ -1174,8 +1170,8 @@ Pp2DxeInitialise ( } =20 Mvpp2Shared->Base =3D PcdGet64 (PcdPp2SharedAddress); - Mvpp2Shared->Rfu1Base =3D PcdGet64 (PcdPp2Rfu1BaseAddress); - Mvpp2Shared->SmiBase =3D PcdGet64 (PcdPp2SmiBaseAddress); + Mvpp2Shared->Rfu1Base =3D Mvpp2Shared->Base + MVPP22_RFU1_OFFSET; + Mvpp2Shared->SmiBase =3D Mvpp2Shared->Base + MVPP22_SMI_OFFSET; Mvpp2Shared->Tclk =3D PcdGet32 (PcdPp2ClockFrequency); =20 /* Prepare buffers */ @@ -1259,6 +1255,10 @@ Pp2DxeInitialise ( Pp2Context->Port.TxpNum =3D 1; Pp2Context->Port.Priv =3D Mvpp2Shared; Pp2Context->Port.FirstRxq =3D 4 * Pp2Context->Instance; + Pp2Context->Port.GmacBase =3D Mvpp2Shared->Base + MVPP22_GMAC_OFFSET + + MVPP22_GMAC_REG_SIZE * Pp2Context->Port.Go= pIndex; + Pp2Context->Port.XlgBase =3D Mvpp2Shared->Base + MVPP22_XLG_OFFSET + + MVPP22_XLG_REG_SIZE * Pp2Context->Port.GopI= ndex; =20 /* Gather accumulated configuration data of all ports' MAC's */ NetCompConfig |=3D MvpPp2xGop110NetcCfgCreate(&Pp2Context->Port); diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index 9052fe2..ecd82b6 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -74,18 +74,12 @@ gMarvellTokenSpaceGuid.PcdPhyConnectionTypes gMarvellTokenSpaceGuid.PcdPhySmiAddresses gMarvellTokenSpaceGuid.PcdPp2ClockFrequency - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed gMarvellTokenSpaceGuid.PcdPp2NumPorts gMarvellTokenSpaceGuid.PcdPp2PortIds - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress gMarvellTokenSpaceGuid.PcdPp2SharedAddress - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize =20 [Depex] TRUE diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 5cbf0c3..9e2f706 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -170,18 +170,12 @@ #NET gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024 gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|0|UINT32|0x3000026 - gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0|UINT64|0x3000027 - gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0|UINT32|0x3000028 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029 gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C - gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0|UINT64|0x300002E gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0|UINT64|0x300002F - gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0|UINT64|0x3000030 - gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0|UINT64|0x3000031 - gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0|UINT32|0x3000032 =20 #PciEmulation gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 01:19:39 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5sm263439lfe.72.2017.08.31.19.33.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 19:33:30 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8aRCZJS5cwxmKR0nZBWP5w+Uz3mwe0uMxEYJl/4SONo=; b=nUGN856OyZerDYuDlGJqSNKinljWKUk7CeGz8KcAEgyYD7/IvKnQoUHILND/PMuJg6 UGUVQNwf1toU6Zajq3mzID0ykOJUbQZyLTwIIqka9VL9hBSlogWg4gT5HeouAsMLEOun 55aJAXC2H2ejXc1tI2cm5Wetl4Vpx3VwDkTslwLj2kRmlwqu1xjkYIXz83K1yQQyT3/M t9bkyaaPNpPSDjXMzNc/Kiqi64YAJg/1f3JsEjVTpeeibwCQ6vW5YzsgV1RauXmqLLsk 1+4aukV6tF5uv0v1qUVXSPsYfflEo++M4OsvWqoC05JEILgRgeRjlxe/ad40kNCyT4Fa gj9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8aRCZJS5cwxmKR0nZBWP5w+Uz3mwe0uMxEYJl/4SONo=; b=ej9GzT7kARjPLpO2ihLf3OspuhFIfUpEIUX7muEsOJc54N8tUXVRjSe5ou4tWGGLiz 5QhTZyVYYFpV34vZ80zQI7pQjHvQprrvM8aR9j6oBPT/nDopgdUjmrMVaXeDXTdW44sy AzieDMKZ8H2+Qv1yncNVVkEoTAp4XpTUSLF1SNPMEsefXHHiD2jA/ivPAZ2wha8vg2YC 1MdwbRwTyA9AqvMkPRUNOI0mMJ/Ttt71+jD/UHklsF8gqZVTS6LmazTWgdo6iBAFlCVg 4Jhd9/ByUFgca4ofEX3j/rUThywc1tOd2hLEA4nPQJqIoa0bP9u3lE3JfHkuIY2UkQ0O ErLg== X-Gm-Message-State: AHPjjUjVLYOPkf8GnWuQ4xQW8AKTYEwoitoRdnu7LOfjgXsGuSd9+hzO oGWEbipXswRa/D8pkophyA== X-Google-Smtp-Source: ADKCNb4YD5S8CLUmgcyo13eB393DePmVta5OzsVUw3Dj78iDleaI39f5w1FBzxr7F+mPGpTJrc1C5Q== X-Received: by 10.25.217.24 with SMTP id q24mr169841lfg.109.1504233211416; Thu, 31 Aug 2017 19:33:31 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 04:37:26 +0200 Message-Id: <1504233451-6455-3-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504233451-6455-1-git-send-email-mw@semihalf.com> References: <1504233451-6455-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 2/7] Drivers/Net/Pp2Dxe: Add SFI support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Since now SerDes can be properly configured to support 10G link, add this feature to the Armada 7k/8k network driver as well. This patch extends low-level configuration routines with SFI additions, which required two new fields in PP2DXE_PORT structure (XpcsBase and MpcsBase). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c | 183 +++++++++++++++++++= ++++ Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h | 31 ++++ Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h | 39 ++++- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 2 + Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 4 +- Platform/Marvell/Include/Protocol/MvPhy.h | 3 +- 6 files changed, 259 insertions(+), 3 deletions(-) diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c index cdd0979..5fb7a58 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c @@ -4116,6 +4116,21 @@ MvGop110PortInit ( /* MAC unreset */ MvGop110GmacReset (Port, UNRESET); break; + case MV_MODE_SFI: + /* Configure PCS */ + MvGopXpcsModeCfg (Port, MVPP2_SFI_LANE_COUNT); + + MvGopMpcsModeCfg (Port); + + /* Configure MAC */ + MvGopXlgMacModeCfg (Port); + + /* PCS unreset */ + MvGopXpcsUnreset (Port); + + /* MAC unreset */ + MvGopXlgMacUnreset (Port); + break; default: return -1; } @@ -4512,6 +4527,118 @@ Mvpp2SmiPhyAddrCfg ( return 0; } =20 +/* Set the internal mux's to the required PCS */ +EFI_STATUS +MvGopXpcsModeCfg ( + IN PP2DXE_PORT *Port, + IN INT32 NumOfLanes + ) +{ + UINT8 LaneCoeff; + + switch (NumOfLanes) { + case 1: + case 2: + case 4: + LaneCoeff =3D NumOfLanes >> 1; + default: + return EFI_INVALID_PARAMETER; + } + + /* Configure XG MAC mode */ + MmioAndThenOr32 ( + Port->Priv->XpcsBase + MVPP22_XPCS_GLOBAL_CFG_0_REG, + ~(MVPP22_XPCS_PCSMODE_MASK | MVPP22_XPCS_LANEACTIVE_MASK), + LaneCoeff << MVPP22_XPCS_LANEACTIVE_OFFS + ); + + return EFI_SUCCESS; +} + +VOID +MvGopMpcsModeCfg ( + IN PP2DXE_PORT *Port + ) +{ + /* Configure MPCS40G COMMON CONTROL */ + MmioAnd32 ( + Port->Priv->MpcsBase + MVPP22_MPCS40G_COMMON_CONTROL, + ~MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK + ); + + /* Configure MPCS CLOCK RESET */ + MmioAndThenOr32 ( + Port->Priv->MpcsBase + MVPP22_MPCS_CLOCK_RESET, + ~(MVPP22_MPCS_CLK_DIVISION_RATIO_MASK | MVPP22_MPCS_CLK_DIV_PHAS= E_SET_MASK), + MVPP22_MPCS_CLK_DIVISION_RATIO_DEFAULT | MVPP22_MPCS_MAC_CLK_RES= ET_MASK | + MVPP22_MPCS_RX_SD_CLK_RESET_MASK | MVPP22_MPCS_TX_SD_CLK_RESET_M= ASK + ); +} + +/* Set the internal mux's to the required MAC in the GOP */ +VOID +MvGopXlgMacModeCfg ( + IN PP2DXE_PORT *Port + ) +{ + /* Configure 10G MAC mode */ + MmioOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, MV_XLG_MAC_CTRL0_RX= FCEN_MASK); + + MmioAndThenOr32 ( + Port->XlgBase + MV_XLG_PORT_MAC_CTRL3_REG, + ~MV_XLG_MAC_CTRL3_MACMODESELECT_MASK, + MV_XLG_MAC_CTRL3_MACMODESELECT_10G + ); + + MmioAndThenOr32 ( + Port->XlgBase + MV_XLG_PORT_MAC_CTRL4_REG, + ~(MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_MASK | MV_XLG_MAC_CTRL4_EN_ID= LE_CHECK_FOR_LINK_MASK), + MV_XLG_MAC_CTRL4_FORWARD_PFC_EN_MASK | MV_XLG_MAC_CTRL4_FORWARD_= 802_3X_FC_EN_MASK + ); + + /* Configure frame size limit */ + MmioAndThenOr32 ( + Port->XlgBase + MV_XLG_PORT_MAC_CTRL1_REG, + ~MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK, + MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_DEFAULT + ); + + /* Mask all port's external interrupts */ + MvGop110XlgPortLinkEventMask (Port); + + /* Unmask link change interrupt - enable automatic status update */ + MmioOr32 ( + Port->XlgBase + MV_XLG_INTERRUPT_MASK_REG, + MV_XLG_INTERRUPT_LINK_CHANGE_MASK | MV_XLG_SUMMARY_INTERRUPT_MASK + ); +} + +/* Set PCS to exit from reset */ +VOID +MvGopXpcsUnreset ( + IN PP2DXE_PORT *Port + ) +{ + MmioOr32 (Port->Priv->XpcsBase + MVPP22_XPCS_GLOBAL_CFG_0_REG, MVPP22_XP= CS_PCSRESET); +} + +/* Set the MAC to exit from reset */ +VOID +MvGopXlgMacUnreset ( + IN PP2DXE_PORT *Port + ) +{ + MmioOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, MV_XLG_MAC_CTRL0_MA= CRESETN_MASK); +} + +BOOLEAN +MvGop110XlgLinkStatusGet ( + IN PP2DXE_PORT *Port + ) +{ + return MmioRead32 (Port->XlgBase + MV_XLG_MAC_PORT_STATUS_REG) & MV_XLG_= MAC_PORT_STATUS_LINKSTATUS_MASK; +} + BOOLEAN MvGop110PortIsLinkUp ( IN PP2DXE_PORT *Port @@ -4522,6 +4649,8 @@ MvGop110PortIsLinkUp ( case MV_MODE_SGMII: case MV_MODE_QSGMII: return MvGop110GmacLinkStatusGet (Port); + case MV_MODE_SFI: + return MvGop110XlgLinkStatusGet (Port); case MV_MODE_XAUI: case MV_MODE_RXAUI: return FALSE; @@ -4546,6 +4675,32 @@ MvGop110GmacLinkStatusGet ( return (Val & 1) ? TRUE : FALSE; } =20 +STATIC +VOID +MvGop110XlgPortEnable ( + IN PP2DXE_PORT *Port + ) +{ + /* Enable port and MIB counters update */ + MmioAndThenOr32 ( + Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, + ~MV_XLG_MAC_CTRL0_MIBCNTDIS_MASK, + MV_XLG_MAC_CTRL0_PORTEN_MASK + ); +} + +STATIC +VOID +MvGop110XlgPortDisable ( + IN PP2DXE_PORT *Port + ) +{ + /* Mask all port's external interrupts */ + MvGop110XlgPortLinkEventMask (Port); + + MmioAnd32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, ~MV_XLG_MAC_CTRL0_= PORTEN_MASK); +} + VOID MvGop110PortDisable ( IN PP2DXE_PORT *Port @@ -4557,6 +4712,11 @@ MvGop110PortDisable ( case MV_MODE_QSGMII: MvGop110GmacPortDisable (Port); break; + case MV_MODE_XAUI: + case MV_MODE_RXAUI: + case MV_MODE_SFI: + MvGop110XlgPortDisable (Port); + break; default: return; } @@ -4573,6 +4733,11 @@ MvGop110PortEnable ( case MV_MODE_QSGMII: MvGop110GmacPortEnable (Port); break; + case MV_MODE_XAUI: + case MV_MODE_RXAUI: + case MV_MODE_SFI: + MvGop110XlgPortEnable (Port); + break; default: return; } @@ -4622,6 +4787,17 @@ MvGop110GmacPortLinkEventMask ( MvGop110GmacWrite (Port, MV_GMAC_INTERRUPT_SUM_MASK_REG, RegVal); } =20 +VOID +MvGop110XlgPortLinkEventMask ( + IN PP2DXE_PORT *Port + ) +{ + MmioAnd32 ( + Port->XlgBase + MV_XLG_EXTERNAL_INTERRUPT_MASK_REG, + ~MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_MASK + ); +} + INT32 MvGop110PortEventsMask ( IN PP2DXE_PORT *Port @@ -4634,6 +4810,11 @@ MvGop110PortEventsMask ( case MV_MODE_QSGMII: MvGop110GmacPortLinkEventMask (Port); break; + case MV_MODE_XAUI: + case MV_MODE_RXAUI: + case MV_MODE_SFI: + MvGop110XlgPortLinkEventMask (Port); + break; default: return -1; } @@ -4655,6 +4836,7 @@ MvGop110FlCfg ( break; case MV_MODE_XAUI: case MV_MODE_RXAUI: + case MV_MODE_SFI: return 0; default: return -1; @@ -4679,6 +4861,7 @@ MvGop110SpeedDuplexSet ( break; case MV_MODE_XAUI: case MV_MODE_RXAUI: + case MV_MODE_SFI: break; default: return -1; diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h index d7d5dcb..a7011f7 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h @@ -433,6 +433,32 @@ Mvpp2SmiPhyAddrCfg ( IN INT32 Addr ); =20 +EFI_STATUS +MvGopXpcsModeCfg ( + IN PP2DXE_PORT *Port, + IN INT32 NumOfLanes + ); + +VOID +MvGopMpcsModeCfg ( + IN PP2DXE_PORT *Port + ); + +VOID +MvGopXlgMacModeCfg ( + IN PP2DXE_PORT *Port + ); + +VOID +MvGopXpcsUnreset ( + IN PP2DXE_PORT *Port + ); + +VOID +MvGopXlgMacUnreset ( + IN PP2DXE_PORT *Port + ); + BOOLEAN MvGop110PortIsLinkUp ( IN PP2DXE_PORT *Port @@ -473,6 +499,11 @@ MvGop110PortEventsMask ( IN PP2DXE_PORT *Port ); =20 +VOID +MvGop110XlgPortLinkEventMask ( + IN PP2DXE_PORT *Port + ); + INT32 MvGop110FlCfg ( IN PP2DXE_PORT *Port diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Ma= rvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h index 868be53..52509b0 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h @@ -885,6 +885,30 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH D= AMAGE. #define MVPP2_PORT_CTRL4_LEDS_NUMBER_MASK \ (0x0000003f << MVPP2_PORT_CTRL4_LEDS_NUMBER_OFFS) =20 +/* XPCS registers */ + +/* Global Configuration 0 */ +#define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0 +#define MVPP22_XPCS_PCSRESET BIT(0) +#define MVPP22_XPCS_PCSMODE_OFFS 3 +#define MVPP22_XPCS_PCSMODE_MASK (0x3 << MVPP22_XPCS= _PCSMODE_OFFS) +#define MVPP22_XPCS_LANEACTIVE_OFFS 5 +#define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << MVPP22_XPCS= _LANEACTIVE_OFFS) + +/* MPCS registers */ + +#define MVPP22_MPCS40G_COMMON_CONTROL 0x14 +#define MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK BIT(10) + +#define MVPP22_MPCS_CLOCK_RESET 0x14c +#define MVPP22_MPCS_TX_SD_CLK_RESET_MASK BIT(0) +#define MVPP22_MPCS_RX_SD_CLK_RESET_MASK BIT(1) +#define MVPP22_MPCS_MAC_CLK_RESET_MASK BIT(2) +#define MVPP22_MPCS_CLK_DIVISION_RATIO_OFFS 4 +#define MVPP22_MPCS_CLK_DIVISION_RATIO_MASK (0x7 << MVPP22_MPCS= _CLK_DIVISION_RATIO_OFFS) +#define MVPP22_MPCS_CLK_DIVISION_RATIO_DEFAULT (0x1 << MVPP22_MPCS= _CLK_DIVISION_RATIO_OFFS) +#define MVPP22_MPCS_CLK_DIV_PHASE_SET_MASK BIT(11) + /* Descriptor ring Macros */ #define MVPP2_QUEUE_NEXT_DESC(q, index) (((index) < (q)-= >LastDesc) ? ((index) + 1) : 0) =20 @@ -1089,6 +1113,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. #define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS 0 #define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK \ (0x00001fff << MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS) +#define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_DEFAULT 0x1400 =20 #define MV_XLG_MAC_CTRL1_MACLOOPBACKEN_OFFS 13 #define MV_XLG_MAC_CTRL1_MACLOOPBACKEN_MASK \ @@ -1167,7 +1192,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. (0x00000001 << MV_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL_OFFS) =20 /* Port Fifos Thresholds Configuration */ -#define MV_XLG_PORT_FIFOS_THRS_CFG_REG (0x001) +#define MV_XLG_PORT_FIFOS_THRS_CFG_REG (0x0010) #define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS 0 #define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_MASK \ (0x0000001f << MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS) @@ -1193,6 +1218,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. #define MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS 13 #define MV_XLG_MAC_CTRL3_MACMODESELECT_MASK \ (0x00000007 << MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS) +#define MV_XLG_MAC_CTRL3_MACMODESELECT_10G \ + (0x00000001 << MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS) =20 /* Port Per Prio Flow Control Status */ #define MV_XLG_PORT_PER_PRIO_FLOW_CTRL_STATUS_REG (0x0020) @@ -1382,6 +1409,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH= DAMAGE. #define MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_MASK \ (0x00000001 << MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_OFFS) =20 +#define MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK 14 +#define MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK_MASK \ + (0x00000001 << MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK) + /* Port Mac Control5 */ #define MV_XLG_PORT_MAC_CTRL5_REG (0x0088) #define MV_XLG_MAC_CTRL5_TXIPGLENGTH_OFFS 0 @@ -1542,6 +1573,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. #define MV_XLG_INTERRUPT_CAUSE_REG (0x0014) /* Port Interrupt Mask */ #define MV_XLG_INTERRUPT_MASK_REG (0x0018) +#define MV_XLG_SUMMARY_INTERRUPT_OFFSET 0 +#define MV_XLG_SUMMARY_INTERRUPT_MASK \ + (0x1 << MV_XLG_SUMMARY_INTERRUPT_OFFSET) #define MV_XLG_INTERRUPT_LINK_CHANGE_OFFS 1 #define MV_XLG_INTERRUPT_LINK_CHANGE_MASK \ (0x1 << MV_XLG_INTERRUPT_LINK_CHANGE_OFFS) @@ -1926,6 +1960,9 @@ typedef struct { #define MVPP2_B_HDR_INFO_LAST_MASK BIT(12) #define MVPP2_B_HDR_INFO_IS_LAST(info) ((info & MVPP2_B_HDR_INFO_LAST_M= ASK) >> MVPP2_B_HDR_INFO_LAST_OFFS) =20 +/* SerDes */ +#define MVPP2_SFI_LANE_COUNT 1 + /* Net Complex */ enum MvNetcTopology { MV_NETC_GE_MAC0_RXAUI_L23 =3D BIT(0), diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.c index d53f3b7..bdaf1a0 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -1171,6 +1171,8 @@ Pp2DxeInitialise ( =20 Mvpp2Shared->Base =3D PcdGet64 (PcdPp2SharedAddress); Mvpp2Shared->Rfu1Base =3D Mvpp2Shared->Base + MVPP22_RFU1_OFFSET; + Mvpp2Shared->XpcsBase =3D Mvpp2Shared->Base + MVPP22_XPCS_OFFSET; + Mvpp2Shared->MpcsBase =3D Mvpp2Shared->Base + MVPP22_MPCS_OFFSET; Mvpp2Shared->SmiBase =3D Mvpp2Shared->Base + MVPP22_SMI_OFFSET; Mvpp2Shared->Tclk =3D PcdGet32 (PcdPp2ClockFrequency); =20 diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.h index a179638..1e03a69 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h @@ -116,6 +116,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define MV_MODE_RGMII PHY_CONNECTION_RGMII #define MV_MODE_XAUI PHY_CONNECTION_XAUI #define MV_MODE_RXAUI PHY_CONNECTION_RXAUI +#define MV_MODE_SFI PHY_CONNECTION_SFI #define MV_MODE_QSGMII 100 #define PP2DXE_MAX_PHY 2 =20 @@ -263,9 +264,10 @@ typedef struct Pp2DxePort PP2DXE_PORT; typedef struct { /* Shared registers' base addresses */ UINT64 Base; + UINT64 MpcsBase; UINT64 Rfu1Base; UINT64 SmiBase; - VOID *LmsBase; + UINT64 XpcsBase; =20 /* List of pointers to Port structures */ PP2DXE_PORT **PortList; diff --git a/Platform/Marvell/Include/Protocol/MvPhy.h b/Platform/Marvell/I= nclude/Protocol/MvPhy.h index 43a9e0b..a91759a 100644 --- a/Platform/Marvell/Include/Protocol/MvPhy.h +++ b/Platform/Marvell/Include/Protocol/MvPhy.h @@ -47,7 +47,8 @@ typedef enum { PHY_CONNECTION_SGMII, PHY_CONNECTION_RTBI, PHY_CONNECTION_XAUI, - PHY_CONNECTION_RXAUI + PHY_CONNECTION_RXAUI, + PHY_CONNECTION_SFI } PHY_CONNECTION; =20 typedef enum { --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 01:19:39 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5sm263439lfe.72.2017.08.31.19.33.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 19:33:32 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=I1I+IBg1kg3vhEr6lCkFQXnu1M/aB/bBiukahCwJS/U=; b=ynV943epPsRYBAYyPZ3EObBxUo9gtHZKx4ZGZqwdEMcb4/R4SMHUYcmCCK/r7dU1Ri wZRBskNJF5tCkK3yU9HIreAk5PHzHo8VD8TUwb5sw3EHnpdRPT8TehYgMgMkJyjXX091 yBQJq0V+ksc3UYzgtQJbH8xVorR+DLBBKEZQqCOI+ujOJtKoj1jMaHFJw70v/3VM2GXH sWg/oH0dPIlpWuGnb8Ne/pR9ksLytnBWHcjJjT7niGL6nt5h5cJNzjP+CxC2igD/+oZR gM53a94uel7wDFmSOvT+PfpRzthJUyQsZ2otAECgW/JFWcJFEBnDsIdBMHku7GFrK7mN oIOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=I1I+IBg1kg3vhEr6lCkFQXnu1M/aB/bBiukahCwJS/U=; b=AtgJ84lYkWdEjnWUwBrtkP6TDJhzjdo0rwnJp5O3KqM9eWeZukK7S//wPNBbgk5mx9 F++CfyNrTbQCxPn9kGyTFlogXUTPWnEuaqVGxIoAbMW2FSXnP5ovgfJG1m6WmUdy1t0E C+8Tqw3RKX3hy8QgToI4RFR53/eajjuPW0HZMQTyyF4LMhw/sA65CeLMpayKQWNbxNR3 xZvRa2d4ulRzVeVDAzgeJezUPdwRrBdYPzIiq9/IyU7+WdracL5kxGXawtmxAg8Ypxjm qUPVsq/qHkTo74wnHkedWwUn7xF0g8kf69SBETT+9VmTwEKkRAuDTkr4fhmiveLjfBva ynyg== X-Gm-Message-State: AHPjjUhEQgPF5+HnajIGvm1trefcnfEkCiKU0qn+5IbjdjJVnKbNzxWi hPW/9R6xPM4s8Y4YKNFJyg== X-Google-Smtp-Source: ADKCNb4pRSrN766xQjiB9Cp+nz6AULN44gTP+YPthPJGCkRQwSoJVD6RkBgCj3ZB34OWJBMAQgb0Mw== X-Received: by 10.46.5.195 with SMTP id 186mr153451ljf.85.1504233214156; Thu, 31 Aug 2017 19:33:34 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 04:37:27 +0200 Message-Id: <1504233451-6455-4-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504233451-6455-1-git-send-email-mw@semihalf.com> References: <1504233451-6455-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 3/7] Drivers/Net/Pp2Dxe: Support multiple ethernet ports simultaneously X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, Joe Zhou , ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Joe Zhou In order to operate simultaneously properly, all ports should use their own resources instead of shared BM Pool and queues. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Joe Zhou Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c | 2 +- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 110 ++++++++++++++++-----= ---- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 10 ++- 3 files changed, 77 insertions(+), 45 deletions(-) diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c index 5fb7a58..85948fc 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c @@ -2747,7 +2747,7 @@ Mvpp2BmStop ( UINT32 Val, i; =20 for (i =3D 0; i < MVPP2_BM_SIZE; i++) { - Mvpp2Read (Priv, MVPP2_BM_PHY_ALLOC_REG(0)); + Mvpp2Read (Priv, MVPP2_BM_PHY_ALLOC_REG(Pool)); } =20 Val =3D Mvpp2Read (Priv, MVPP2_BM_POOL_CTRL_REG(Pool)); diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.c index bdaf1a0..42cf0f9 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -189,32 +189,43 @@ Pp2DxeBmPoolInit ( Mvpp2BmIrqClear(Mvpp2Shared, Index); } =20 - Mvpp2Shared->BmPools =3D AllocateZeroPool (sizeof(MVPP2_BMS_POOL)); + for (Index =3D 0; Index < MVPP2_MAX_PORT; Index++) { + Mvpp2Shared->BmPools[Index] =3D AllocateZeroPool (sizeof(MVPP2_BMS_POO= L)); =20 - if (Mvpp2Shared->BmPools =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } + if (Mvpp2Shared->BmPools[Index] =3D=3D NULL) { + Status =3D EFI_OUT_OF_RESOURCES; + goto FreePools; + } =20 - Status =3D DmaAllocateAlignedBuffer (EfiBootServicesData, - EFI_SIZE_TO_PAGES (PoolSize), - MVPP2_BM_POOL_PTR_ALIGN, - (VOID **)&PoolAddr); - if (EFI_ERROR (Status)) { - goto FreePools; - } + Status =3D DmaAllocateAlignedBuffer (EfiBootServicesData, + EFI_SIZE_TO_PAGES (PoolSize), + MVPP2_BM_POOL_PTR_ALIGN, + (VOID **)&PoolAddr); + if (EFI_ERROR (Status)) { + goto FreeBmPools; + } =20 - ZeroMem (PoolAddr, PoolSize); + ZeroMem (PoolAddr, PoolSize); =20 - Mvpp2Shared->BmPools->Id =3D MVPP2_BM_POOL; - Mvpp2Shared->BmPools->VirtAddr =3D (UINT32 *)PoolAddr; - Mvpp2Shared->BmPools->PhysAddr =3D (UINTN)PoolAddr; + Mvpp2Shared->BmPools[Index]->Id =3D Index; + Mvpp2Shared->BmPools[Index]->VirtAddr =3D (UINT32 *)PoolAddr; + Mvpp2Shared->BmPools[Index]->PhysAddr =3D (UINTN)PoolAddr; =20 - Mvpp2BmPoolHwCreate(Mvpp2Shared, Mvpp2Shared->BmPools, MVPP2_BM_SIZE); + Mvpp2BmPoolHwCreate(Mvpp2Shared, Mvpp2Shared->BmPools[Index], MVPP2_BM= _SIZE); + } =20 return EFI_SUCCESS; =20 +FreeBmPools: + FreePool (Mvpp2Shared->BmPools[Index]); FreePools: - FreePool (Mvpp2Shared->BmPools); + while (Index-- >=3D 0) { + FreePool (Mvpp2Shared->BmPools[Index]); + DmaFreeBuffer ( + EFI_SIZE_TO_PAGES (PoolSize), + Mvpp2Shared->BmPools[Index]->VirtAddr + ); + } return Status; } =20 @@ -226,22 +237,24 @@ Pp2DxeBmStart ( ) { UINT8 *Buff, *BuffPhys; - INTN Index; + INTN Index, Pool; =20 ASSERT(BM_ALIGN >=3D sizeof(UINTN)); =20 - Mvpp2BmPoolCtrl(Mvpp2Shared, MVPP2_BM_POOL, MVPP2_START); - Mvpp2BmPoolBufsizeSet(Mvpp2Shared, Mvpp2Shared->BmPools, RX_BUFFER_SIZE); + for (Pool =3D 0; Pool < MVPP2_MAX_PORT; Pool++) { + Mvpp2BmPoolCtrl(Mvpp2Shared, Pool, MVPP2_START); + Mvpp2BmPoolBufsizeSet(Mvpp2Shared, Mvpp2Shared->BmPools[Pool], RX_BUFF= ER_SIZE); =20 - /* Fill BM pool with Buffers */ - for (Index =3D 0; Index < MVPP2_BM_SIZE; Index++) { - Buff =3D (UINT8 *)(BufferLocation.RxBuffers + (Index * RX_BUFFER_SIZE)= ); - if (Buff =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } + /* Fill BM pool with Buffers */ + for (Index =3D 0; Index < MVPP2_BM_SIZE; Index++) { + Buff =3D (UINT8 *)(BufferLocation.RxBuffers[Pool] + (Index * RX_BUFF= ER_SIZE)); + if (Buff =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } =20 - BuffPhys =3D ALIGN_POINTER(Buff, BM_ALIGN); - Mvpp2BmPoolPut(Mvpp2Shared, MVPP2_BM_POOL, (UINTN)BuffPhys, (UINTN)Buf= fPhys); + BuffPhys =3D ALIGN_POINTER(Buff, BM_ALIGN); + Mvpp2BmPoolPut(Mvpp2Shared, Pool, (UINTN)BuffPhys, (UINTN)BuffPhys); + } } =20 return EFI_SUCCESS; @@ -415,7 +428,7 @@ Pp2DxeLatePortInitialize ( } =20 /* Use preallocated area */ - Port->Txqs[0].Descs =3D BufferLocation.TxDescs; + Port->Txqs[0].Descs =3D BufferLocation.TxDescs[Port->Id]; =20 for (Queue =3D 0; Queue < TxqNumber; Queue++) { MVPP2_TX_QUEUE *Txq =3D &Port->Txqs[Queue]; @@ -431,7 +444,7 @@ Pp2DxeLatePortInitialize ( return EFI_OUT_OF_RESOURCES; } =20 - Port->Rxqs[0].Descs =3D BufferLocation.RxDescs; + Port->Rxqs[0].Descs =3D BufferLocation.RxDescs[Port->Id]; =20 for (Queue =3D 0; Queue < TxqNumber; Queue++) { MVPP2_RX_QUEUE *Rxq =3D &Port->Rxqs[Queue]; @@ -465,8 +478,8 @@ Pp2DxeLateInitialize ( } =20 /* Attach pool to Rxq */ - Mvpp2RxqLongPoolSet(Port, 0, MVPP2_BM_POOL); - Mvpp2RxqShortPoolSet(Port, 0, MVPP2_BM_POOL); + Mvpp2RxqLongPoolSet(Port, 0, Port->Id); + Mvpp2RxqShortPoolSet(Port, 0, Port->Id); =20 /* * Mark this port being fully initialized, @@ -654,9 +667,13 @@ Pp2DxeHalt ( PP2DXE_CONTEXT *Pp2Context =3D Context; PP2DXE_PORT *Port =3D &Pp2Context->Port; STATIC BOOLEAN CommonPartHalted =3D FALSE; + INTN Index; =20 if (!CommonPartHalted) { - Mvpp2BmStop(Mvpp2Shared, MVPP2_BM_POOL); + for (Index =3D 0; Index < MVPP2_MAX_PORT; Index++) { + Mvpp2BmStop(Mvpp2Shared, Index); + } + CommonPartHalted =3D TRUE; } =20 @@ -1188,13 +1205,26 @@ Pp2DxeInitialise ( =20 ZeroMem (BufferSpace, BD_SPACE); =20 - BufferLocation.TxDescs =3D BufferSpace; - BufferLocation.AggrTxDescs =3D (MVPP2_TX_DESC *)((UINTN)BufferSpace + MV= PP2_MAX_TXD * sizeof(MVPP2_TX_DESC)); - BufferLocation.RxDescs =3D (MVPP2_RX_DESC *)((UINTN)BufferSpace + - (MVPP2_MAX_TXD + MVPP2_AGGR_T= XQ_SIZE) * sizeof(MVPP2_TX_DESC)); - BufferLocation.RxBuffers =3D (DmaAddrT)(BufferSpace + - (MVPP2_MAX_TXD + MVPP2_AGGR_TXQ_SI= ZE) * sizeof(MVPP2_TX_DESC) + - MVPP2_MAX_RXD * sizeof(MVPP2_RX_DE= SC)); + for (Index =3D 0; Index < MVPP2_MAX_PORT; Index++) { + BufferLocation.TxDescs[Index] =3D (MVPP2_TX_DESC *) + (BufferSpace + Index * MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC)); + } + + BufferLocation.AggrTxDescs =3D (MVPP2_TX_DESC *) + ((UINTN)BufferSpace + MVPP2_MAX_TXD * MVPP2_MAX_PORT * sizeof(MVPP2_TX= _DESC)); + + for (Index =3D 0; Index < MVPP2_MAX_PORT; Index++) { + BufferLocation.RxDescs[Index] =3D (MVPP2_RX_DESC *) + ((UINTN)BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_T= XQ_SIZE) * + sizeof(MVPP2_TX_DESC) + Index * MVPP2_MAX_RXD * sizeof(MVPP2_RX_DESC= )); + } + + for (Index =3D 0; Index < MVPP2_MAX_PORT; Index++) { + BufferLocation.RxBuffers[Index] =3D (DmaAddrT) + (BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE= ) * + sizeof(MVPP2_TX_DESC) + MVPP2_MAX_RXD * MVPP2_MAX_PORT * sizeof(MVPP= 2_RX_DESC) + + Index * MVPP2_BM_SIZE * RX_BUFFER_SIZE); + } =20 /* Initialize HW */ Mvpp2AxiConfig(Mvpp2Shared); diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.h index 1e03a69..b85cff7 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h @@ -56,6 +56,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #include "Mvpp2LibHw.h" =20 +#define MVPP2_MAX_PORT 3 + #define PP2DXE_SIGNATURE SIGNATURE_32('P', 'P', '2', 'D= ') #define INSTANCE_FROM_SNP(a) CR((a), PP2DXE_CONTEXT, Snp, P= P2DXE_SIGNATURE) =20 @@ -276,7 +278,7 @@ typedef struct { MVPP2_TX_QUEUE *AggrTxqs; =20 /* BM pools */ - MVPP2_BMS_POOL *BmPools; + MVPP2_BMS_POOL *BmPools[MVPP2_MAX_PORT]; =20 /* PRS shadow table */ MVPP2_PRS_SHADOW *PrsShadow; @@ -330,10 +332,10 @@ struct Pp2DxePort { =20 /* Structure for preallocation for buffer */ typedef struct { - MVPP2_TX_DESC *TxDescs; + MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT]; MVPP2_TX_DESC *AggrTxDescs; - MVPP2_RX_DESC *RxDescs; - DmaAddrT RxBuffers; + MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT]; + DmaAddrT RxBuffers[MVPP2_MAX_PORT]; } BUFFER_LOCATION; =20 typedef struct { --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 01:19:39 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504233224357992.6447288684194; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5sm263439lfe.72.2017.08.31.19.33.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 19:33:34 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KEWADQldFSHyBKKW1eLSEwSvShTDidhGkZHeIrOqqbs=; b=1KVODAjsk6+WgK8IFzx8I4/mjZ7P/AB+JawGfGm4no8Vnq36e6ztCwoj5S5l8UNq2T gZMequqr/VfO8YNncnkN6MN4o2tDt1BVMi0HnLm7fWMElp/nvkPlgKX74dGGfniAFE4M regVY9wFmOS/YLbM3FARN5Qif8+XqkzTVu8ADu3sMGxb88pP+hPw/4tHo6Ek2H2WsllE IfCb4/U5p8cxomMG7pUK6TkrJ6qGd8x58x7pZgtYYbF8GRlk3OnsJh3GCRP61TiORkN6 9IfxnU2Y1zEu7Afk2vtB6yBnsH9gWpNdiUE/rCpypnYf0AHtnqcg5ecvmN4BqEDoUEWK qOkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KEWADQldFSHyBKKW1eLSEwSvShTDidhGkZHeIrOqqbs=; b=WjJ/Yy9IFW1JT/OTdOvSq3BYCn9dZoce1Wio07wYGPupKjZMgDVhNKfN8ENpYKkAkg Gw6hoByitV+ZtQ3uUfMvklzbhj9HOnbJoqVVUrtn5tMzAqWm0a65oK2GmxMDp0hNtsEy MUYQ2sjAidQOrpk0TyZ6OfyU59V+SDHw52KuLIBxhHUO6t4g34GMZUES/5Cx4xqIZYJ9 CMhq783EpHm8aJ2i/V4hQwJ2btrSnWF/DMnEKsXH5FBDKdsS4Hv4T78EqyzhL9ReKw6z QrIGoKQukHktCTEYtleV9oGjTXkBL1RLL2lzInyDZp9mUtSTWhrRNyUG0yVvPPFrzpQ9 aPmA== X-Gm-Message-State: AHPjjUjxczCvYdkB4MEoiCN9P1UDc7UX6VXoND8IulQ9B9RtABVetvDS 1eE7f2CGP8fHvwH5hhX88g== X-Google-Smtp-Source: ADKCNb6VFmlwkxgWjVSZUdl1WoHMftfzYUvzKjQWY2fdgJJRbW1hiH2Gr6G7GBebGN8thbbQx5Gh+g== X-Received: by 10.46.6.17 with SMTP id 17mr138258ljg.31.1504233215579; Thu, 31 Aug 2017 19:33:35 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 04:37:28 +0200 Message-Id: <1504233451-6455-5-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504233451-6455-1-git-send-email-mw@semihalf.com> References: <1504233451-6455-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 4/7] Drivers/Net/Pp2Dxe: Increase amount of ingress resources X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, Joe Zhou , ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Joe Zhou Increase Rx ring and BM pool size for each port, which is helpful when dealing with more intense incoming network traffic. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Joe Zhou --- Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h | 2 +- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Ma= rvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h index 52509b0..0ebf936 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h @@ -965,7 +965,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define MVPP2_RXQ_TOTAL_NUM (MVPP2_MAX_PORTS= * MVPP2_MAX_RXQ) =20 /* Max number of Rx descriptors */ -#define MVPP2_MAX_RXD 32 +#define MVPP2_MAX_RXD 64 =20 /* Max number of Tx descriptors */ #define MVPP2_MAX_TXD 32 diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.h index b85cff7..9e71ec9 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h @@ -138,7 +138,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DA= MAGE. #define MVPP2_BM_SWF_LONG_POOL(Port) ((Port > 2) ? 2 : Port) #define MVPP2_BM_SWF_SHORT_POOL 3 #define MVPP2_BM_POOL 0 -#define MVPP2_BM_SIZE 32 +#define MVPP2_BM_SIZE 64 =20 /* * BM short pool packet Size --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 01:19:39 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504233227477333.32049219247824; Thu, 31 Aug 2017 19:33:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DB7B321E74900; Thu, 31 Aug 2017 19:30:56 -0700 (PDT) Received: from mail-lf0-x22d.google.com (mail-lf0-x22d.google.com [IPv6:2a00:1450:4010:c07::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D51F121E2BE3D for ; Thu, 31 Aug 2017 19:30:54 -0700 (PDT) Received: by mail-lf0-x22d.google.com with SMTP id y128so4754059lfd.4 for ; Thu, 31 Aug 2017 19:33:38 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5sm263439lfe.72.2017.08.31.19.33.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 19:33:36 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P1R7Rn2lhfScy9BjHGrIukHzGv1h9IM54VR7ehORn0U=; b=d0vCr5jC0r4U68RoVYmwUvSHxdf1T+9A3+Ybessh3GxiO9/ysqrzKVvLF+6U6XaRIQ 4AurmEcP87rme5ZuO2hMvdN2PbwRtqKx5xWrGh5ksKeJhnCjsH+WX8MIRHKT9ioPipgO rQbtOx+Pz63EgWHezdM0FCcBXjP1dnh8YJDlZRXmOxNyyzov7w8u8PwQfuYdN8ByxC1I 2GMovcr7mrpTCfVJ15yNjSPLIlLtHPF/iLfZC1D9gJoIqXCcvydYRWK9psiJl0ThMzNz EWUA1Jo2IvpRE3CknexYSrp5RaLR46tVMxEBkZYN7mmixnChvMW+SFEqZzevr4FH7K/m 0oTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P1R7Rn2lhfScy9BjHGrIukHzGv1h9IM54VR7ehORn0U=; b=R2Vj3+7O6OhfHvxI20q3ZWBaDookqP+bobOC63kJteGNFovQz0fRcbrHPmv773a7lb cjwSyanxKYd6aalz4P85zBFAfsYYrtYNeY2Mkayr2eE0AEdQ/or/Clmsvxezt+AxTPh9 SxgRtZ7/ScF6Kwq4vK4Bm4MZ7oSglR8zD/mXsbjCIzOhGYoIwvt7yDNloeXPj6gY5p0T QNemMp7VotWQbSqnRb5rLm7EejXLSryGTRFxvV+8VwrOlCMFY+c3vAHCBlz+rPv4Os1d ZFVgszsMVOmNYtqq+JK5SFHAUtzW8H4S4Dfbypc5b82uTLtArbADK0K5rTzXlMmTJCBS EqCg== X-Gm-Message-State: AHPjjUjNeHWBAv+L3ut2VXUeFsBDjT1HM1kxAz886DcESeoORu8/kpVR YZ1QNnvsCx/9okVfz0QIWw== X-Google-Smtp-Source: ADKCNb4na2uK/SNHqkPdR910uHHiPzpE6yLPp045W8JHJebpiSMvDdGA3Hngg9/VIRl06dgR64xByg== X-Received: by 10.46.80.2 with SMTP id e2mr149968ljb.167.1504233216933; Thu, 31 Aug 2017 19:33:36 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 04:37:29 +0200 Message-Id: <1504233451-6455-6-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504233451-6455-1-git-send-email-mw@semihalf.com> References: <1504233451-6455-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 5/7] Platforms/Marvell: Update ethernet ports types on A70x0 DB X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Modify ethernet Port0 and Port1 types to be on par with the board settings. Initial support required extra extension boards and converters. This patch sets ports to following settings: * Port0 (eth0) -> SFI @ 10Gbps * Port1 (eth1) -> SGMII over 88E1512 PHY @ 1Gbps Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index d77e0b6..bbe6ba5 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -101,8 +101,8 @@ =20 #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SGMII0;SA= TA1;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5= 000" + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1= ;USB3_HOST1;PCIE2" + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;= 5000" =20 #UtmiPhy gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 @@ -115,7 +115,7 @@ gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200 =20 #PHY - gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x4, 0x4, 0x0 } + gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x8, 0x4, 0x0 } gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE =20 @@ -123,8 +123,8 @@ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 } gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 } - gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 } gMarvellTokenSpaceGuid.PcdPp2NumPorts|3 gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 01:19:39 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1504233230338308.2964311092842; Thu, 31 Aug 2017 19:33:50 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2CB7321E74907; Thu, 31 Aug 2017 19:30:58 -0700 (PDT) Received: from mail-lf0-x230.google.com (mail-lf0-x230.google.com [IPv6:2a00:1450:4010:c07::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8F96921EB5283 for ; Thu, 31 Aug 2017 19:30:56 -0700 (PDT) Received: by mail-lf0-x230.google.com with SMTP id z12so4778354lfd.3 for ; Thu, 31 Aug 2017 19:33:40 -0700 (PDT) Received: from enkidu.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5sm263439lfe.72.2017.08.31.19.33.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 19:33:37 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2bGQ7hRCD7fDHK9Uuwh4EqMEc+0bI9WjB1itHEqvIsI=; b=YGq17MCnbskFII0ePPczgn8NAyYTOe7NVWBy7+L53xIfLCORS8c51+N1rHlLm3czck Km5tBoE8lgm5W3xzQmzAbMLZ0GelHRzCJCWjKbp+AWlPF4TnAje0Ys7a3Xc1sRiFzfmd Lj5ylyXeG6M1oSxxW7dvd1/F+X7oVccfnDDct3XarmqmEJyNYV/qAaSIR00MdnRC/qv8 vHWEBOpzDJdCVH7cXFhm+Cx3YUVGMVE9RGWuHBKZP9iPnhL8dWeHm08wjui42ZRQye4c 0BlzjrnKA5UWElf0jKxWzZESWTwV0gr8SF3/n1+djxHCKuRx/k14VsNIE+BOFbYpXhNg frSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2bGQ7hRCD7fDHK9Uuwh4EqMEc+0bI9WjB1itHEqvIsI=; b=PwzEP0ydKAXJL4nysrak5hvypGMiMgTRIW9gA2uWyPsvbcvf+CmakSLQLKRXNhviN0 DdbBUQa3REetObbe9oXesPao6ZBfnPAMwXh/Qqbysn5DMgw1CebCMdW2vEtGK65gkr4s xVMbeuhxTiU3U0Hle7xkKKynwP6MUVgNsSPOYDdIPAsBb2ImpQvpfK1HLqMEgSJFnCUp uruY7yNWL3J31w5gtimJT1ycHkJSVXFDCAe0vfjaPSHIWFEMxuJcr0CHev0ihFJXnWKG I+0EMSpzlkxtINaOBx0Xc9S60lBff2gPJ5b/zkfeTjfNaggHzV47nvYvHQcyjRcJKI1Y fsmQ== X-Gm-Message-State: AHPjjUjv3N9MP4SxFqy1sNytpYQuP6BLV+4Z6x2sS3IBX9Q1Sgs+B+Hx azX2sJx61bZLibA5bwYxAw== X-Google-Smtp-Source: ADKCNb7aj4p5Tu8TQqiTPWczYJ6b65jXxE7eUhLFMeqYAqhPAzamA2ao5Y9HVXQJLsOpHnCPlS0riQ== X-Received: by 10.46.13.18 with SMTP id 18mr188690ljn.156.1504233218261; Thu, 31 Aug 2017 19:33:38 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 04:37:30 +0200 Message-Id: <1504233451-6455-7-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504233451-6455-1-git-send-email-mw@semihalf.com> References: <1504233451-6455-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 6/7] Drivers/Net/Pp2Dxe: Move devices description to MvHwDescLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch introduces Pp2Dxe description, using the new structures and template in MvHwDescLib. This change enables more flexible addition of multiple Pp2Dxe controllers. For that purpose, static global variables (BufferLocation and Mvpp2Shared) had to be replaced by dynamically allocated resources. PortingGuide is updated accordingly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 3 +- .../Marvell/Documentation/PortingGuide/Pp2.txt | 9 +- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 109 ++++++++++++++++-= ---- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 19 ++-- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 3 +- Platform/Marvell/Include/Library/MvHwDescLib.h | 26 +++++ Platform/Marvell/Marvell.dec | 3 +- 7 files changed, 125 insertions(+), 47 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index bbe6ba5..334bfaa 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -121,13 +121,12 @@ =20 #NET gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 } - gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 } gMarvellTokenSpaceGuid.PcdPp2NumPorts|3 gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } - gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000 + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } =20 #PciEmulation gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 } diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform= /Marvell/Documentation/PortingGuide/Pp2.txt index 3c2f418..9b829c9 100644 --- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt +++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt @@ -3,6 +3,9 @@ Pp2Dxe porting guide Pp2Dxe is driver supporting PP2 NIC on Marvell platforms. Following PCDs are required to operate: =20 +Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled: + gMarvellTokenSpaceGuid.PcdPp2Controllers + Number of ports/network interfaces: gMarvellTokenSpaceGuid.PcdPp2NumPorts =20 @@ -30,9 +33,3 @@ PHY_SPEED (in Mbps) is defined as follows: 4 SPEED_2500, 5 SPEED_10000 } PHY_SPEED; - -Base address of shared register space of PP2: - gMarvellTokenSpaceGuid.PcdPp2SharedAddress - -TCLK frequency in Hz: - gMarvellTokenSpaceGuid.PcdPp2ClockFrequency diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 42cf0f9..8e6bfbc 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -42,6 +42,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. #include #include #include +#include #include #include #include @@ -53,8 +54,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMA= GE. =20 #define ReturnUnlock(tpl, status) do { gBS->RestoreTPL (tpl); return (stat= us); } while(0) =20 -STATIC MVPP2_SHARED *Mvpp2Shared; -STATIC BUFFER_LOCATION BufferLocation; +DECLARE_A7K8K_PP2_TEMPLATE; + STATIC PP2_DEVICE_PATH Pp2DevicePathTemplate =3D { { { @@ -172,7 +173,7 @@ QueueRemove ( STATIC EFI_STATUS Pp2DxeBmPoolInit ( - VOID + MVPP2_SHARED *Mvpp2Shared ) { INTN Index; @@ -233,7 +234,7 @@ FreePools: STATIC EFI_STATUS Pp2DxeBmStart ( - VOID + MVPP2_SHARED *Mvpp2Shared ) { UINT8 *Buff, *BuffPhys; @@ -247,7 +248,7 @@ Pp2DxeBmStart ( =20 /* Fill BM pool with Buffers */ for (Index =3D 0; Index < MVPP2_BM_SIZE; Index++) { - Buff =3D (UINT8 *)(BufferLocation.RxBuffers[Pool] + (Index * RX_BUFF= ER_SIZE)); + Buff =3D (UINT8 *)(Mvpp2Shared->BufferLocation.RxBuffers[Pool] + (In= dex * RX_BUFFER_SIZE)); if (Buff =3D=3D NULL) { return EFI_OUT_OF_RESOURCES; } @@ -342,6 +343,7 @@ Pp2DxeSetupAggrTxqs ( ) { MVPP2_TX_QUEUE *AggrTxq; + MVPP2_SHARED *Mvpp2Shared =3D Pp2Context->Port.Priv; =20 AggrTxq =3D Mvpp2Shared->AggrTxqs; AggrTxq->DescsPhys =3D (DmaAddrT)AggrTxq->Descs; @@ -361,6 +363,7 @@ Pp2DxeOpen ( ) { PP2DXE_PORT *Port =3D &Pp2Context->Port; + MVPP2_SHARED *Mvpp2Shared =3D Pp2Context->Port.Priv; UINT8 MacBcast[NET_ETHER_ADDR_LEN] =3D { 0xff, 0xff, 0xff, 0xff, 0xff, 0= xff }; UINT8 DevAddr[NET_ETHER_ADDR_LEN]; INTN Ret; @@ -412,6 +415,7 @@ Pp2DxeLatePortInitialize ( ) { PP2DXE_PORT *Port =3D &Pp2Context->Port; + MVPP2_SHARED *Mvpp2Shared =3D Pp2Context->Port.Priv; INTN Queue; =20 Port->TxRingSize =3D MVPP2_MAX_TXD; @@ -428,7 +432,7 @@ Pp2DxeLatePortInitialize ( } =20 /* Use preallocated area */ - Port->Txqs[0].Descs =3D BufferLocation.TxDescs[Port->Id]; + Port->Txqs[0].Descs =3D Mvpp2Shared->BufferLocation.TxDescs[Port->Id]; =20 for (Queue =3D 0; Queue < TxqNumber; Queue++) { MVPP2_TX_QUEUE *Txq =3D &Port->Txqs[Queue]; @@ -444,7 +448,7 @@ Pp2DxeLatePortInitialize ( return EFI_OUT_OF_RESOURCES; } =20 - Port->Rxqs[0].Descs =3D BufferLocation.RxDescs[Port->Id]; + Port->Rxqs[0].Descs =3D Mvpp2Shared->BufferLocation.RxDescs[Port->Id]; =20 for (Queue =3D 0; Queue < TxqNumber; Queue++) { MVPP2_RX_QUEUE *Rxq =3D &Port->Rxqs[Queue]; @@ -666,6 +670,7 @@ Pp2DxeHalt ( { PP2DXE_CONTEXT *Pp2Context =3D Context; PP2DXE_PORT *Port =3D &Pp2Context->Port; + MVPP2_SHARED *Mvpp2Shared =3D Pp2Context->Port.Priv; STATIC BOOLEAN CommonPartHalted =3D FALSE; INTN Index; =20 @@ -737,6 +742,7 @@ Pp2SnpStationAddress ( PP2DXE_CONTEXT *Pp2Context =3D INSTANCE_FROM_SNP(Snp); PP2_DEVICE_PATH *Pp2DevicePath =3D Pp2Context->DevicePath; PP2DXE_PORT *Port =3D &Pp2Context->Port; + MVPP2_SHARED *Mvpp2Shared =3D Pp2Context->Port.Priv; UINT32 State =3D Snp->Mode->State; EFI_TPL SavedTpl; INTN Ret; @@ -877,6 +883,7 @@ Pp2SnpTransmit ( { PP2DXE_CONTEXT *Pp2Context =3D INSTANCE_FROM_SNP(This); PP2DXE_PORT *Port =3D &Pp2Context->Port; + MVPP2_SHARED *Mvpp2Shared =3D Pp2Context->Port.Priv; MVPP2_TX_QUEUE *AggrTxq =3D Mvpp2Shared->AggrTxqs; MVPP2_TX_DESC *TxDesc; EFI_STATUS Status; @@ -1002,6 +1009,7 @@ Pp2SnpReceive ( INTN ReceivedPackets; PP2DXE_CONTEXT *Pp2Context =3D INSTANCE_FROM_SNP(This); PP2DXE_PORT *Port =3D &Pp2Context->Port; + MVPP2_SHARED *Mvpp2Shared =3D Pp2Context->Port.Priv; UINTN PhysAddr, VirtAddr; EFI_STATUS Status =3D EFI_SUCCESS; EFI_TPL SavedTpl; @@ -1160,11 +1168,12 @@ Pp2DxeParsePortPcd ( Pp2Context->Port.Speed =3D Speed[Pp2Context->Instance]; } =20 +STATIC EFI_STATUS -EFIAPI -Pp2DxeInitialise ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable +Pp2DxeInitialiseController ( + IN MVPP2_SHARED *Mvpp2Shared, + IN UINTN BaseAddress, + IN UINTN ClockFrequency ) { PP2DXE_CONTEXT *Pp2Context =3D NULL; @@ -1179,19 +1188,12 @@ Pp2DxeInitialise ( return EFI_INVALID_PARAMETER; } =20 - /* Initialize private data */ - Mvpp2Shared =3D AllocateZeroPool (sizeof (MVPP2_SHARED)); - if (Mvpp2Shared =3D=3D NULL) { - DEBUG((DEBUG_ERROR, "Allocation fail.\n")); - return EFI_OUT_OF_RESOURCES; - } - - Mvpp2Shared->Base =3D PcdGet64 (PcdPp2SharedAddress); + Mvpp2Shared->Base =3D BaseAddress; Mvpp2Shared->Rfu1Base =3D Mvpp2Shared->Base + MVPP22_RFU1_OFFSET; Mvpp2Shared->XpcsBase =3D Mvpp2Shared->Base + MVPP22_XPCS_OFFSET; Mvpp2Shared->MpcsBase =3D Mvpp2Shared->Base + MVPP22_MPCS_OFFSET; Mvpp2Shared->SmiBase =3D Mvpp2Shared->Base + MVPP22_SMI_OFFSET; - Mvpp2Shared->Tclk =3D PcdGet32 (PcdPp2ClockFrequency); + Mvpp2Shared->Tclk =3D ClockFrequency; =20 /* Prepare buffers */ Status =3D DmaAllocateAlignedBuffer (EfiBootServicesData, @@ -1206,21 +1208,21 @@ Pp2DxeInitialise ( ZeroMem (BufferSpace, BD_SPACE); =20 for (Index =3D 0; Index < MVPP2_MAX_PORT; Index++) { - BufferLocation.TxDescs[Index] =3D (MVPP2_TX_DESC *) + Mvpp2Shared->BufferLocation.TxDescs[Index] =3D (MVPP2_TX_DESC *) (BufferSpace + Index * MVPP2_MAX_TXD * sizeof(MVPP2_TX_DESC)); } =20 - BufferLocation.AggrTxDescs =3D (MVPP2_TX_DESC *) + Mvpp2Shared->BufferLocation.AggrTxDescs =3D (MVPP2_TX_DESC *) ((UINTN)BufferSpace + MVPP2_MAX_TXD * MVPP2_MAX_PORT * sizeof(MVPP2_TX= _DESC)); =20 for (Index =3D 0; Index < MVPP2_MAX_PORT; Index++) { - BufferLocation.RxDescs[Index] =3D (MVPP2_RX_DESC *) + Mvpp2Shared->BufferLocation.RxDescs[Index] =3D (MVPP2_RX_DESC *) ((UINTN)BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_T= XQ_SIZE) * sizeof(MVPP2_TX_DESC) + Index * MVPP2_MAX_RXD * sizeof(MVPP2_RX_DESC= )); } =20 for (Index =3D 0; Index < MVPP2_MAX_PORT; Index++) { - BufferLocation.RxBuffers[Index] =3D (DmaAddrT) + Mvpp2Shared->BufferLocation.RxBuffers[Index] =3D (DmaAddrT) (BufferSpace + (MVPP2_MAX_TXD * MVPP2_MAX_PORT + MVPP2_AGGR_TXQ_SIZE= ) * sizeof(MVPP2_TX_DESC) + MVPP2_MAX_RXD * MVPP2_MAX_PORT * sizeof(MVPP= 2_RX_DESC) + Index * MVPP2_BM_SIZE * RX_BUFFER_SIZE); @@ -1228,7 +1230,7 @@ Pp2DxeInitialise ( =20 /* Initialize HW */ Mvpp2AxiConfig(Mvpp2Shared); - Pp2DxeBmPoolInit(); + Pp2DxeBmPoolInit (Mvpp2Shared); Mvpp2RxFifoInit(Mvpp2Shared); =20 Mvpp2Shared->PrsShadow =3D AllocateZeroPool (sizeof(MVPP2_PRS_SHADOW) * = MVPP2_PRS_TCAM_SRAM_SIZE); @@ -1245,7 +1247,7 @@ Pp2DxeInitialise ( =20 Mvpp2ClsInit(Mvpp2Shared); =20 - Status =3D Pp2DxeBmStart(); + Status =3D Pp2DxeBmStart (Mvpp2Shared); if (EFI_ERROR(Status)) { DEBUG((DEBUG_ERROR, "Pp2Dxe: BM start error\n")); return Status; @@ -1258,7 +1260,7 @@ Pp2DxeInitialise ( return EFI_OUT_OF_RESOURCES; } =20 - Mvpp2Shared->AggrTxqs->Descs =3D BufferLocation.AggrTxDescs; + Mvpp2Shared->AggrTxqs->Descs =3D Mvpp2Shared->BufferLocation.AggrTxDescs; Mvpp2Shared->AggrTxqs->Id =3D 0; Mvpp2Shared->AggrTxqs->LogId =3D 0; Mvpp2Shared->AggrTxqs->Size =3D MVPP2_AGGR_TXQ_SIZE; @@ -1316,3 +1318,56 @@ Pp2DxeInitialise ( =20 return EFI_SUCCESS; } + +EFI_STATUS +EFIAPI +Pp2DxeInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + MVHW_PP2_DESC *Desc =3D &mA7k8kPp2DescTemplate; + UINT8 *Pp2DeviceTable, Index; + MVPP2_SHARED *Mvpp2Shared; + EFI_STATUS Status; + + /* Obtain table with enabled Pp2 devices */ + Pp2DeviceTable =3D (UINT8 *)PcdGetPtr (PcdPp2Controllers); + if (Pp2DeviceTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Missing PcdPp2Controllers\n")); + return EFI_INVALID_PARAMETER; + } + + if (PcdGetSize (PcdPp2Controllers) > MVHW_MAX_PP2_DEVS) { + DEBUG ((DEBUG_ERROR, "Wrong PcdPp2Controllers format\n")); + return EFI_INVALID_PARAMETER; + } + + /* Initialize enabled chips */ + for (Index =3D 0; Index < PcdGetSize (PcdPp2Controllers); Index++) { + if (!MVHW_DEV_ENABLED (Pp2, Index)) { + DEBUG ((DEBUG_ERROR, "Skip Pp2 controller %d\n", Index)); + continue; + } + + /* Initialize private data */ + Mvpp2Shared =3D AllocateZeroPool (sizeof (MVPP2_SHARED)); + if (Mvpp2Shared =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Pp2Dxe #%d: Mvpp2Shared allocation fail\n", In= dex)); + return EFI_OUT_OF_RESOURCES; + } + + Status =3D Pp2DxeInitialiseController ( + Mvpp2Shared, + Desc->Pp2BaseAddresses[Index], + Desc->Pp2ClockFrequency[Index] + ); + if (EFI_ERROR(Status)) { + FreePool (Mvpp2Shared); + DEBUG ((DEBUG_ERROR, "Pp2Dxe #%d: Controller initialisation fail\n",= Index)); + return Status; + } + } + + return EFI_SUCCESS; +} diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.h index 9e71ec9..7071cef 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h @@ -262,6 +262,14 @@ typedef struct { =20 typedef struct Pp2DxePort PP2DXE_PORT; =20 +/* Structure for preallocation for buffer */ +typedef struct { + MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT]; + MVPP2_TX_DESC *AggrTxDescs; + MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT]; + DmaAddrT RxBuffers[MVPP2_MAX_PORT]; +} BUFFER_LOCATION; + /* Shared Packet Processor resources */ typedef struct { /* Shared registers' base addresses */ @@ -271,6 +279,9 @@ typedef struct { UINT64 SmiBase; UINT64 XpcsBase; =20 + /* Preallocated buffers */ + BUFFER_LOCATION BufferLocation; + /* List of pointers to Port structures */ PP2DXE_PORT **PortList; =20 @@ -330,14 +341,6 @@ struct Pp2DxePort { UINT8 FirstRxq; }; =20 -/* Structure for preallocation for buffer */ -typedef struct { - MVPP2_TX_DESC *TxDescs[MVPP2_MAX_PORT]; - MVPP2_TX_DESC *AggrTxDescs; - MVPP2_RX_DESC *RxDescs[MVPP2_MAX_PORT]; - DmaAddrT RxBuffers[MVPP2_MAX_PORT]; -} BUFFER_LOCATION; - typedef struct { MAC_ADDR_DEVICE_PATH Pp2Mac; EFI_DEVICE_PATH_PROTOCOL End; diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index ecd82b6..b67162d 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -73,13 +73,12 @@ [Pcd] gMarvellTokenSpaceGuid.PcdPhyConnectionTypes gMarvellTokenSpaceGuid.PcdPhySmiAddresses - gMarvellTokenSpaceGuid.PcdPp2ClockFrequency + gMarvellTokenSpaceGuid.PcdPp2Controllers gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed gMarvellTokenSpaceGuid.PcdPp2NumPorts gMarvellTokenSpaceGuid.PcdPp2PortIds - gMarvellTokenSpaceGuid.PcdPp2SharedAddress =20 [Depex] TRUE diff --git a/Platform/Marvell/Include/Library/MvHwDescLib.h b/Platform/Marv= ell/Include/Library/MvHwDescLib.h index ac8dc37..6a86865 100644 --- a/Platform/Marvell/Include/Library/MvHwDescLib.h +++ b/Platform/Marvell/Include/Library/MvHwDescLib.h @@ -85,6 +85,17 @@ typedef struct { } MVHW_NONDISCOVERABLE_DESC; =20 // +// PP2 NIC devices description template definition +// +#define MVHW_MAX_PP2_DEVS 4 + +typedef struct { + UINT8 Pp2DevCount; + UINTN Pp2BaseAddresses[MVHW_MAX_PP2_DEVS]; + UINTN Pp2ClockFrequency[MVHW_MAX_PP2_DEVS]; +} MVHW_PP2_DESC; + +// // RealTimeClock devices description template definition // #define MVHW_MAX_RTC_DEVS 2 @@ -153,6 +164,21 @@ MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTem= plate =3D {\ } =20 // +// Platform description of Pp2 NIC devices +// +#define MVHW_CP0_PP2_BASE 0xF2000000 +#define MVHW_CP1_PP2_BASE 0xF4000000 +#define MVHW_PP2_CLK_FREQ 333333333 + +#define DECLARE_A7K8K_PP2_TEMPLATE \ +STATIC \ +MVHW_PP2_DESC mA7k8kPp2DescTemplate =3D {\ + 2,\ + { MVHW_CP0_PP2_BASE, MVHW_CP1_PP2_BASE },\ + { MVHW_PP2_CLK_FREQ, MVHW_PP2_CLK_FREQ } \ +} + +// // Platform description of RealTimeClock devices // #define MVHW_CP0_RTC0_BASE 0xF2284000 diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index 9e2f706..e6a3621 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -169,13 +169,12 @@ =20 #NET gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }|VOID*|0x3000024 - gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|0|UINT32|0x3000026 + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x0 }|VOID*|0x3000028 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029 gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C - gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0|UINT64|0x300002F =20 #PciEmulation gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x0 }|VOID*|0x3000033 --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sat May 4 01:19:39 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; 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[31.172.191.173]) by smtp.gmail.com with ESMTPSA id p5sm263439lfe.72.2017.08.31.19.33.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 19:33:38 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=g73vO4SB/xLUG9yDwExDmgJpZSjk+ANI6TEFfo3++wU=; b=X8QgrLIiWnFgDZ/5WeFQ4Cytb64PJBaGqUBnb29T7RSk72BwHaoDxJefy9EpI++FHL xfx0/7UwNLKi4j008OybVK9scJNpJVWykuq5vAzkvjzuZ/ZolAn4T76pDC8PMmOV988Y Wh2Ovb9sEMW93519CpxnnPDY6TWXKzuvW5RYhmAnsPvK/ojxHY47zf/wZOBOVjNw8XVy /EO/UH+BKcDFNoQ7C1PDgs48hlVLvsZbW2tXrCPBMBb/6CasP2GaB/ffxWWA1rPOCyjx YHJnQh2tABubGKboxntcV/mk2aAnRW7nlC9qBlEcDWnEFPjQr607X8jReBsuYt5NHt6n s4Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=g73vO4SB/xLUG9yDwExDmgJpZSjk+ANI6TEFfo3++wU=; b=I+rHk+M+HOvwKR6rB73rM98U+rwLqh/BcYiHAjDboLfApeMNkmleLh8IbCT6QL4F/L DJuPfyIqQRLfTnjRZEcgcdX+O4ivfgvZqECvD7k1QhPPdM+8IsKTgAKSP21aPQBi/GuX s62MfvieeBwIF9K9Qe/e4I7h/g1n+/0T4JLFj47pJfGx+oA40YSqjv6YXCG3KRPWBEbw 9Ir749CjhVh2y7ThmlxD9K/Xd78yHRxHdhsR5PKYfia338hhms9MRfYIzn46uMvpNy9m 95SrfR6ld3xGaXektUwrRUaG5I1DzS0CtKTS4aOS6d02a0V/x5/UzxiAIDcXro7E8IWf xFNw== X-Gm-Message-State: AHPjjUhnlRxyQq1X9mH1Lku5Q15pRRgVLchD5ce5Er34+aVI9MukOoe1 /FV1KdD5C7QiKtBEtv8dfQ== X-Google-Smtp-Source: ADKCNb4Jd3nHTWihC/X23nJQwCGdhTHgAY43n0vqTmvdyi9kLtel+H+XaLUtTdhA5o1FuSOKJ0BAiA== X-Received: by 10.46.33.14 with SMTP id h14mr161772ljh.128.1504233219633; Thu, 31 Aug 2017 19:33:39 -0700 (PDT) From: Marcin Wojtas To: edk2-devel@lists.01.org Date: Fri, 1 Sep 2017 04:37:31 +0200 Message-Id: <1504233451-6455-8-git-send-email-mw@semihalf.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1504233451-6455-1-git-send-email-mw@semihalf.com> References: <1504233451-6455-1-git-send-email-mw@semihalf.com> Subject: [edk2] [platforms: PATCH 7/7] Drivers/Net/Pp2Dxe: Enable using ports from different controllers X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jinghua@marvell.com, ard.biesheuvel@linaro.org, agraf@suse.de, leif.lindholm@linaro.org, nadavh@marvell.com, neta@marvell.com, kostap@marvell.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" After Pp2Dxe data migrated to MvHwDescLib, both controllers could be used, but not at the same time. It was caused by ports' insufficient description. This patch fixes this problem by introducing new PCD responsible for the mapping between port and its controller. Also it was possible to remove redundant PcdPp2NumPorts. Update documentation accordingly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas Reviewed-by: Ard Biesheuvel --- Platform/Marvell/Armada/Armada70x0.dsc | 2 +- .../Marvell/Documentation/PortingGuide/Pp2.txt | 4 +- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 63 ++++++++++++++----= ---- Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 1 + Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf | 2 +- Platform/Marvell/Marvell.dec | 2 +- 6 files changed, 47 insertions(+), 27 deletions(-) diff --git a/Platform/Marvell/Armada/Armada70x0.dsc b/Platform/Marvell/Arma= da/Armada70x0.dsc index 334bfaa..f519196 100644 --- a/Platform/Marvell/Armada/Armada70x0.dsc +++ b/Platform/Marvell/Armada/Armada70x0.dsc @@ -124,7 +124,7 @@ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x5, 0x3, 0x3 } - gMarvellTokenSpaceGuid.PcdPp2NumPorts|3 + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 } gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } =20 diff --git a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt b/Platform= /Marvell/Documentation/PortingGuide/Pp2.txt index 9b829c9..f05ba27 100644 --- a/Platform/Marvell/Documentation/PortingGuide/Pp2.txt +++ b/Platform/Marvell/Documentation/PortingGuide/Pp2.txt @@ -6,8 +6,8 @@ are required to operate: Array with used controllers - Set to 0x1 for enabled, 0x0 for disabled: gMarvellTokenSpaceGuid.PcdPp2Controllers =20 -Number of ports/network interfaces: - gMarvellTokenSpaceGuid.PcdPp2NumPorts +Array specifying, to which controller the port belongs to: + gMarvellTokenSpaceGuid.PcdPp2Port2Controller =20 Addresses of PHY devices: gMarvellTokenSpaceGuid.PcdPhySmiAddresses diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.c index 8e6bfbc..620bd5c 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c @@ -508,9 +508,7 @@ Pp2DxePhyInitialize ( ) { EFI_STATUS Status; - UINT8 *PhyAddresses; =20 - PhyAddresses =3D PcdGetPtr (PcdPhySmiAddresses); Status =3D gBS->LocateProtocol ( &gMarvellPhyProtocolGuid, NULL, @@ -521,14 +519,14 @@ Pp2DxePhyInitialize ( return Status; } =20 - if (PhyAddresses[Pp2Context->Instance] =3D=3D 0xff) { + if (Pp2Context->Port.PhyAddr =3D=3D 0xff) { /* PHY iniitalization not required */ return EFI_SUCCESS; } =20 Status =3D Pp2Context->Phy->Init( Pp2Context->Phy, - PhyAddresses[Pp2Context->Instance], + Pp2Context->Port.PhyAddr, Pp2Context->Port.PhyInterface, &Pp2Context->PhyDev ); @@ -1145,14 +1143,16 @@ Pp2DxeSnpInstall ( STATIC VOID Pp2DxeParsePortPcd ( - IN PP2DXE_CONTEXT *Pp2Context + IN PP2DXE_CONTEXT *Pp2Context, + IN INTN Index ) { - UINT8 *PortIds, *GopIndexes, *PhyConnectionTypes, *AlwaysUp, *Speed; + UINT8 *PortIds, *GopIndexes, *PhyConnectionTypes, *AlwaysUp, *Speed, *Ph= yAddresses; =20 PortIds =3D PcdGetPtr (PcdPp2PortIds); GopIndexes =3D PcdGetPtr (PcdPp2GopIndexes); PhyConnectionTypes =3D PcdGetPtr (PcdPhyConnectionTypes); + PhyAddresses =3D PcdGetPtr (PcdPhySmiAddresses); AlwaysUp =3D PcdGetPtr (PcdPp2InterfaceAlwaysUp); Speed =3D PcdGetPtr (PcdPp2InterfaceSpeed); =20 @@ -1160,17 +1160,20 @@ Pp2DxeParsePortPcd ( ASSERT (PcdGetSize (PcdPhyConnectionTypes) =3D=3D PcdGetSize (PcdPp2Port= Ids)); ASSERT (PcdGetSize (PcdPp2InterfaceAlwaysUp) =3D=3D PcdGetSize (PcdPp2Po= rtIds)); ASSERT (PcdGetSize (PcdPp2InterfaceSpeed) =3D=3D PcdGetSize (PcdPp2PortI= ds)); - - Pp2Context->Port.Id =3D PortIds[Pp2Context->Instance]; - Pp2Context->Port.GopIndex =3D GopIndexes[Pp2Context->Instance]; - Pp2Context->Port.PhyInterface =3D PhyConnectionTypes[Pp2Context->Instanc= e]; - Pp2Context->Port.AlwaysUp =3D AlwaysUp[Pp2Context->Instance]; - Pp2Context->Port.Speed =3D Speed[Pp2Context->Instance]; + ASSERT (PcdGetSize (PcdPhySmiAddresses) =3D=3D PcdGetSize (PcdPp2PortIds= )); + + Pp2Context->Port.Id =3D PortIds[Index]; + Pp2Context->Port.GopIndex =3D GopIndexes[Index]; + Pp2Context->Port.PhyInterface =3D PhyConnectionTypes[Index]; + Pp2Context->Port.PhyAddr =3D PhyAddresses[Index]; + Pp2Context->Port.AlwaysUp =3D AlwaysUp[Index]; + Pp2Context->Port.Speed =3D Speed[Index]; } =20 STATIC EFI_STATUS Pp2DxeInitialiseController ( + IN UINT8 ControllerIndex, IN MVPP2_SHARED *Mvpp2Shared, IN UINTN BaseAddress, IN UINTN ClockFrequency @@ -1179,14 +1182,11 @@ Pp2DxeInitialiseController ( PP2DXE_CONTEXT *Pp2Context =3D NULL; EFI_STATUS Status; INTN Index; + INTN PortIndex =3D 0; VOID *BufferSpace; UINT32 NetCompConfig =3D 0; - UINT8 NumPorts =3D PcdGet32 (PcdPp2NumPorts); - - if (NumPorts =3D=3D 0) { - DEBUG((DEBUG_ERROR, "Pp2Dxe: port number set to 0\n")); - return EFI_INVALID_PARAMETER; - } + STATIC UINT8 DeviceInstance; + UINT8 *Pp2PortMappingTable; =20 Mvpp2Shared->Base =3D BaseAddress; Mvpp2Shared->Rfu1Base =3D Mvpp2Shared->Base + MVPP22_RFU1_OFFSET; @@ -1265,7 +1265,18 @@ Pp2DxeInitialiseController ( Mvpp2Shared->AggrTxqs->LogId =3D 0; Mvpp2Shared->AggrTxqs->Size =3D MVPP2_AGGR_TXQ_SIZE; =20 - for (Index =3D 0; Index < NumPorts; Index++) { + Pp2PortMappingTable =3D (UINT8 *)PcdGetPtr (PcdPp2Port2Controller); + + for (Index =3D 0; Index < PcdGetSize (PcdPp2Port2Controller); Index++) { + if (Pp2PortMappingTable[Index] !=3D ControllerIndex) { + continue; + } + + if (PortIndex++ > MVPP2_MAX_PORT) { + DEBUG ((DEBUG_ERROR, "Pp2Dxe: Wrong too many ports for single contro= ller\n")); + return EFI_INVALID_PARAMETER; + } + Pp2Context =3D AllocateZeroPool (sizeof (PP2DXE_CONTEXT)); if (Pp2Context =3D=3D NULL) { /* @@ -1277,7 +1288,8 @@ Pp2DxeInitialiseController ( } =20 /* Instances are enumerated from 0 */ - Pp2Context->Instance =3D Index; + Pp2Context->Instance =3D DeviceInstance; + DeviceInstance++; =20 /* Install SNP protocol */ Status =3D Pp2DxeSnpInstall(Pp2Context); @@ -1285,10 +1297,10 @@ Pp2DxeInitialiseController ( return Status; } =20 - Pp2DxeParsePortPcd(Pp2Context); + Pp2DxeParsePortPcd(Pp2Context, Index); Pp2Context->Port.TxpNum =3D 1; Pp2Context->Port.Priv =3D Mvpp2Shared; - Pp2Context->Port.FirstRxq =3D 4 * Pp2Context->Instance; + Pp2Context->Port.FirstRxq =3D 4 * (PortIndex - 1); Pp2Context->Port.GmacBase =3D Mvpp2Shared->Base + MVPP22_GMAC_OFFSET + MVPP22_GMAC_REG_SIZE * Pp2Context->Port.Go= pIndex; Pp2Context->Port.XlgBase =3D Mvpp2Shared->Base + MVPP22_XLG_OFFSET + @@ -1343,6 +1355,12 @@ Pp2DxeInitialise ( return EFI_INVALID_PARAMETER; } =20 + /* Check amount of declared ports */ + if (PcdGetSize (PcdPp2Port2Controller) > Desc->Pp2DevCount * MVPP2_MAX_P= ORT) { + DEBUG ((DEBUG_ERROR, "Pp2Dxe: Wrong too many ports declared\n")); + return EFI_INVALID_PARAMETER; + } + /* Initialize enabled chips */ for (Index =3D 0; Index < PcdGetSize (PcdPp2Controllers); Index++) { if (!MVHW_DEV_ENABLED (Pp2, Index)) { @@ -1358,6 +1376,7 @@ Pp2DxeInitialise ( } =20 Status =3D Pp2DxeInitialiseController ( + Index, Mvpp2Shared, Desc->Pp2BaseAddresses[Index], Desc->Pp2ClockFrequency[Index] diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvel= l/Drivers/Net/Pp2Dxe/Pp2Dxe.h index 7071cef..cde2995 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h @@ -327,6 +327,7 @@ struct Pp2DxePort { UINT16 RxRingSize; =20 INT32 PhyInterface; + UINTN PhyAddr; BOOLEAN Link; BOOLEAN Duplex; BOOLEAN AlwaysUp; diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf b/Platform/Marv= ell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf index b67162d..752fcc0 100644 --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.inf @@ -77,7 +77,7 @@ gMarvellTokenSpaceGuid.PcdPp2GopIndexes gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed - gMarvellTokenSpaceGuid.PcdPp2NumPorts + gMarvellTokenSpaceGuid.PcdPp2Port2Controller gMarvellTokenSpaceGuid.PcdPp2PortIds =20 [Depex] diff --git a/Platform/Marvell/Marvell.dec b/Platform/Marvell/Marvell.dec index e6a3621..4e2dd6d 100644 --- a/Platform/Marvell/Marvell.dec +++ b/Platform/Marvell/Marvell.dec @@ -173,7 +173,7 @@ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0 }|VOID*|0x3000029 gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0 }|VOID*|0x300002A gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x0 }|VOID*|0x300002B - gMarvellTokenSpaceGuid.PcdPp2NumPorts|0|UINT32|0x300002D + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0 }|VOID*|0x300002D gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0 }|VOID*|0x300002C =20 #PciEmulation --=20 1.8.3.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel