From nobody Sun Apr 28 17:57:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1501573862735894.359483620692; Tue, 1 Aug 2017 00:51:02 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2A88D21D28FE5; Tue, 1 Aug 2017 00:48:49 -0700 (PDT) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 46CC721D0FDE5 for ; Tue, 1 Aug 2017 00:48:47 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Aug 2017 00:50:56 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga003.jf.intel.com with ESMTP; 01 Aug 2017 00:50:43 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,305,1498546800"; d="scan'208";a="999468490" From: Eric Dong To: edk2-devel@lists.01.org Date: Tue, 1 Aug 2017 15:50:36 +0800 Message-Id: <1501573838-10740-2-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1501573838-10740-1-git-send-email-eric.dong@intel.com> References: <1501573838-10740-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 1/3] UefiCpuPkg: Add definition for LMCE feature. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong Reviewed-by: Jeff Fan --- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index 8ea0609..54153f4 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -35,6 +35,7 @@ #define CPU_FEATURE_FASTSTRINGS 6 #define CPU_FEATURE_VMX 7 #define CPU_FEATURE_SMX 8 +#define CPU_FEATURE_LMCE 9 #define CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER 10 #define CPU_FEATURE_LIMIT_CPUID_MAX_VAL 11 #define CPU_FEATURE_MCE 12 --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 17:57:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1501573865062864.7295292275919; Tue, 1 Aug 2017 00:51:05 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 66CA221D4918C; Tue, 1 Aug 2017 00:48:49 -0700 (PDT) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CF9F421D091BF for ; Tue, 1 Aug 2017 00:48:47 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Aug 2017 00:50:57 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga003.jf.intel.com with ESMTP; 01 Aug 2017 00:50:47 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,305,1498546800"; d="scan'208";a="999468493" From: Eric Dong To: edk2-devel@lists.01.org Date: Tue, 1 Aug 2017 15:50:37 +0800 Message-Id: <1501573838-10740-3-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1501573838-10740-1-git-send-email-eric.dong@intel.com> References: <1501573838-10740-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 2/3] UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 56 +++++++++++++- .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 12 +++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 1 + UefiCpuPkg/Library/CpuCommonFeaturesLib/Lmce.c | 90 ++++++++++++++++++= ++++ 4 files changed, 157 insertions(+), 2 deletions(-) create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Lmce.c diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index c03e5ab..67a44c6 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -866,8 +866,8 @@ FeatureControlGetConfigData ( CPU_FEATURE_GET_CONFIG_DATA was not provide= d in RegisterCpuFeature(). =20 - @retval TRUE Enhanced Intel SpeedStep feature is supported. - @retval FALSE Enhanced Intel SpeedStep feature is not supported. + @retval TRUE Protected Processor Inventory Number feature is support= ed. + @retval FALSE Protected Processor Inventory Number feature is not sup= ported. =20 @note This service could be called by BSP/APs. **/ @@ -909,4 +909,56 @@ PpinInitialize ( IN BOOLEAN State ); =20 +/** + Detects if Local machine check exception feature supported on current=20 + processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Local machine check exception feature is supported. + @retval FALSE Local machine check exception feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +LmceSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ); + +/** + Initializes Local machine check exception feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Local machine check exception feature is in= itialized. + +**/ +RETURN_STATUS +EFIAPI +LmceInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ); + #endif diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index b88b7d1..4c78209 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -217,6 +217,18 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { + Status =3D RegisterCpuFeature ( + "LMCE", + NULL, + LmceSupport, + LmceInitialize, + CPU_FEATURE_LMCE, + CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEF= ORE, + CPU_FEATURE_END + ); + ASSERT_EFI_ERROR (Status); + } =20 return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.i= nf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf index 202d560..2cca58e 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -48,6 +48,7 @@ PendingBreak.c X2Apic.c Ppin.c + Lmce.c =20 [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Lmce.c b/UefiCpuPkg/Li= brary/CpuCommonFeaturesLib/Lmce.c new file mode 100644 index 0000000..8f4fa03 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Lmce.c @@ -0,0 +1,90 @@ +/** @file + Local machine check exception feature. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "CpuCommonFeatures.h" + +/** + Detects if Local machine check exception feature supported on current=20 + processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Local machine check exception feature is supported. + @retval FALSE Local machine check exception feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +LmceSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ) +{ + MSR_IA32_MCG_CAP_REGISTER McgCap; + + McgCap.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_CAP); + return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P !=3D 0); +} + +/** + Initializes Local machine check exception feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Local machine check exception feature is in= itialized. + +**/ +RETURN_STATUS +EFIAPI +LmceInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ) +{ + MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; + + ASSERT (ConfigData !=3D NULL); + MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; + if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { + CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.LmceOn, + (State) ? 1 : 0 + ); + } + return RETURN_SUCCESS; +} --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 17:57:02 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1501573867815679.5676285127897; Tue, 1 Aug 2017 00:51:07 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9EE5821D491A1; Tue, 1 Aug 2017 00:48:49 -0700 (PDT) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 09D1021D091BF for ; Tue, 1 Aug 2017 00:48:48 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Aug 2017 00:50:57 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga003.jf.intel.com with ESMTP; 01 Aug 2017 00:50:52 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,305,1498546800"; d="scan'208";a="999468497" From: Eric Dong To: edk2-devel@lists.01.org Date: Tue, 1 Aug 2017 15:50:38 +0800 Message-Id: <1501573838-10740-4-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1501573838-10740-1-git-send-email-eric.dong@intel.com> References: <1501573838-10740-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 3/3] UefiCpuPkg PiSmmCpuDxeSmm: Check LMCE capability when wait for AP. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong Reviewed-by: Jeff Fan --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 57 +++++++++++++++++++++++++++++++= +++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 4ac5e8e..6b66c49 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -196,6 +196,56 @@ AllCpusInSmmWithExceptions ( return TRUE; } =20 +/** + Has OS enabled Lmce in the MSR_IA32_MCG_EXT_CTL + =20 + @retval TRUE Os enable lmce. + @retval FALSE Os not enable lmce. + +**/ +BOOLEAN +IsLmceOsEnabled ( + VOID + ) +{ + MSR_IA32_MCG_CAP_REGISTER McgCap; + MSR_IA32_FEATURE_CONTROL_REGISTER FeatureCtrl; + MSR_IA32_MCG_EXT_CTL_REGISTER McgExtCtrl; + + McgCap.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_CAP); + if (McgCap.Bits.MCG_LMCE_P =3D=3D 0) { + return FALSE; + } + + FeatureCtrl.Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL); + if (FeatureCtrl.Bits.LmceOn =3D=3D 0) { + return FALSE; + } + + McgExtCtrl.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL); + return (BOOLEAN) (McgExtCtrl.Bits.LMCE_EN =3D=3D 1); +} + +/** + Return if Local machine check exception signaled.=20 + + Indicates (when set) that a local machine check exception was generated.= This indicates that the current machine-check event was=20 + delivered to only the logical processor. + + @retval TRUE LMCE was signaled. + @retval FALSE LMCE was not signaled. + +**/ +BOOLEAN +IsLmceSignaled ( + VOID + ) +{ + MSR_IA32_MCG_STATUS_REGISTER McgStatus; + + McgStatus.Uint64 =3D AsmReadMsr64 (MSR_IA32_MCG_STATUS); + return (BOOLEAN) (McgStatus.Bits.LMCE_S =3D=3D 1); +} =20 /** Given timeout constraint, wait for all APs to arrive, and insure when th= is function returns, no AP will execute normal mode code before @@ -209,9 +259,14 @@ SmmWaitForApArrival ( { UINT64 Timer; UINTN Index; + BOOLEAN LmceEn; + BOOLEAN LmceSignal; =20 ASSERT (*mSmmMpSyncData->Counter <=3D mNumberOfCpus); =20 + LmceEn =3D IsLmceOsEnabled (); + LmceSignal =3D IsLmceSignaled(); + // // Platform implementor should choose a timeout value appropriately: // - The timeout value should balance the SMM time constrains and the li= kelihood that delayed CPUs are excluded in the SMM run. Note @@ -227,7 +282,7 @@ SmmWaitForApArrival ( // Sync with APs 1st timeout // for (Timer =3D StartSyncTimer (); - !IsSyncTimerTimeout (Timer) && + !IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) && !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EX= CEPTION_SMI_DISABLED ); ) { CpuPause (); --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel