From nobody Sun Apr 28 03:41:56 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1500448230858644.2016529497629; Wed, 19 Jul 2017 00:10:30 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6538D2193B806; Wed, 19 Jul 2017 00:08:31 -0700 (PDT) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0907821B06E6D for ; Wed, 19 Jul 2017 00:08:30 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 19 Jul 2017 00:10:24 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga004.jf.intel.com with ESMTP; 19 Jul 2017 00:10:23 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,380,1496127600"; d="scan'208";a="109554857" From: Eric Dong To: edk2-devel@lists.01.org Date: Wed, 19 Jul 2017 15:10:19 +0800 Message-Id: <1500448221-6264-2-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1500448221-6264-1-git-send-email-eric.dong@intel.com> References: <1500448221-6264-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 1/3] UefiCpuPkg: Add Pcds used by processor trace feature. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/UefiCpuPkg.dec | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index e5b0334..8779138 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -285,5 +285,15 @@ # @ValidList 0x80000001 | 0 gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00,= 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019 =20 + ## Contains the size of memory required when CPU processor trace is enab= led. + # @Prompt The memory size used for processor trace. + # @ValidList 0x80000001 | 0 + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x10|UINT32|0x60000012 + + ## Contains the processor trace output scheme when CPU processor trace i= s enabled. + # @Prompt The processor trace output scheme. + # @ValidList 0x80000001 | 0 + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x2|UINT8|0x600000= 15 + [UserExtensions.TianoCore."ExtraFiles"] UefiCpuPkgExtra.uni --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 03:41:56 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1500448232422834.8993548612625; Wed, 19 Jul 2017 00:10:32 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A10CC21D0DE7E; Wed, 19 Jul 2017 00:08:33 -0700 (PDT) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 111FE21D0DE75 for ; Wed, 19 Jul 2017 00:08:31 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 19 Jul 2017 00:10:25 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga004.jf.intel.com with ESMTP; 19 Jul 2017 00:10:24 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,380,1496127600"; d="scan'208";a="109554862" From: Eric Dong To: edk2-devel@lists.01.org Date: Wed, 19 Jul 2017 15:10:20 +0800 Message-Id: <1500448221-6264-3-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1500448221-6264-1-git-send-email-eric.dong@intel.com> References: <1500448221-6264-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 2/3] UefiCpuPkg: Add Processor Trace feature definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index 10286ed..74b683c 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -71,6 +71,7 @@ #define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE (32+9) #define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS (32+10) #define CPU_FEATURE_PPIN (32+11) +#define CPU_FEATURE_PROC_TRACE (32+12) =20 #define CPU_FEATURE_BEFORE_ALL BIT27 #define CPU_FEATURE_AFTER_ALL BIT28 --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 03:41:56 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1500448238400286.5636635680868; Wed, 19 Jul 2017 00:10:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id DC2CD2193B838; Wed, 19 Jul 2017 00:08:33 -0700 (PDT) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4380921D0DE74 for ; Wed, 19 Jul 2017 00:08:32 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 19 Jul 2017 00:10:26 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga004.jf.intel.com with ESMTP; 19 Jul 2017 00:10:25 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,380,1496127600"; d="scan'208";a="109554871" From: Eric Dong To: edk2-devel@lists.01.org Date: Wed, 19 Jul 2017 15:10:21 +0800 Message-Id: <1500448221-6264-4-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1500448221-6264-1-git-send-email-eric.dong@intel.com> References: <1500448221-6264-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch 3/3] UefiCpuPkg: Enable Processor Trace feature. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ruiyu Ni , Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jeff Fan Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 66 +++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 11 + .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 4 +- .../Library/CpuCommonFeaturesLib/ProcTrace.c | 458 +++++++++++++++++= ++++ 4 files changed, 538 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index c03e5ab..74b24f6 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -909,4 +909,70 @@ PpinInitialize ( IN BOOLEAN State ); =20 +/** + Prepares for the data used by CPU feature detection and initialization. + + @param[in] NumberOfProcessors The number of CPUs in the platform. + + @return Pointer to a buffer of CPU related configuration data. + + @note This service could be called by BSP only. +**/ +VOID * +EFIAPI +ProcTraceGetConfigData ( + IN UINTN NumberOfProcessors + ); + +/** + Detects if Intel Processor Trace feature supported on current processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Enhanced Intel SpeedStep feature is supported. + @retval FALSE Enhanced Intel SpeedStep feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +ProcTraceSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ); + +/** + Initializes Intel Processor Trace feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Intel Processor Trace feature feature is in= itialized. + +**/ +RETURN_STATUS +EFIAPI +ProcTraceInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ); + #endif diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index b88b7d1..a4cb260 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -217,6 +217,17 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) { + Status =3D RegisterCpuFeature ( + "Proc Trace", + ProcTraceGetConfigData, + ProcTraceSupport, + ProcTraceInitialize, + CPU_FEATURE_PROC_TRACE, + CPU_FEATURE_END + ); + ASSERT_EFI_ERROR (Status); + } =20 return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.i= nf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf index 202d560..e9225bb 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -48,6 +48,7 @@ PendingBreak.c X2Apic.c Ppin.c + ProcTrace.c =20 [Packages] MdePkg/MdePkg.dec @@ -66,4 +67,5 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport ## CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle ## SOMETIMES_= CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset ## SOMETIMES_= CONSUMES - + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme ## SOMETIMES_= CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize ## SOMETIMES_= CONSUMES \ No newline at end of file diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuP= kg/Library/CpuCommonFeaturesLib/ProcTrace.c new file mode 100644 index 0000000..e1b7579 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c @@ -0,0 +1,458 @@ +/** @file + Intel Processor Trace feature. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "CpuCommonFeatures.h" + +#define MAX_TOPA_ENTRY_COUNT 2 + +/// +/// Processor trace buffer size selection. +/// +typedef enum { + Enum4K =3D 0, + Enum8K, + Enum16K, + Enum32K, + Enum64K, + Enum128K, + Enum256K, + Enum512K, + Enum1M, + Enum2M, + Enum4M, + Enum8M, + Enum16M, + Enum32M, + Enum64M, + Enum128M, + EnumProcTraceMemDisable +} PROC_TRACE_MEM_SIZE; + +/// +/// Processor trace output scheme selection. +/// +typedef enum { + OutputSchemeSingleRange =3D 0, + OutputSchemeToPA, + OutputSchemeInvalid +} PROC_TRACE_OUTPUT_SCHEME; + +typedef struct { + BOOLEAN ProcTraceSupported; + BOOLEAN TopaSupported; + BOOLEAN SingleRangeSupported; + UINT8 ProcTraceOutputScheme; =20 + UINT32 ProcTraceMemSize; + UINT32 NumberOfProcessors; + + UINTN *ThreadMemRegionTable; + UINTN AllocatedThreads; + + UINTN *TopaMemArray; + UINTN TopaMemArrayCount; + +} PROC_TRACE_DATA; + +typedef struct { + UINT64 TopaEntry[MAX_TOPA_ENTRY_COUNT]; +} PROC_TRACE_TOPA_TABLE; + +/** + Prepares for the data used by CPU feature detection and initialization. + + @param[in] NumberOfProcessors The number of CPUs in the platform. + + @return Pointer to a buffer of CPU related configuration data. + + @note This service could be called by BSP only. +**/ +VOID * +EFIAPI +ProcTraceGetConfigData ( + IN UINTN NumberOfProcessors + ) +{ + PROC_TRACE_DATA *ConfigData; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; + CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx; + + ConfigData =3D AllocateZeroPool (sizeof (PROC_TRACE_DATA)); + ASSERT (ConfigData !=3D NULL); + + ConfigData->NumberOfProcessors =3D (UINT32) NumberOfProcessors; + + ConfigData->ProcTraceMemSize =3D PcdGet32 (PcdCpuProcTraceMemSize); + ConfigData->ProcTraceOutputScheme =3D PcdGet8 (PcdCpuProcTraceOutputSche= me); + + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint3= 2, NULL, NULL); + ConfigData->ProcTraceSupported =3D Ebx.Bits.IntelProcessorTrace =3D=3D 1; + + if (ConfigData->ProcTraceSupported) { + AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_M= AIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL); + ConfigData->TopaSupported =3D Ecx.Bits.RTIT =3D=3D 1; + ConfigData->SingleRangeSupported =3D Ecx.Bits.SingleRangeOutput =3D=3D= 1; + } + + return ConfigData; +} + +/** + Detects if Intel Processor Trace feature feature supported on current=20 + processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Enhanced Intel SpeedStep feature is supported. + @retval FALSE Enhanced Intel SpeedStep feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +ProcTraceSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ) +{ + PROC_TRACE_DATA *ProcTraceData; + + // + // Check if ProcTraceMemorySize option is enabled (0xFF means disable by= user) + // + ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; + if (ProcTraceData->ProcTraceMemSize >=3D EnumProcTraceMemDisable) { + return FALSE; + } + + // + // Check if Processor Trace is supported + // + if (!ProcTraceData->ProcTraceSupported) { + return FALSE; + } + + if (ProcTraceData->TopaSupported || ProcTraceData->SingleRangeSupported)= { + return TRUE; + } + + return FALSE; +} + +/** + Initializes Intel Processor Trace feature feature to specific state. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Intel Processor Trace feature feature is in= itialized. + +**/ +RETURN_STATUS +EFIAPI +ProcTraceInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ) +{ + UINT64 MsrValue; + UINT32 MemRegionSize; + UINTN Pages; + UINTN Alignment; + UINTN MemRegionBaseAddr; + UINTN *ThreadMemRegionTable; + UINTN Index; + UINTN TopaTableBaseAddr; + UINTN AlignedAddress; + UINTN *TopaMemArray; + PROC_TRACE_TOPA_TABLE *TopaTable; + PROC_TRACE_DATA *ProcTraceData; + BOOLEAN IsBsp; + + ProcTraceData =3D (PROC_TRACE_DATA *) ConfigData; + + MemRegionBaseAddr =3D 0; + IsBsp =3D FALSE; + + if (ProcessorNumber =3D=3D 0) { + IsBsp =3D TRUE; + DEBUG ((DEBUG_INFO, "Initialize Processor Trace\n")); + } + + /// + /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding + /// + MemRegionSize =3D (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12)); + if (IsBsp) { + DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegion= Size)); + } + + // + // Clear MSR_IA32_RTIT_CTL[0] and IA32_RTIT_STS only if MSR_IA32_RTIT_CT= L[0]=3D=3D1b + // + MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + if ((MsrValue & BIT0) !=3D 0) { + /// + /// Clear bit 0 in MSR IA32_RTIT_CTL (570) + /// + MsrValue &=3D (UINT64) ~BIT0; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_CTL, + MsrValue + ); + + /// + /// Clear MSR IA32_RTIT_STS (571h) to all zeros + /// + MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_STATUS); + MsrValue &=3D 0x0; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_STATUS, + MsrValue + ); + } + + if (IsBsp) { + // + // Let BSP allocate and create the necessary memory region (Aligned = to the size of + // the memory region from setup option(ProcTraceMemSize) which is an= integral multiple of 4kB) + // for the all the enabled threads for storing Processor Trace debug= data. Then Configure the trace + // address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Not= e that all regions must be + // aligned based on their size, not just 4K. Thus a 2M region must h= ave bits 20:12 clear. + // + ThreadMemRegionTable =3D (UINTN *) AllocatePool (ProcTraceData->Number= OfProcessors * sizeof (UINTN *)); + if (ThreadMemRegionTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed= \n")); + return RETURN_OUT_OF_RESOURCES; + } + ProcTraceData->ThreadMemRegionTable =3D ThreadMemRegionTable; + + for (Index =3D 0; Index < ProcTraceData->NumberOfProcessors; Index++, = ProcTraceData->AllocatedThreads++) { + Pages =3D EFI_SIZE_TO_PAGES (MemRegionSize); + Alignment =3D MemRegionSize; + AlignedAddress =3D (UINTN) AllocateAlignedReservedPages (Pages, Alig= nment); + if (AlignedAddress =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d= threads\n", ProcTraceData->AllocatedThreads)); + if (Index =3D=3D 0) { + // + // Could not allocate for BSP even + // + FreePool ((VOID *) ThreadMemRegionTable); + ThreadMemRegionTable =3D NULL; + return RETURN_OUT_OF_RESOURCES; + } + break; + } + + ThreadMemRegionTable[Index] =3D AlignedAddress; + DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for th= read %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index])); + } + + DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", Pr= ocTraceData->AllocatedThreads)); + MemRegionBaseAddr =3D ThreadMemRegionTable[0]; + } else { + if (ProcessorNumber < ProcTraceData->AllocatedThreads) { + MemRegionBaseAddr =3D ProcTraceData->ThreadMemRegionTable[ProcessorN= umber]; + } else { + return RETURN_SUCCESS; + } + } + + /// + /// Check Processor Trace output scheme: Single Range output or ToPA tab= le + /// + + // + // Single Range output scheme + // + if (ProcTraceData->SingleRangeSupported && (ProcTraceData->ProcTraceOutp= utScheme =3D=3D OutputSchemeSingleRange)) { + if (IsBsp) { + DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme = \n")); + } + + // + // Clear MSR IA32_RTIT_CTL (0x570) ToPA (Bit 8) + // + MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + MsrValue &=3D (UINT64) ~BIT8; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_CTL, + MsrValue + ); + + // + // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with the allo= cated Memory Region + // + MsrValue =3D (UINT64) MemRegionBaseAddr; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_OUTPUT_BASE, + MsrValue + ); + + // + // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT= _MASK_PTRS (561h) + // + MsrValue =3D (UINT64) MemRegionSize - 1; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_OUTPUT_MASK_PTRS, + MsrValue + ); + + } + + // + // ToPA(Table of physical address) scheme + // + if (ProcTraceData->TopaSupported && (ProcTraceData->ProcTraceOutputSchem= e =3D=3D OutputSchemeToPA)) { + // + // Create ToPA structure aligned at 4KB for each logical thread + // with at least 2 entries by 8 bytes size each. The first entry + // should have the trace output base address in bits 47:12, 6:9 + // for Size, bits 4,2 and 0 must be cleared. The second entry + // should have the base address of the table location in bits + // 47:12, bits 4 and 2 must be cleared and bit 0 must be set. + // + if (IsBsp) { + DEBUG ((DEBUG_INFO, "ProcTrace: Enabling ToPA scheme \n")); + // + // Let BSP allocate ToPA table mem for all threads + // + TopaMemArray =3D (UINTN *) AllocatePool (ProcTraceData->AllocatedThr= eads * sizeof (UINTN *)); + if (TopaMemArray =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n")); + return RETURN_OUT_OF_RESOURCES; + } + ProcTraceData->TopaMemArray =3D TopaMemArray; + + for (Index =3D 0; Index < ProcTraceData->AllocatedThreads; Index++) { + Pages =3D EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE)); + Alignment =3D 0x1000; + AlignedAddress =3D (UINTN) AllocateAlignedReservedPages (Pages, Al= ignment); + if (AlignedAddress =3D=3D 0) { + if (Index < ProcTraceData->AllocatedThreads) { + ProcTraceData->AllocatedThreads =3D Index; + } + DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocating ToPA me= m only for %d threads\n", ProcTraceData->AllocatedThreads)); + if (Index =3D=3D 0) { + // + // Could not allocate for BSP + // + FreePool ((VOID *) TopaMemArray); + TopaMemArray =3D NULL; + return RETURN_OUT_OF_RESOURCES; + } + break; + } + + TopaMemArray[Index] =3D AlignedAddress; + DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for th= read %d is 0x%llX \n", Index, (UINT64) TopaMemArray[Index])); + } + + DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n"= , ProcTraceData->AllocatedThreads)); + // + // BSP gets the first block + // + TopaTableBaseAddr =3D TopaMemArray[0]; + } else { + // + // Count for currently executing AP. + // + if (ProcessorNumber < ProcTraceData->AllocatedThreads) { + TopaTableBaseAddr =3D ProcTraceData->TopaMemArray[ProcessorNumber]; + } else { + return RETURN_SUCCESS; + } + } + + TopaTable =3D (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr; + TopaTable->TopaEntry[0] =3D (UINT64) (MemRegionBaseAddr | ((ProcTraceD= ata->ProcTraceMemSize) << 6)) & ~BIT0; + TopaTable->TopaEntry[1] =3D (UINT64) TopaTableBaseAddr | BIT0; + + // + // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[47:12] with ToPA= base + // + MsrValue =3D (UINT64) TopaTableBaseAddr; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_OUTPUT_BASE, + MsrValue + ); + + // + // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0 + // + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_OUTPUT_MASK_PTRS, + 0x7F + ); + // + // Enable ToPA output scheme by enabling MSR IA32_RTIT_CTL (0x570) ToP= A (Bit 8) + // + MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + MsrValue |=3D BIT8; + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_CTL, + MsrValue + ); + } + + /// + /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h) + /// + MsrValue =3D AsmReadMsr64 (MSR_IA32_RTIT_CTL); + MsrValue |=3D (UINT64) BIT0 + BIT2 + BIT3 + BIT13; + if (!State) { + MsrValue &=3D (UINT64) ~BIT0; + } + CPU_REGISTER_TABLE_WRITE64 ( + ProcessorNumber, + Msr, + MSR_IA32_RTIT_CTL, + MsrValue + ); + + return RETURN_SUCCESS; +} --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel