From nobody Fri May 3 05:48:31 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1500260254596438.82890598609686; Sun, 16 Jul 2017 19:57:34 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 1747B21D0B656; Sun, 16 Jul 2017 19:55:38 -0700 (PDT) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 967B52193B80A for ; Sun, 16 Jul 2017 19:55:36 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2017 19:57:28 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 16 Jul 2017 19:57:28 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,372,1496127600"; d="scan'208";a="112031237" From: Eric Dong To: edk2-devel@lists.01.org Date: Mon, 17 Jul 2017 10:57:23 +0800 Message-Id: <1500260245-5512-2-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1500260245-5512-1-git-send-email-eric.dong@intel.com> References: <1500260245-5512-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch v2 1/3] UefiCpuPkg RegisterCpuFeaturesLib: Add error handling. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Disable CPU feature may return error, add error handling code to handle it instead of assert it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong Cc: Jeff Fan --- .../Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 9 +++++= +++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index e91a438..7a76730 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -536,7 +536,14 @@ AnalysisProcessorFeatures ( } } else { Status =3D CpuFeatureInOrder->InitializeFunc (ProcessorNumber, Cpu= Info, CpuFeatureInOrder->ConfigData, FALSE); - ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + if (CpuFeatureInOrder->FeatureName !=3D NULL) { + DEBUG ((DEBUG_WARN, "Warning :: Failed to enable Feature Name = =3D %a.\n", CpuFeatureInOrder->FeatureName)); + } else { + DEBUG ((DEBUG_WARN, "Warning :: Failed to enable Feature Mask = =3D ")); + DumpCpuFeatureMask (CpuFeatureInOrder->FeatureMask); + } + } } Entry =3D Entry->ForwardLink; } --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:31 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1500260256836434.36301402488414; Sun, 16 Jul 2017 19:57:36 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 4CE5921D0B65D; Sun, 16 Jul 2017 19:55:40 -0700 (PDT) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7B1A121CF25C0 for ; Sun, 16 Jul 2017 19:55:37 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2017 19:57:29 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 16 Jul 2017 19:57:29 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,372,1496127600"; d="scan'208";a="112031240" From: Eric Dong To: edk2-devel@lists.01.org Date: Mon, 17 Jul 2017 10:57:24 +0800 Message-Id: <1500260245-5512-3-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1500260245-5512-1-git-send-email-eric.dong@intel.com> References: <1500260245-5512-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch v2 2/3] UefiCpuPkg: Add feature definition for PPIN. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong Cc: Jeff Fan --- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 1 + 1 file changed, 1 insertion(+) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index 4aa3529..10286ed 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -70,6 +70,7 @@ #define CPU_FEATURE_THREE_STRICK_COUNTER (32+8) #define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE (32+9) #define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS (32+10) +#define CPU_FEATURE_PPIN (32+11) =20 #define CPU_FEATURE_BEFORE_ALL BIT27 #define CPU_FEATURE_AFTER_ALL BIT28 --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 05:48:31 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1500260259708895.8865879955681; Sun, 16 Jul 2017 19:57:39 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8C7CC21D147B7; Sun, 16 Jul 2017 19:55:40 -0700 (PDT) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6E4F821C9E7D9 for ; Sun, 16 Jul 2017 19:55:38 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2017 19:57:30 -0700 Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.51]) by orsmga002.jf.intel.com with ESMTP; 16 Jul 2017 19:57:29 -0700 X-Original-To: edk2-devel@lists.01.org X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,372,1496127600"; d="scan'208";a="112031244" From: Eric Dong To: edk2-devel@lists.01.org Date: Mon, 17 Jul 2017 10:57:25 +0800 Message-Id: <1500260245-5512-4-git-send-email-eric.dong@intel.com> X-Mailer: git-send-email 2.7.0.windows.1 In-Reply-To: <1500260245-5512-1-git-send-email-eric.dong@intel.com> References: <1500260245-5512-1-git-send-email-eric.dong@intel.com> Subject: [edk2] [Patch v2 3/3] UefiCpuPkg CpuCommonFeaturesLib: Enable Ppin feature. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jeff Fan MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong Cc: Jeff Fan --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 55 ++++++++++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 11 ++ .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf | 1 + UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 114 +++++++++++++++++= ++++ 4 files changed, 181 insertions(+) create mode 100644 UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index 9c6e0b4..c03e5ab 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -854,4 +854,59 @@ FeatureControlGetConfigData ( IN UINTN NumberOfProcessors ); =20 +/** + Detects if Protected Processor Inventory Number feature supported on cur= rent=20 + processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Enhanced Intel SpeedStep feature is supported. + @retval FALSE Enhanced Intel SpeedStep feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +PpinSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ); + +/** + Initializes Protected Processor Inventory Number feature to specific sta= te. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Protected Processor Inventory Number featur= e is=20 + initialized. + @retval RETURN_DEVICE_ERROR Device can't change state because it has be= en=20 + locked. + +**/ +RETURN_STATUS +EFIAPI +PpinInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ); + #endif diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index 2bd32ab..b88b7d1 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -206,6 +206,17 @@ CpuCommonFeaturesLibConstructor ( ); ASSERT_EFI_ERROR (Status); } + if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) { + Status =3D RegisterCpuFeature ( + "PPIN", + NULL, + PpinSupport, + PpinInitialize, + CPU_FEATURE_PPIN, + CPU_FEATURE_END + ); + ASSERT_EFI_ERROR (Status); + } =20 return RETURN_SUCCESS; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.i= nf b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf index e68936b..202d560 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -47,6 +47,7 @@ MonitorMwait.c PendingBreak.c X2Apic.c + Ppin.c =20 [Packages] MdePkg/MdePkg.dec diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Li= brary/CpuCommonFeaturesLib/Ppin.c new file mode 100644 index 0000000..146c4cf --- /dev/null +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c @@ -0,0 +1,114 @@ +/** @file + Protected Processor Inventory Number(PPIN) feature. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "CpuCommonFeatures.h" + +/** + Detects if Protected Processor Inventory Number feature supported on cur= rent=20 + processor. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + + @retval TRUE Enhanced Intel SpeedStep feature is supported. + @retval FALSE Enhanced Intel SpeedStep feature is not supported. + + @note This service could be called by BSP/APs. +**/ +BOOLEAN +EFIAPI +PpinSupport ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData OPTIONAL + ) +{ + MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo; + + if ((CpuInfo->DisplayFamily =3D=3D 0x06) &&=20 + ((CpuInfo->DisplayModel =3D=3D 0x3E) || // Xeon E5 V2 + (CpuInfo->DisplayModel =3D=3D 0x56) || // Xeon Processor D Pro= duct + (CpuInfo->DisplayModel =3D=3D 0x4F) || // Xeon E5 v4, E7 v4 + (CpuInfo->DisplayModel =3D=3D 0x55) || // Xeon Processor Scala= ble + (CpuInfo->DisplayModel =3D=3D 0x57) || // Xeon Phi processor 3= 200, 5200, 7200 series. + (CpuInfo->DisplayModel =3D=3D 0x85) // Future Xeon phi proc= essor=20 + )) { + // + // Check whether platform support this feature. + // + PlatformInfo.Uint64 =3D AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1); + return (PlatformInfo.Bits.PPIN_CAP !=3D 0); + } + + return FALSE; +} + +/** + Initializes Protected Processor Inventory Number feature to specific sta= te. + + @param[in] ProcessorNumber The index of the CPU executing this functio= n. + @param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFOR= MATION + structure for the CPU executing this functi= on. + @param[in] ConfigData A pointer to the configuration buffer retur= ned + by CPU_FEATURE_GET_CONFIG_DATA. NULL if + CPU_FEATURE_GET_CONFIG_DATA was not provide= d in + RegisterCpuFeature(). + @param[in] State If TRUE, then the Protected Processor Inven= tory=20 + Number feature must be enabled. + If FALSE, then the Protected Processor Inve= ntory=20 + Number feature must be disabled. + + @retval RETURN_SUCCESS Protected Processor Inventory Number featur= e is=20 + initialized. + @retval RETURN_DEVICE_ERROR Device can't change state because it has be= en=20 + locked. + +**/ +RETURN_STATUS +EFIAPI +PpinInitialize ( + IN UINTN ProcessorNumber, + IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, + IN VOID *ConfigData, OPTIONAL + IN BOOLEAN State + ) +{ + MSR_IVY_BRIDGE_PPIN_CTL_REGISTER MsrPpinCtrl; + + // + // Check whether device already lock this register. + // If already locked, just base on the request state and + // the current state to return the status. + // + MsrPpinCtrl.Uint64 =3D AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL); + if (MsrPpinCtrl.Bits.LockOut !=3D 0) { + return MsrPpinCtrl.Bits.Enable_PPIN =3D=3D State ? RETURN_SUCCESS : RE= TURN_DEVICE_ERROR; + } + + CPU_REGISTER_TABLE_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IVY_BRIDGE_PPIN_CTL, + MSR_IVY_BRIDGE_PPIN_CTL_REGISTER, + Bits.Enable_PPIN, + (State) ? 1 : 0 + ); + + return RETURN_SUCCESS; +} --=20 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel