From nobody Fri May 3 04:54:32 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1497653837508485.5040313411258; Fri, 16 Jun 2017 15:57:17 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D749A21A07A99; Fri, 16 Jun 2017 15:55:54 -0700 (PDT) Received: from NAM01-BY2-obe.outbound.protection.outlook.com (mail-by2nam01on0060.outbound.protection.outlook.com [104.47.34.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 257D721A07A98 for ; Fri, 16 Jun 2017 15:55:53 -0700 (PDT) Received: from leduran-Precision-WorkStation-T5400.amd.com (165.204.78.1) by DM5PR12MB1244.namprd12.prod.outlook.com (10.168.237.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1178.14; Fri, 16 Jun 2017 22:57:10 +0000 X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=79H8GIHG99tbmVCpYmUJVMuXYz4jiAQHFHd0LQlUvtw=; b=KrQd7ysQ9w0NAOY/e5Kwcza/IuccYsuOxy6EuHuo5IfseLMvvStz/235IiGkL2vCJeyaiL2gDD1YnAMqfbDI6EbuJIXwqTKTil7uN50Dfi9xbm53z9uqKo0sy/Bbq0bm6DSbZ7gkFgOtYCj6KodtwBbu2uGEPLJ0/SIgxZ1LGDw= Authentication-Results: lists.01.org; dkim=none (message not signed) header.d=none;lists.01.org; dmarc=none action=none header.from=amd.com; From: Leo Duran To: edk2-devel@lists.01.org Date: Fri, 16 Jun 2017 17:56:59 -0500 Message-Id: <1497653820-15192-2-git-send-email-leo.duran@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497653820-15192-1-git-send-email-leo.duran@amd.com> References: <1497653820-15192-1-git-send-email-leo.duran@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.78.1] X-ClientProxiedBy: MWHPR1701CA0003.namprd17.prod.outlook.com (10.172.58.13) To DM5PR12MB1244.namprd12.prod.outlook.com (10.168.237.135) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 75b46df5-47eb-43c0-a507-08d4b50b0594 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(48565401081)(201703131423075)(201703031133081); SRVR:DM5PR12MB1244; X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 3:yF9quJ2iZplLDFUdXF4UmEYmtFKus7B5OSXEZX/6fQouFbVkcxf1u9u1Z4sLq6ur5+mICGns7p4QaXwa1IUIkzFokYtfAf4I54As6ki/3lkJnfAz+pk6ZH/3wPrDYJyqYPbfiHIFoVKwIxHggS9HvGJJsZ0yyXgzUFUorMkKo5fzTeRkKRzA8flSr4jiImwsVZoqywzP9De3CwfyKlMOfpVZoYKuoF+JosroPj5via0IV1VVg2FPFYhQ1qxI3iupb/GYdNUf3U2ol3aIVSfQkPDyqB75GgbSKwah+RIrzyohi02v7uzOdgnMrxy8nuPAcZy2S+0rdlE8GFde5l9iPbv/CxRZnwZchSbC73TnMZ4=; 25:yrcsoAECiJkMTjT3DXzN9QFjcdz9z1J5Zc8pgoFUTbFA3MxK4hmAuggLYLu6uFQPYqkK3V4DExxCy2tpvFRnAAb67Iqt2VY49OmvvI5TtEFji0UQvtV7UMzGeyZlfzdjimw8B+0BoYU70FDN7RA/1pPpkJaO2H/OHGjS9w/DoPn/qG1jv4TsseBs5epizKn5xosengzGa9pyV24rXzfjLNIs75M96u8ohBPM2QXFAZjGjk3/POKWpv7QdMwWeJzHCigMkjI18Q1QC4moYwy9t4Ph5d4LznfBxFVQEW5Z78V6FKERX70h55O/Ht+iWrCl6eDH7MYvmNaslg2equeiIrcB6hnYc6CcumAf/8Yw7o7jwK+Sin002YHYNXCaQJCgLMPJuvLsG2LINNzud1JYkFQIynh3yZGEEcGgJzkT0vkf+9mRrAX3Wl+teLAIrGW3zdfswzskvCpd6c/UecGh3bQPwm3MuFaOUpzV8kbHioU= X-MS-TrafficTypeDiagnostic: DM5PR12MB1244: X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 31:/oNKbfT3XKTAoHvCnK5zX/EqVntmDwQhmreJPiEfNYOx3R/qv9EbnSX4BGVHb56quvb7CVdcN+PH5PS7yuZ+wu1NV0+I99gy+ANnYHrmS9Gem2+HsY1xkQiGdjtg/1B+vZPsvz8iR0orQaB5K1BeqboEYVUC9t75dFP9jiUv1x+LR+n0WIXbRYdbeJPvFLVc+yKYlKNJs7QrWmT95a1UvmBETa6a7VL12rdGNw1r8hc=; 20:IIaxOTgnfINqzCamPHtmW3rEL/0E67399gZf8NV5YQEJKdbuvVFAsx1eMJbX30fAXNu1VCbmglBkV+t5kqabu7Pohi0a37I0NilqM/iRdbzvXGYCG12Q/1P8sl/+dmCI/NlEIjmc1hGFEXHtWO52co2b0qJzF3FbHui6b+5k6AQMC4nR7kkg7acHe/xNxzcEyTA2GjscYvc2/FV0oWt5DHvwQVzczcdOcGWr5SDqdpXGA/UIijHaHHgN767dnqILoWJk7BirY3N24nZ7o/Ic9In5et5v93+nSq94e0Qpamd31tM8kLRu6LMqmApdKH5ocp7XahMaFOzmT72R1z7KiZ71AKcUXIp5liE924+C2FWKnP4ka6M3CtyIh/myne8z3ssxRbQj2jWfzLSmPt+V8fhslLO9ZPeXLjFZeg9CMnZSRn+aDAwIL+frNWBrfkFb3GxkqcgqX65Tb7OUm72e1l++CKTLzekjgJNAkymW1ed/HmAz3LL9xt+gk/g2JHHR X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(767451399110)(228905959029699); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(93006095)(93001095)(3002001)(100000703101)(100105400095)(10201501046)(6055026)(6041248)(20161123558100)(20161123555025)(20161123564025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123560025)(6072148)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:DM5PR12MB1244; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:DM5PR12MB1244; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR12MB1244; 4:XDXgeTF5IAxFBtJjU0iNywe/MmvbMFw5S2jl688HID?= =?us-ascii?Q?hWPWSNwFxA68CkJGdFcz6RNjgCdDkLxsxRdRqOL1WbpmfNGBKEH5H9p8FJcp?= =?us-ascii?Q?OONLFTPaFjxTctiPM3b9/jHDO7SJXM3eB7b9wvg4PDUpCN5vdhU6LfpAg1ov?= =?us-ascii?Q?29iMze+DS/NfGDLCHM4TYzHS3Y4ZoDdDc6Ck0bRe5sLHR0WbWJfVdeZVS+yx?= =?us-ascii?Q?zujGEfJUf+QpmlHP21jkTIuf6XgvBIqOkQw7aCjYe0RedyP+KuJt/B0OHOKj?= =?us-ascii?Q?Vc5K07EoytWKX3erDnivELN5W2qlRPRQBwWf2We7ZGMQWKSYNIcTF7oZ/hLY?= =?us-ascii?Q?ux49tAoEhNRDadbmfKwPbbvnQ31QTaVizupmo9AtD4NVUNbVfGN+KoYbvrBE?= =?us-ascii?Q?kdJeAmZAGnQzvQwmXfPdqo7ecX04pemii/IJIjGUn20DinzUpPq/NLFsG5MP?= =?us-ascii?Q?5Oeo9RSUTxYfVsJQExD1AAkuTPXc/jkx1PZFDtm9/5ZncuFhtoxZKAlo0Cax?= =?us-ascii?Q?TlfnBwefAzt/SAdjQY3w2RvQ5BFiUgJFNRiAge1yCGJMIL42tDXaWRJ4802W?= =?us-ascii?Q?KdFuq1BvCGWKHMCrygfooMcpwOLclYlBDggujxgxj/+gOoVFuKXyCoJHmIro?= =?us-ascii?Q?Ecti1TEMb+PykYhV76bp0xZ/oAbByNJSSHjDzOSAkoAh5tddZXkWMW5qVQHo?= =?us-ascii?Q?MEBQ5EfBUg63lgMRltp9WIWgLvv6E19dee+q3rkYGQPs1oCzHsZ/iVo+Gqlm?= =?us-ascii?Q?GY9f0c/84iX54hXFHLEctZQ5ADHHUl4d9se+//HUFot+oA5N69LcZMKdYRyV?= =?us-ascii?Q?dJ4OXzrBe3/GBKntbDiZFAWFIh/p9zIzQ/siWwDTgMYaIN98CTctFQ4AGz6g?= =?us-ascii?Q?Qo7yezkXRUl0ZGUzkGRm+TYMuNyooL4wfSvfs8g4a570tNBMG0g1V0pNPDhP?= =?us-ascii?Q?SCvPOLTKyqGwDCpiA8GPwPA2EcKizH+zo5uKWgtjTUgbpVWqzGGUo2aijXMA?= =?us-ascii?Q?xfZtWIjYmG4BwTWI2XkvaBLnxAEEFMz3G+9RRqhqwQXWcoJL5SLphuAxpSdU?= =?us-ascii?Q?9tusgT5Uj4msHJytuCioSa4VxnP7DkWBiWAylY0n2+oHQnVuNeQ2ALDH0zWR?= =?us-ascii?Q?XgbA2/3WSNcXz+EtGvK5EcIP0EF0zRjU35CsBYFxZIhGoKm7Jx3R4pLHXOHs?= =?us-ascii?Q?mh6C4HCoXWTpzeWaybHV+27GL9NVhd63YPFOw/HARbuXE22u8XNOU221L+yU?= =?us-ascii?Q?6YGuVcQx8hfPd+bS0=3D?= X-Forefront-PRVS: 0340850FCD X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4630300001)(6009001)(39850400002)(39840400002)(39860400002)(39400400002)(39410400002)(39450400003)(110136004)(2906002)(5660300001)(38730400002)(8676002)(5003940100001)(25786009)(53936002)(33646002)(81166006)(4326008)(54906002)(86362001)(36756003)(6486002)(6116002)(2351001)(3846002)(47776003)(48376002)(66066001)(50466002)(50226002)(42186005)(478600001)(189998001)(53416004)(6916009)(6666003)(50986999)(2950100002)(2361001)(7736002)(305945005)(76176999); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1244; H:leduran-Precision-WorkStation-T5400.amd.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR12MB1244; 23:yKfClatzqw3v+CgCLRKUFqA3Cn0DMWDOyTM8ZFCwe?= =?us-ascii?Q?qe1/aCBzix/acJwGC8oGOUIykccG6K4fGQiqj7xDO0mSaac+EYo1O7hMRtVu?= =?us-ascii?Q?YnNZZkZ7kIrRCVdjepfz5jEqbTFMPDqoAP12yxaw9xn13P87PwYqLoiFiGC1?= =?us-ascii?Q?8nE60bBBJDxyJvj+NamDUrBz3mg1ibdKAt4NUIhbB6dCz3T/QDcCUowjO7L9?= =?us-ascii?Q?+fuvM8sY5ThSPUmyUoKVEE8qycxIIGCaHIUrMGDTzfS3y56A61TREw4guvQv?= =?us-ascii?Q?SASAPwxH/YA1+09u1mDM+240RIUQw7p7Om4fgM2z2RHD+yLnkUQPGeieNPOS?= =?us-ascii?Q?c0INteFvPqFO3Z2ExPupajIwZ0gLRuPahx8B1UQDAieC7tDW4sJoaQ3UBA7K?= =?us-ascii?Q?rTrliUidfuZnc8fexAgPmxHa4v9v++awsCV1P8vFUSmzzXQNEsk2yRlKgabm?= =?us-ascii?Q?QtcMBQLFOE4HONIq/B/Ar57FdAS/MMNl9oU2mMftI3052EkvRsUBBbtvHlaL?= =?us-ascii?Q?62DuZlFAdrxWXorR4C4JL+G8aVPglRCVs6TtLyGgdCNEATgaCIdE2ezurO/8?= =?us-ascii?Q?6+x//iC80e69gAHi81ymz6s/dUWuxBMvfz8vJNXLaG9oVP6U4eHD/3DxTRMr?= =?us-ascii?Q?o++rzRRhurEUhKxeAw30ydHp6V3km7FsKRU3lMix+IdIkt3fQVS4a4Fu393s?= =?us-ascii?Q?ygsHBF29t9AaJIkr4S2bs9G6rprjKw/ANssc4mFMZ2U+fkDrBoSp/qHP5QPh?= =?us-ascii?Q?XnkjNQojwZwXt8JyquRXOlGMa83+nU8qtvDHSKJecv759V9hPCyk+Bgh06kD?= =?us-ascii?Q?wZtMFL5VbDf6HOvapMEPQjPe1/GuKPayTWgjfZ/Vg3Vf+ExBRDcWNNHM4KnJ?= =?us-ascii?Q?5WLRgbV+vSgUVKglhDC1m0AxwvN0RQ2rkdp04CpjhV9UyErDRoxMeG8xjCVU?= =?us-ascii?Q?/liOFgfCXipqNjlHuHoVQwAW6cGWkJtkA4BVsvTP4QzXwQarS6C/ZWnC3ABP?= =?us-ascii?Q?PBqbuctX/jfOjXDNelnneLnfDYhj0WB81oLBZhLS68sEpGsyMAK4RA0OkPya?= =?us-ascii?Q?aOFiMXG/lF/X8K3JdCJFP2LmMhI6vesPZ93oUGx7LqazxVhcQ=3D=3D?= X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR12MB1244; 6:hpNmn8c0MGrGcqv/ooS9Uh7XoaNI/XrTftvmIDadRJ?= =?us-ascii?Q?XMDcEWwx3EHWkxoMklzVkpk/XpNs4swI5q7zBhUx+75fQK8d/r9PJuRYz6R/?= =?us-ascii?Q?5mQ2/+w2aLdK2jkXOKtXUSS8pVQuh3rhUtSlnFFb9TC02WEKGWUV6NSHyeMC?= =?us-ascii?Q?KhhKeS2nZHVY4nGtyPwrjbRQMY3DV22p6rt/62om4DqwjRMPSSuImn5lxxIJ?= =?us-ascii?Q?ALkceG01cW+eGG3r+Ycw5E4v7hCDB3OIv+h091wAqPlx2TLDYVx9g+Ztd4rw?= =?us-ascii?Q?XTHbKl2zC/aawmqilN3isi8WmcK8lR6pj7311fhAhGJXyVqV3GyuAzF0Y6vb?= =?us-ascii?Q?t0rrPPT5KhNVdDGkZRrfnqrJRga3P2jB3FKUcnyjibTyJiaK5YisorNB7hSj?= =?us-ascii?Q?vpBE2OT6rW+MmxI3foSzwuVdWErdmpK1tJm54P2RrixkLRJ1g+oQt51hLfKk?= =?us-ascii?Q?kR0KldRamCperJ8urd6T3EAF6+GMMAsG3SJvp8VtNx/5lixUTIMkvemf9BCs?= =?us-ascii?Q?2we5izI+FK3cyY8TYF1+6eJK33/CjxjZ/ZGvjjnVHAdAFKbgH44+xKZiTgMK?= =?us-ascii?Q?UP6Wbfa1p8YHT5vlDsUE27R6LMgK1N52hRMO//crWtLSgLA2nG4qK8lMkaHP?= =?us-ascii?Q?nR7R9i7FDjW7ECfmdNcacb37auSaM6LbU4VTU3VYA/Eid0ojzxgy1s1z0lXD?= =?us-ascii?Q?R4fMuW4tapYWnvZ0aY4X74rocNGfTFZiDqhp1RHd+0S0r49yWDLUV0Xv5u+b?= =?us-ascii?Q?Rjra/u6oXSifAGxz/wrhPDS2nM8R9vLTNgG7XpZXe47p3vzQjtjTg3lslyFN?= =?us-ascii?Q?y7+MIGa0y95OsNlFTRY06ryvKkYHBpJMGhAWNLTpmKhhmrX3nT9WBq+EyUPo?= =?us-ascii?Q?IcxzvswYD5ivDAijOkT6S0zdAOFls1z9FTwbJg4uq6dCwSJUDbtjRPkkZIWf?= =?us-ascii?Q?7Y2oQMnum2HWFVzQ6sWBAPVA6SAZvqyBcIaGzmdk6UHH6+ioUSVOD4Qdm+rz?= =?us-ascii?Q?8GI2tTtvTUm5csrHp3BKfY?= X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 5:HMERWTpDPLhKEndgveb14DDcQ4HxQqv5PJicc0Ekew4MZ8A3B1Mlp8DfFR3cQeSOQfMypTyKTPoBUn0a3Pp4QNiK4zth3hts7tyD2GDF9FDUvRVM6MYeVLsXITG+s0HtvMspqhpJg652pcCANWSNq95YbIGtxfkIz2ViFnoPoIJeiNaA4zQKCtcdQUcz+idv5QOwBKJ5fSfAFgcoz7QyqbYEuhVA6aBnUT9DsGSdUaaD7eKBEznMNQCzVkpObhaWbf228qPKdKEayGwMeSpv2vbAO8KIxpFUO80CLzhIvHONQoQrtM4shGqkPldR302J6ZJ2643PSi1k5NBTww2R304RO2mTtOXOVv4RnXmbDFhSMEZHZQnUQQsJql7PB7gRHOWGvdpJ7cttY+YH1m1lVWPeYSjr2Zj8syw4SiacyYKwSqxNujmIAVBgNG44Hz2HjUdeobCsaW+ds326jk3vK97EID+bojOcqVAporMdeeMG0agXx/StXiLGgA0Yy+sF; 24:ha9d50v//dG9amXSj2zHunMEo+5Z06LTRj4fvTXom11Mh04KOMLzBWpJjcA/gPSwhCbYLPkjf8ZCA0IbrB9A7IxZYvRJqaDh2unWaqURqro= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 7:PFnc6FkSb3bPk5iTec5qtrJ2BTdDBx3Tufww4rJkNECW5TfrvX3nNVoPiw1+MbWVTuHXzGSDDx/4/68mRKhpYBMVRtJvBVYzkEl0Ru7mwWNSyuUb+SzL8OTgVNwGNJzfhM7bjnzbRRZmCD5YlDu5HxWCr4nyeDk+jesXapnekuXpXlsFUOAMrsxIT2ujjtGKEY4ugHxjP20LZsI5tZpeROnLnyNvD9kZvs7UCf91KnU3OdcKGfXa/wEuUEJX6wjjgbffPvP/VYW8bwstT4uXNwZP44DkHddsiXAqWB+RE/4GDZI+QyM9WwAqT019CXPm9GaC/nF2IOSuKZhkDXQr/QWnFVbvBBTirk5xF+XG7h71ge4kQ5aMhkcy1DRf8SCJEQYtbP2zftWqkEhRqN/Mi6vWzApKERWkq1aj9FwJaodRhtvOP4u+tY81/YJ8ZtffhWGSzMM+Rpr+ayBkalO0SX7sXz1VzuLcBRBjWX1hnhaxC56SbJpPjNNczW7bOlhOnHbEHULyj5AI305jY1dtyrI7vsf3PbZadUp6Bx3TMrIq0quRMOyjrGP/9Kgr3eNYi1GkdQoWrXdUws6C0rJ+0SvAtA8Pf1lC1ir2jM62uVt8X6X+A8r1oALnBv1B9a/9ET/7d/WuKgfXcwLQQz+u7knnUhf62eRJW/sN99LNYa0h0gWltGuOzuU6gTvMmqDTfg95sfaWm/noZgE93KzzadFvCGPJq6L21Or8iTs3Wtm7iuPVb7cuGVcP0jV4p6tOIXbwWsOM+fb41EjvAMNLeRIIIQTPlORYOvnr3qYV5nM= X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 20:MVomw/8KF7yUgSbDyab2rDrS8ZwVF2zcBl1iRwiN7JsWRm//IiHIEM0p2ckrEN9JLHMezcxcncOzBCvKK4soUREtTbsyJeICL6cqgdjsgTX6GEANcHSirDlINZSJnzMASBvB5W6hCfEjLoswj0t6l9pkgrC8hOQpP8Faxsxf6NXV/jsOWXO1z9jTUTQEoQScXmu8oGq+sQBHKGnOTcuqgJFm9Lj+BAl596HwtSDWxa/HXgj/MebvTX6AOJE1G6RW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2017 22:57:10.0696 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1244 Subject: [edk2] [PATCH v4 1/2] UefiCpuPkg: Add CPUID definitions for AMD. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Leo Duran , Jeff Fan , Liming Gao Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Include/Register/Amd/Cpuid.h | 599 ++++++++++++++++++++++++++++= +++- 1 file changed, 590 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Include/Register/Amd/Cpuid.h b/UefiCpuPkg/Include/R= egister/Amd/Cpuid.h index 74ffb95..0b1204d 100644 --- a/UefiCpuPkg/Include/Register/Amd/Cpuid.h +++ b/UefiCpuPkg/Include/Register/Amd/Cpuid.h @@ -7,6 +7,7 @@ not provided for that register. =20 Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
+ This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -24,8 +25,587 @@ #define __AMD_CPUID_H__ =20 /** +CPUID Signature Information =20 - Memory Encryption Information +@param EAX CPUID_SIGNATURE (0x00) + +@retval EAX Returns the highest value the CPUID instruction recognizes f= or + returning basic processor information. The value is returned= is + processor specific. +@retval EBX First 4 characters of a vendor identification string. +@retval ECX Last 4 characters of a vendor identification string. +@retval EDX Middle 4 characters of a vendor identification string. + +**/ + +/// +/// @{ CPUID signature values returned by AMD processors +/// +#define CPUID_SIGNATURE_GENUINE_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h') +#define CPUID_SIGNATURE_GENUINE_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i') +#define CPUID_SIGNATURE_GENUINE_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D') +/// +/// @} +/// + + +/** + CPUID Extended Processor Signature and Features + + @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) + + @retval EAX Extended Family, Model, Stepping Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX. + @retval EBX Brand Identifier + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX. + @retval ECX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX. + @retval EDX Extended Feature Identifiers + described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX. +**/ + +/** + CPUID Extended Processor Signature and Features EAX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 3:0] Stepping. + /// + UINT32 Stepping:4; + /// + /// [Bits 7:4] Base Model. + /// + UINT32 BaseModel:4; + /// + /// [Bits 11:8] Base Family. + /// + UINT32 BaseFamily:4; + /// + /// [Bit 15:12] Reserved. + /// + UINT32 Reserved1:4; + /// + /// [Bits 19:16] Extended Model. + /// + UINT32 ExtModel:4; + /// + /// [Bits 27:20] Extended Family. + /// + UINT32 ExtFamily:8; + /// + /// [Bit 31:28] Reserved. + /// + UINT32 Reserved2:4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EAX; + +/** + CPUID Extended Processor Signature and Features EBX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 27:0] Reserved. + /// + UINT32 Reserved:28; + /// + /// [Bit 31:28] Package Type. + /// + UINT32 PkgType:4; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EBX; + +/** + CPUID Extended Processor Signature and Features ECX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] LAHF/SAHF available in 64-bit mode. + /// + UINT32 LAHF_SAHF:1; + /// + /// [Bit 1] Core multi-processing legacy mode. + /// + UINT32 CmpLegacy:1; + /// + /// [Bit 2] Secure Virtual Mode feature. + /// + UINT32 SVM:1; + /// + /// [Bit 3] Extended APIC register space. + /// + UINT32 ExtApicSpace:1; + /// + /// [Bit 4] LOCK MOV CR0 means MOV CR8. + /// + UINT32 AltMovCr8:1; + /// + /// [Bit 5] LZCNT instruction support. + /// + UINT32 LZCNT:1; + /// + /// [Bit 6] SSE4A instruction support. + /// + UINT32 SSE4A:1; + /// + /// [Bit 7] Misaligned SSE Mode. + /// + UINT32 MisAlignSse:1; + /// + /// [Bit 8] ThreeDNow Prefetch instructions. + /// + UINT32 PREFETCHW:1; + /// + /// [Bit 9] OS Visible Work-around support. + /// + UINT32 OSVW:1; + /// + /// [Bit 10] Instruction Based Sampling. + /// + UINT32 IBS:1; + /// + /// [Bit 11] Extended Operation Support. + /// + UINT32 XOP:1; + /// + /// [Bit 12] SKINIT and STGI support. + /// + UINT32 SKINIT:1; + /// + /// [Bit 13] Watchdog Timer support. + /// + UINT32 WDT:1; + /// + /// [Bit 14] Reserved. + /// + UINT32 Reserved1:1; + /// + /// [Bit 15] Lightweight Profiling support. + /// + UINT32 LWP:1; + /// + /// [Bit 16] 4-Operand FMA instruction support. + /// + UINT32 FMA4:1; + /// + /// [Bit 17] Translation Cache Extension. + /// + UINT32 TCE:1; + /// + /// [Bit 21:18] Reserved. + /// + UINT32 Reserved2:4; + /// + /// [Bit 22] Topology Extensions support. + /// + UINT32 TopologyExtensions:1; + /// + /// [Bit 23] Core Performance Counter Extensions. + /// + UINT32 PerfCtrExtCore:1; + /// + /// [Bit 25:24] Reserved. + /// + UINT32 Reserved3:2; + /// + /// [Bit 26] Data Breakpoint Extension. + /// + UINT32 DataBreakpointExtension:1; + /// + /// [Bit 27] Performance Time-Stamp Counter. + /// + UINT32 PerfTsc:1; + /// + /// [Bit 28] L3 Performance Counter Extensions. + /// + UINT32 PerfCtrExtL3:1; + /// + /// [Bit 29] MWAITX and MONITORX capability. + /// + UINT32 MwaitExtended:1; + /// + /// [Bit 31:30] Reserved. + /// + UINT32 Reserved4:2; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_ECX; + +/** + CPUID Extended Processor Signature and Features EDX for CPUID leaf + #CPUID_EXTENDED_CPU_SIG. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 0] x87 floating point unit on-chip. + /// + UINT32 FPU:1; + /// + /// [Bit 1] Virtual-mode enhancements. + /// + UINT32 VME:1; + /// + /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE. + /// + UINT32 DE:1; + /// + /// [Bit 3] Page-size extensions (4 MB pages). + /// + UINT32 PSE:1; + /// + /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD. + /// + UINT32 TSC:1; + /// + /// [Bit 5] MSRs, with RDMSR and WRMSR instructions. + /// + UINT32 MSR:1; + /// + /// [Bit 6] Physical-address extensions (PAE). + /// + UINT32 PAE:1; + /// + /// [Bit 7] Machine check exception, CR4.MCE. + /// + UINT32 MCE:1; + /// + /// [Bit 8] CMPXCHG8B instruction. + /// + UINT32 CMPXCHG8B:1; + /// + /// [Bit 9] APIC exists and is enabled. + /// + UINT32 APIC:1; + /// + /// [Bit 10] Reserved. + /// + UINT32 Reserved1:1; + /// + /// [Bit 11] SYSCALL and SYSRET instructions. + /// + UINT32 SYSCALL_SYSRET:1; + /// + /// [Bit 12] Memory-type range registers. + /// + UINT32 MTRR:1; + /// + /// [Bit 13] Page global extension, CR4.PGE. + /// + UINT32 PGE:1; + /// + /// [Bit 14] Machine check architecture, MCG_CAP. + /// + UINT32 MCA:1; + /// + /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV. + /// + UINT32 CMOV:1; + /// + /// [Bit 16] Page attribute table. + /// + UINT32 PAT:1; + /// + /// [Bit 17] Page-size extensions. + /// + UINT32 PSE36 : 1; + /// + /// [Bit 19:18] Reserved. + /// + UINT32 Reserved2:2; + /// + /// [Bit 20] No-execute page protection. + /// + UINT32 NX:1; + /// + /// [Bit 21] Reserved. + /// + UINT32 Reserved3:1; + /// + /// [Bit 22] AMD Extensions to MMX instructions. + /// + UINT32 MmxExt:1; + /// + /// [Bit 23] MMX instructions. + /// + UINT32 MMX:1; + /// + /// [Bit 24] FXSAVE and FXRSTOR instructions. + /// + UINT32 FFSR:1; + /// + /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations. + /// + UINT32 FFXSR:1; + /// + /// [Bit 26] 1-GByte large page support. + /// + UINT32 Page1GB:1; + /// + /// [Bit 27] RDTSCP intructions. + /// + UINT32 RDTSCP:1; + /// + /// [Bit 28] Reserved. + /// + UINT32 Reserved4:1; + /// + /// [Bit 29] Long Mode. + /// + UINT32 LM:1; + /// + /// [Bit 30] 3DNow! instructions. + /// + UINT32 ThreeDNow:1; + /// + /// [Bit 31] AMD Extensions to 3DNow! instructions. + /// + UINT32 ThreeDNowExt:1; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_EXTENDED_CPU_SIG_EDX; + + +/** +CPUID Linear Physical Address Size + +@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) + +@retval EAX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX. +@retval EBX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX. +@retval ECX Linear/Physical Address Size described by the type + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX. +@retval EDX Reserved. +**/ + +/** + CPUID Linear Physical Address Size EAX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Maximum physical byte address size in bits. + /// + UINT32 PhysicalAddressBits:8; + /// + /// [Bits 15:8] Maximum linear byte address size in bits. + /// + UINT32 LinearAddressBits:8; + /// + /// [Bits 23:16] Maximum guest physical byte address size in bits. + /// + UINT32 GuestPhysAddrSize:8; + /// + /// [Bit 31:24] Reserved. + /// + UINT32 Reserved:8; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX; + +/** + CPUID Linear Physical Address Size EBX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 0] Clear Zero Instruction. + /// + UINT32 CLZERO:1; + /// + /// [Bits 1] Instructions retired count support. + /// + UINT32 IRPerf:1; + /// + /// [Bits 2] Restore error pointers for XSave instructions. + /// + UINT32 XSaveErPtr:1; + /// + /// [Bit 31:3] Reserved. + /// + UINT32 Reserved:29; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX; + +/** + CPUID Linear Physical Address Size ECX for CPUID leaf + #CPUID_VIR_PHY_ADDRESS_SIZE. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Number of threads - 1. + /// + UINT32 NC:8; + /// + /// [Bit 11:8] Reserved. + /// + UINT32 Reserved1:4; + /// + /// [Bits 15:12] APIC ID size. + /// + UINT32 ApicIdCoreIdSize:4; + /// + /// [Bits 17:16] Performance time-stamp counter size. + /// + UINT32 PerfTscSize:2; + /// + /// [Bit 31:18] Reserved. + /// + UINT32 Reserved2:14; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX; + + +/** + CPUID AMD Processor Topology + + @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E) + + @retval EAX Extended APIC ID described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EAX. + @retval EBX Core Indentifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX. + @retval ECX Node Indentifiers described by the type + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX. + @retval EDX Reserved. +**/ +#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E + +/** + CPUID AMD Processor Topology EAX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bit 31:0] Extended APIC Id. + /// + UINT32 ExtendedApicId; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX; + +/** + CPUID AMD Processor Topology EBX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Core Id. + /// + UINT32 CoreId:8; + /// + /// [Bits 15:8] Threads per core. + /// + UINT32 ThreadsPerCore:8; + /// + /// [Bit 31:16] Reserved. + /// + UINT32 Reserved:16; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX; + +/** + CPUID AMD Processor Topology ECX for CPUID leaf + #CPUID_AMD_PROCESSOR_TOPOLOGY. +**/ +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 7:0] Node Id. + /// + UINT32 NodeId:8; + /// + /// [Bits 10:8] Nodes per processor. + /// + UINT32 NodesPerProcessor:3; + /// + /// [Bit 31:11] Reserved. + /// + UINT32 Reserved:21; + } Bits; + /// + /// All bit fields as a 32-bit value + /// + UINT32 Uint32; +} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX; + + +/** + CPUID Memory Encryption Information =20 @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F) =20 @@ -33,8 +613,8 @@ @retval EBX If memory encryption feature is present then return the page table bit number used to enable memory encryption= support and reducing of physical address space in bits. - @retval ECX Returns number of encrypted guest supported simultaneosuly. - @retval EDX Returns minimum SEV enabled and SEV disbled ASID.. + @retval ECX Returns number of encrypted guest supported simultaneously. + @retval EDX Returns minimum SEV enabled and SEV disabled ASID. =20 Example usage @code @@ -79,7 +659,7 @@ typedef union { UINT32 SevEsBit:1; =20 /// - /// [Bit 4:31] Reserved + /// [Bit 31:4] Reserved /// UINT32 ReservedBits:28; } Bits; @@ -99,17 +679,18 @@ typedef union { /// struct { /// - /// [Bit 0:5] Page table bit number used to enable memory encryption + /// [Bit 5:0] Page table bit number used to enable memory encryption /// UINT32 PtePosBits:6; =20 /// - /// [Bit 6:11] Reduction of system physical address space bits when me= mory encryption is enabled + /// [Bit 11:6] Reduction of system physical address space bits when + /// memory encryption is enabled /// UINT32 ReducedPhysBits:5; =20 /// - /// [Bit 12:31] Reserved + /// [Bit 31:12] Reserved /// UINT32 ReservedBits:21; } Bits; @@ -129,7 +710,7 @@ typedef union { /// struct { /// - /// [Bit 0:31] Number of encrypted guest supported simultaneously + /// [Bit 31:0] Number of encrypted guest supported simultaneously /// UINT32 NumGuests; } Bits; @@ -149,7 +730,7 @@ typedef union { /// struct { /// - /// [Bit 0:31] Minimum SEV enabled, SEV-ES disabled ASID + /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID /// UINT32 MinAsid; } Bits; --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Fri May 3 04:54:32 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; dkim=fail spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1497653840390132.40308755403657; Fri, 16 Jun 2017 15:57:20 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2098321A07A98; Fri, 16 Jun 2017 15:55:57 -0700 (PDT) Received: from NAM01-BY2-obe.outbound.protection.outlook.com (mail-by2nam01on0042.outbound.protection.outlook.com [104.47.34.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4BE1C21A07A98 for ; Fri, 16 Jun 2017 15:55:54 -0700 (PDT) Received: from leduran-Precision-WorkStation-T5400.amd.com (165.204.78.1) by DM5PR12MB1244.namprd12.prod.outlook.com (10.168.237.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1178.14; Fri, 16 Jun 2017 22:57:11 +0000 X-Original-To: edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=HoIOAyfHZglsyjrD/BhdDbyMU1a7n1EMAkwXfueBPBY=; b=oAy//5dHcoHebuXGzWCCf1Id94DrxeB/OEZfY1muBdT6Zet6c8XBlupQ9nPrJpjKC8tHn2kWr8BXDQ2hUr9uMRuUuL0a/YNltIFHhcU8d++mY3Q1UIdQesnSY9zyUkWdjfZa5qMOIfKbeyXTvzEE/f84hsJaR7VrUnPXZiUQrTc= Authentication-Results: lists.01.org; dkim=none (message not signed) header.d=none;lists.01.org; dmarc=none action=none header.from=amd.com; From: Leo Duran To: edk2-devel@lists.01.org Date: Fri, 16 Jun 2017 17:57:00 -0500 Message-Id: <1497653820-15192-3-git-send-email-leo.duran@amd.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1497653820-15192-1-git-send-email-leo.duran@amd.com> References: <1497653820-15192-1-git-send-email-leo.duran@amd.com> MIME-Version: 1.0 X-Originating-IP: [165.204.78.1] X-ClientProxiedBy: MWHPR1701CA0003.namprd17.prod.outlook.com (10.172.58.13) To DM5PR12MB1244.namprd12.prod.outlook.com (10.168.237.135) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 015f7af9-9694-4546-c476-08d4b50b0655 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(48565401081)(201703131423075)(201703031133081); SRVR:DM5PR12MB1244; X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 3:LnfG7bRXl/DTuzOF81uc+xqOHxkhRoQCvOoALkSvUX4HNDcGL4SgCThCmv/CEVxS7U3dWzMSpyAHZo62E62qpMArRhNZfuIBWCpPmpCc2M1QNt9cAVu7y3H6441sFOjTTQTX2/b2k2HSJ1Qqp33VNobwn3PFpttVVkbIaqqAiYwJVWjd0W6QaIocSrOCUvuRZI3b5fFexknJQ7Letpeq6OSJ0EeWd8whptBkIOIJI2y8oBgn/pjAGpcXQvT59r7aBWjVak7hSjj4bmJp/1uanIWOq6iy02aNfNToWixv2tXppWg1BerInTzTCP5ECZLTFYgRxNgjlxHZUrK/Wg8f+RaENUAfvPVMlUf0rzUxijI=; 25:QjEL7aLrdvUKztyXBzndHQKPgrBpPLBtxoroEnfVEEnaE/rkXnufdixlw2tBtomiBqQFhc8vEAkmWisUSFc2jmoQ0RnqS8NLlUK2B0wa/a8YPbk+nIQErQfIg3NFHLV8EL6bYlXcsL6oimSzQBPa62DGdWGfu+cdiHIOLLLJOJxkwyCj2mK4JoUhkzqzsE1Pr9vWPBoNV4tpdSIF5iGbZperyBR82GTqoyTvAj9WBscBQZJ8hTMndFrs6SgwLRUj+TlHwxfwWwqXKCQZPm9OdZY2fWde4hzuY2fCcPS3NI8ETcR4JD1aQdm0/ipTFhp5iX3lt0eC9vv4INpXXWZFCisaXjThh4XNuwemvGE8LAkNSMKp0s45TxNnybNIbTTsTqeWnjEH0T/RJhjDwQMRu6dtDQHJ4in0+fFksAu4tZ3KGKeXxbxhfiIVt1lCNP3jVL7XBWVDa2g/afFA/51vpi2n32xFCiDUFHC2WrLkyig= X-MS-TrafficTypeDiagnostic: DM5PR12MB1244: X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 31:LxrnkIkyi+VJFMJYY1Aa8OHo3Gr2Xe5oMJc0cex1hJdqNWPeckZEsoI8+ABW+Rm2tSBalddLWkke4vXe0F5YK5uZk3It+C4Kh8fZ8q7GBMbqH8HhtHXnS7UNI8zwTLZUfb3Ln8ykLt8FyGrJy8nPzag/2YBEUms5Fj6eAfPlHackV48waPaVE3pLGbCSmI+Ch8fzgxsL81SArKD9ujtkzURX+kj/SDYwsdLvrkNsF3Y=; 20:SiFw2GEZfaTMPbGuJiMSoNvk79Z+eDbHA3dAY2fk5KCNxWzJLeV1BgPYGI/DEQ3nnRhaIIQ6+eMGPRIh+DVkxEztqkTP4CtAIRvkS/isACtxRcepSkqOlhS3Wl8F6Ao/Q0NDjb78woyCo3SdNV5//LNjA6XULcjq1eOgsx+NjPo2AoBs0Y8UCtcblGSo0rNxASqMjpnBFYn/fvuJah5TrejDLzWLJnmAAK4cHWw0DDmMudJBpL0kqgTFRwqO20aDBg1XIjLBYfYjDRSuphQxIINljdovBoq6182QlS7NEeWuKUltWor/HwD9aVz9XHx8Ypnf0aMb3EvBCoZabKyvTSQq6PzxQdNV+gRTdMx5V+edwjQfp+QZ5FS6zQymA+FWs1UD4/fuV72pdF+CWzk82WYNL1LRHBLmXNaWCyPeB0lT8p5Pwf+HzwIEk/F3zaSRPiK3tn1THNeqiwT8BSdMPvpDMhcz7WUyMUx/mh1hAUaxdBB/nmJcL7M9Xa9gg41h X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(767451399110)(228905959029699); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(93006095)(93001095)(3002001)(100000703101)(100105400095)(10201501046)(6055026)(6041248)(20161123558100)(20161123555025)(20161123564025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123560025)(6072148)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:DM5PR12MB1244; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:DM5PR12MB1244; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR12MB1244; 4:yOp75uVhnRkgu9GmP1qcDEAWGfNzcnXgVFXHaaMsRr?= =?us-ascii?Q?iZdqBYERsfnvKIKR7qzoJyokfhtoV2OT7tn2+JSCIj8f6MyckmzsK8X0m2Vr?= =?us-ascii?Q?d8QUjzUa2Xo7RvEuHLvUika9VXgvpGos1mfQuPaenn/jXa5BHMLRx+ZpyEK3?= =?us-ascii?Q?g+Tb396wAaigvIKAmr8hhwLY2lUlDrNEy/AyJkWsAHgoSs4y4Nua7C3fEYLw?= =?us-ascii?Q?17NgIomWVippWVls9EXpF7eWWSYKWYpyVdk46Y5C2RwPzu9cExvYFsQrIHI4?= =?us-ascii?Q?L2AIu1x26yb5yWoV9ZKolCfcmawM6G3nm1Bh+g+jGmgxepRoKz+yFh1XUxm1?= =?us-ascii?Q?KqXG9FGA//qXy+ofmZZBUXCCqZgmBarnJgR6cLtTf7ivTnYcA10ak8TVnNqH?= =?us-ascii?Q?EMC3CEsRQQdR1pL7x29TxL7wy4a340JQu5AhF3jtEUkbc8mcBY3JTEzxPLeg?= =?us-ascii?Q?ojtknTaJ4lflcREjXU73qjxCFji3CwJdsqO4XyMV1l1Op0WGDHEp5FyiqVMR?= =?us-ascii?Q?fRl0d+DdPI99rB5YUrmrBB/571BSLdCQVEr288HmMbXat8hhoCkL44ecGw1u?= =?us-ascii?Q?FpBR+Kw4eGYRB+VUmxwNDTkhHYvGO+a60i+vyaRI6mHY8ZFcTX9p69bgFDer?= =?us-ascii?Q?GnYD/K/bUqKiStuH2PkcWAzRWnypqmebYd8gkEphqKKHnE5O9Z1aQzVIJaR6?= =?us-ascii?Q?qIs2jw2SmpJfm1b0XlNRYZ33KLUEXz1QgPPWCltO0Y1faa4bTgrY8dvpyDhj?= =?us-ascii?Q?zVP9riSVZKz5uIAZ4FDeUu6xMfTap0sbFDkj3JWbxdmfGJT/Y3gxa5XzfzfW?= =?us-ascii?Q?5o7Slai4Zpb9XmXUqramPGujWgdlAE1NlxI9e0VHZieOTeCPftll5Yhfrl9F?= =?us-ascii?Q?m2ixg2sCNvZO/MNsJj2v/97bJOsY7xKC8ovKqD5+13OdR4HEc4yoRmBDseGk?= =?us-ascii?Q?N2TCzabaW00Ctsr10Gnk1sDPWgR0m+FIOg6c/Fhl3eXCyBpAr1IbT/tIWEHu?= =?us-ascii?Q?ilw0lzPInvlrkqgYESehfh2Yoa8WYRNQsPHxJgJPzPA2cX5qjHVxgcuWinO6?= =?us-ascii?Q?L2ei7q38R2tTXHTFIp+/XS7WXZIuDPQTwVsWOUEeIgCUvKaVtW+u6VhLjErq?= =?us-ascii?Q?KXE/1ngVj9iZdV6MUebT56bZ62XpSpdnR8xurhnE5mIZ765puAUr9rRaSQUe?= =?us-ascii?Q?VNMMLX2CiEZAHKgPKbGfqFBx+tWTKKrylsDF8R9oqzjKYNL0iq08jTFA=3D?= =?us-ascii?Q?=3D?= X-Forefront-PRVS: 0340850FCD X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4630300001)(6009001)(39850400002)(39840400002)(39860400002)(39400400002)(39410400002)(39450400003)(110136004)(2906002)(5660300001)(38730400002)(8676002)(5003940100001)(25786009)(53936002)(33646002)(81166006)(4326008)(54906002)(86362001)(36756003)(6486002)(6116002)(2351001)(3846002)(47776003)(48376002)(66066001)(50466002)(50226002)(42186005)(478600001)(189998001)(53416004)(6916009)(6666003)(50986999)(2950100002)(2361001)(7736002)(305945005)(76176999)(19627235001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1244; H:leduran-Precision-WorkStation-T5400.amd.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR12MB1244; 23:xh3cqRMoPY9p7OMmvcyURbRyrbNgm7Ue9AH0eIkFN?= =?us-ascii?Q?eaFCt1WUOMH2xZ2Sgn0l4jNyD/iGcqXzWIOj4sjOmbZK7uNUWHf0+nebpyP1?= =?us-ascii?Q?Sn0/FPdDPJGI5TFyYR/izC2+SNn4i9pHqL26Vsza5dBknxDDckj9ubQHUm9X?= =?us-ascii?Q?YkuF0WOK+g+x/nrfFxHtciSpdhdTp790UkV8O6l+VsPkFtuXIKad2X8za3rx?= =?us-ascii?Q?UMP8HprKsH6Qx7sQ0mOOFWXcCJVwT6DfG/TL83O7pY32AtzBY7xsuUc7Yv1q?= =?us-ascii?Q?uleyKlgIp7TrKCyU3M/lbDZ1OFYoYM3yoKaNrIhPajmDvCpjJhs2uSs+GXSV?= =?us-ascii?Q?sC+07GcK/fjmlWKo1mPLT4mFtzywcPNfqPOUUMDS4ZOQQrrLFBr59JiZQ7qZ?= =?us-ascii?Q?9zQj+tO0W/sxU7s1KwLafehbaPrhNReWEdM1ZNkqOZ2A8sQddDV70lu8Oa/3?= =?us-ascii?Q?k0xT7mg63oTgkG/kD77rJa7ityg2HmCZSpbMR3u+/kKsfH/B8ww49zpyeOxd?= =?us-ascii?Q?4fMfJiPB0O+QV5YYDkDPG6lg+sJ9ZTouDY7hNzoLKcmxIJSEZhyMTgCz5qfY?= =?us-ascii?Q?lUZUYXh94pi7jNHMttuWymPyrK6aglBInHw7k6ScXJXUyA97dOLta9r+9kRL?= =?us-ascii?Q?nnL9+23npGR2hVdenTYTsnd+D16YcWKX6druvGdceaqBJ/Q6qu25fS1RLakt?= =?us-ascii?Q?NHhdtFCXeuwD0eKpLKTaSkSNjtofVfWQfPyZggkLM3zv4WJ1JBhyuQscFI03?= =?us-ascii?Q?jGgtSd6I4CK/tIIAvTC7HvPsFn+CTOQ1EIF9NnLDNnzQLqsWOvxh9JQXuzvq?= =?us-ascii?Q?5hLl3GYiroIfsVYtDryYaTdbj+YoxtUCuW4nHRLuey6YRMKO1NXcJdKZU5JT?= =?us-ascii?Q?hdmTp7Z5+Xv4IJc/MXK5FGsmnsw2MFp+637Frht4TNTNY02qC6lsW9s7lSLJ?= =?us-ascii?Q?7duZH4NjvmQvFsAkLA6WPfjoFaD2OY5oVKfeV43b2jKU+ZXaawLEWfCW8rHo?= =?us-ascii?Q?ZgbSTOci31WSxlSmDj+iklXLRG8sjNwhBDegX1Ere5VMwup3EtZNptmLeev3?= =?us-ascii?Q?ejCIt+gyzRHbly9i71Y641l45xRfOxYHOanxOU+qupQmJ9gQEW6cx3Je4kvI?= =?us-ascii?Q?e3qn+wcV4g=3D?= X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR12MB1244; 6:U4PPfAC/vIifeZZcPo+nYHOagsFolH4/mWLPsy6Amj?= =?us-ascii?Q?11VYddbpjrXYGOl7OImatMXq1+alrzzZs61jyzxVePtUrzqSz0bdoPMOG+5u?= =?us-ascii?Q?EQO04I0TwWo45Dwma05Wh9fw3scLPMDkl3QLatYwhweXzPJ8uaSqOxm0iC3O?= =?us-ascii?Q?04ns36AVU9O6n8tztt0JgiD7jpc6KvPhEtD2J+EAAfZ13ZkN7qoK43RTak4p?= =?us-ascii?Q?lsA+DTJ38reEkTKyoS8/iw5AjVUYbPl7ebH2eiXGaKxiRQHvigCbA2qYAVxV?= =?us-ascii?Q?oHXS4U/VGGqZlMH42OhTwCO+pusaER3RhYQVzQcVPdr+RMRxudU/NJ2HQNMG?= =?us-ascii?Q?3LXU0XdFmjGFXzR/qSuOveH46us08wQmlIA7GVF0Jjj2LoDcQbbZQY+STPbz?= =?us-ascii?Q?XH4YoHuzsJHEwdYaaCZtiGStadWJULhLhhYtmN1ys3wKDciZidcIvcNaiCVX?= =?us-ascii?Q?MHQqV5h4vJN2wglrQK7uYQgekgAnE4vWkjJ8o5/a6bRSsiRVXwBgXtV2dqIY?= =?us-ascii?Q?uvxbkFBTppkmKGJ7qCI6gCzrQ3pY1pdsN6ia+QQFOaSSk7xrVqISk1eq5yQA?= =?us-ascii?Q?pICcrnfcIoyWhw+Ug3bYTat04dhhI17RUQV7dtQqu9yGVFxmSsxMBgTP9L9I?= =?us-ascii?Q?SQy0A4dCC0ItE5euYO6/NAFf+0/fddnb5x2q2/lPEkL4kKBWDpAu0cprNbl+?= =?us-ascii?Q?rHzdVciQeWjEE+emfHZpdqcEkrbBQV+NNTyH98EXZ9SmL3HabagHN9rDNysm?= =?us-ascii?Q?Bpr7T5Qw1Hxx6wimKMJeedb35N2nR0ekB00vo8B6kTdYo0cu+VbLxdccQ4Eh?= =?us-ascii?Q?o13VHpgbsuTkiz9KRw07KbHafUNBbaGPK+D2uCanNSEJOcEyHjHxBKR8hIYu?= =?us-ascii?Q?WA5ZFpTA7DcoIN6I81HxPSQ80399/i/5Mk84gJSgNvtXpoIaSXcTQrVTYqlS?= =?us-ascii?Q?eV6wLjnlt0nQVZhgUis2Td78OQKbDeaWMxvzi3iFyI7VUflwnVYuJR9T00KJ?= =?us-ascii?Q?MCZmSt2skTJHy9ET6qVumn?= X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 5:uN03VGSohkJg3sTfrHnjI5XqPLDuT/SMmXltCy7NDOxwwHqUpHaq4rFTOMVBxsfSg1gR0E1uXPv4yqv16fq8RD7gdux2tTxPPpeyVUNlaS9yGh8PUaFCVw5evJXYGokw9VA4X8hCsvT7IWsiuRHkUVhH5X+h61E7mGlmT6MuH0ymDOiO/GA/Bw0gsY94k0Pmd/GcegJkr2hfP6jZCBuCoFdxtpXtvIH6aDJkMgqMF9piHX3YHJFG4BoZuMd1J9UMo/cQ1Kqt9J3tushW0L42fo8TkNwfSqbo5gsWJR1xS+6D08MscxVSoGtAjkLAkmBkARTLsl0MT34VUAZLhycilKNaKdYt9PrP4VKR/8WTYwjjI6egWLLnf3jdtC2XHyLvl8UN5KK4OsUoNmFYlJsKlwpH71J/EXUPS3ohY5/hDr+xVtpuu95QnaqYKBPEw/K5s19JMziaHXaxie4WnlAS3yoxIQqDgTN202qj3ku4UhIcF6mnJyPp5/br6UKFtNoX; 24:l2irvHp3n/i45P7bpNR5LqqJV0ypriwPh4bX/RhwWd1iAwjihvsRQ+ABIOzfzlcZ0m+VqcCkyYNvMBQkAsldmz2frq8SgDZeF5q5UxIG0J8= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 7:JOc5CnlKS3GL6OQbeyScYnTxgoaZ7JS9BTJyBQyqfEQIXmS04LD+ucalln9SsRzZxiJefuR8S1LNVMbf56rRzGeph3lNn9tMpHmpIo+PnhlQYqZEQBMD55m8C0+ScTYW5LeYPMt16KLCLdP+Z/iXO+SFkFiFshe1YZMqjvY6+5ccyAkLlFmx69GWM//vYbsfjx18RDorri/QrSJ9FakfH61exGC6qzGmd1qmpl4gbjL7zxREr+SmkTnaQtHVXkcXG2NLk5DjKILVY+br2rBcC9a9uQFvNp+uVXW3blXJngwW48VXaArxkMerpceQ8w3VGD180Et01zflNrE1RMlE2I9qfgWBR3RCQUtbfOuGRq0d68eimBvau0phWyX6fsxJ2xrJu/du9XzbsmZouN5eKKxeo/gjFzw1W9kjZhuKEHvCQspHWvTMNsdMdu4py64v9fIHnKqmSh1XGWtF3pEZP/jXcmHeg5Se8w/GRkcCOMHUI6lub+V6GyuLe0RC5v91BjIc/tNUwgdT4HKgSrOhTBnN6/Wo2bVpSPsrxtztEgLXioQjIhJ87QpAjWN0CWt1nEgjF9rE5VVr7L0nzpjgHOskrxRmfEggL+wiTTF1cSdq7xS8Q3HIAz9SStlKrR+rs5CgSarLa8yCzk+dOn5KdNX6h6GfRIFA6KqLry9uGh1PRH0s6qpPGmz4KoLk8QEQapBWAw2GSVXRB7P/+lRSuy08jEQ6ULGzdHGvT7L7eWY28rjhZrnoM8JM97CSqyVnCrw2YzMbtXNM4+r9/igavfd3dxaM7WHYj9x9/Wq/WMg= X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1244; 20:GJpy4JGcYTpH8Zny6XfoFQQxuHon9Kp5Zt352+ehCCupM5jugkMLEpxu7odrUDCCoveQwh3tWiokY9h08RrRs0paxtNoXtijRPiXxgydH+V3J27AhUv5b5s7TOzZH8vfqrevLjI6OrAtZ9F9K/XmhZpPAHW9JFIqUY68FTwlSOTZ20KTPJiWPu3Ae4nkyVFmCYzCM9zxXG5NViftC0b8sSlUnJtxzQKmbf4grCDQkgqEBwwv0AlmYH9S3qQ4OPvO X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2017 22:57:11.3353 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1244 Subject: [edk2] [PATCH v4 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jordan Justen , Leo Duran , Jeff Fan , Liming Gao Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Cc: Jordan Justen Cc: Jeff Fan Cc: Liming Gao Cc: Brijesh Singh Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 140 ++++++++++++++++-= ---- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 140 ++++++++++++++++-= ---- 2 files changed, 216 insertions(+), 64 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index f81bbb2..898d844 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -4,6 +4,8 @@ This local APIC library instance supports xAPIC mode only. =20 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Inc. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -15,6 +17,7 @@ **/ =20 #include +#include #include #include =20 @@ -966,20 +969,33 @@ GetProcessorLocationByApicId ( OUT UINT32 *Thread OPTIONAL ) { - BOOLEAN TopologyLeafSupported; - UINTN ThreadBits; - UINTN CoreBits; - CPUID_VERSION_INFO_EBX VersionInfoEbx; - CPUID_VERSION_INFO_EDX VersionInfoEdx; - CPUID_CACHE_PARAMS_EAX CacheParamsEax; - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; + BOOLEAN TopologyLeafSupported; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; + UINT32 SignatureEbx; + UINT32 SignatureEcx; + UINT32 SignatureEdx; + UINT32 MaxStandardCpuIdIndex; + UINT32 MaxExtendedCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + UINT32 MaxThreadPerPackageMask; + UINT32 ActualThreadPerPackageMask; + UINT32 MaxCoresPerNode; + UINT32 CorePerNodeMask; + UINT32 ApicIdShift; + UINTN ThreadBits; + UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. @@ -987,10 +1003,10 @@ GetProcessorLocationByApicId ( AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { - *Thread =3D 0; + *Thread =3D 0; } if (Core !=3D NULL) { - *Core =3D 0; + *Core =3D 0; } if (Package !=3D NULL) { *Package =3D 0; @@ -998,24 +1014,24 @@ GetProcessorLocationByApicId ( return; } =20 + // + // Assume three-level mapping of APIC ID: Package|Core|Thread. + // ThreadBits =3D 0; CoreBits =3D 0; =20 // - // Assume three-level mapping of APIC ID: Package:Core:SMT. + // Get max index of CPUID and vendor's signature // - TopologyLeafSupported =3D FALSE; - - // - // Get the max index of basic CPUID - // - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, &SignatureEbx, &Signat= ureEcx, &SignatureEdx); + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); =20 // // If the extended topology enumeration leaf is available, it // is the preferred mechanism for enumerating topology. // - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { + TopologyLeafSupported =3D FALSE; + if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { AsmCpuidEx( CPUID_EXTENDED_TOPOLOGY, 0, @@ -1065,27 +1081,87 @@ GetProcessorLocationByApicId ( } =20 if (!TopologyLeafSupported) { + // + // Get logical processor count + // AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL= , NULL); - MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; + + // + // Assume single-core processor + // + MaxCoresPerPackage =3D 1; + + // + // Check for topology extensions on AMD processor + // + if (SignatureEbx =3D=3D CPUID_SIGNATURE_GENUINE_AMD_EBX && + SignatureEcx =3D=3D CPUID_SIGNATURE_GENUINE_AMD_ECX && + SignatureEdx =3D=3D CPUID_SIGNATURE_GENUINE_AMD_EDX) { + if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx= .Uint32, NULL); + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopolo= gyEbx.Uint32, + &AmdProcessorTopologyEcx.Uint32, NULL); + // + // Get cores per processor package + // + MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / (AmdProces= sorTopologyEbx.Bits.ThreadsPerCore + 1); + + // + // Account for actual thread count (e.g., SMT disabled) + // + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddre= ssSizeEcx.Uint32, NULL); + MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.Ap= icIdCoreIdSize; + ActualThreadPerPackageMask =3D 1; + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage= ) { + ActualThreadPerPackageMask <<=3D 1; + } + + // + // Adjust APIC Id to report concatenation of Package|Core|Thread. + // + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { + MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopology= Ecx.Bits.NodesPerProcessor + 1); + + CorePerNodeMask =3D 1; + while (CorePerNodeMask < MaxCoresPerNode) { + CorePerNodeMask <<=3D 1; + } + CorePerNodeMask -=3D 1; + + ApicIdShift =3D 0; + do { + ApicIdShift +=3D 1; + ActualThreadPerPackageMask <<=3D 1; + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); + + InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicI= dShift) | (InitialApicId & CorePerNodeMask); + } + } + } } else { // - // Must be a single-core processor. + // Extract core count based on CACHE information // - MaxCoresPerPackage =3D 1; + if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NU= LL, NULL); + if (CacheParamsEax.Uint32 !=3D 0) { + MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIds= ForLogicalProcessors + 1; + } + } } =20 ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / Max= CoresPerPackage - 1) + 1); - CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + } =20 if (Thread !=3D NULL) { - *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); } if (Core !=3D NULL) { - *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); } if (Package !=3D NULL) { *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index e690d2a..9d3b82f 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -5,6 +5,8 @@ which have xAPIC and x2APIC modes. =20 Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Inc. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -16,6 +18,7 @@ **/ =20 #include +#include #include #include =20 @@ -1061,20 +1064,33 @@ GetProcessorLocationByApicId ( OUT UINT32 *Thread OPTIONAL ) { - BOOLEAN TopologyLeafSupported; - UINTN ThreadBits; - UINTN CoreBits; - CPUID_VERSION_INFO_EBX VersionInfoEbx; - CPUID_VERSION_INFO_EDX VersionInfoEdx; - CPUID_CACHE_PARAMS_EAX CacheParamsEax; - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; + BOOLEAN TopologyLeafSupported; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; + UINT32 SignatureEbx; + UINT32 SignatureEcx; + UINT32 SignatureEdx; + UINT32 MaxStandardCpuIdIndex; + UINT32 MaxExtendedCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + UINT32 MaxThreadPerPackageMask; + UINT32 ActualThreadPerPackageMask; + UINT32 MaxCoresPerNode; + UINT32 CorePerNodeMask; + UINT32 ApicIdShift; + UINTN ThreadBits; + UINTN CoreBits; =20 // // Check if the processor is capable of supporting more than one logical= processor. @@ -1082,10 +1098,10 @@ GetProcessorLocationByApicId ( AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { if (Thread !=3D NULL) { - *Thread =3D 0; + *Thread =3D 0; } if (Core !=3D NULL) { - *Core =3D 0; + *Core =3D 0; } if (Package !=3D NULL) { *Package =3D 0; @@ -1093,24 +1109,24 @@ GetProcessorLocationByApicId ( return; } =20 + // + // Assume three-level mapping of APIC ID: Package|Core|Thread. + // ThreadBits =3D 0; CoreBits =3D 0; =20 // - // Assume three-level mapping of APIC ID: Package:Core:SMT. + // Get max index of CPUID and vendor's signature // - TopologyLeafSupported =3D FALSE; - - // - // Get the max index of basic CPUID - // - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, &SignatureEbx, &Signat= ureEcx, &SignatureEdx); + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NU= LL); =20 // // If the extended topology enumeration leaf is available, it // is the preferred mechanism for enumerating topology. // - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { + TopologyLeafSupported =3D FALSE; + if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { AsmCpuidEx( CPUID_EXTENDED_TOPOLOGY, 0, @@ -1160,27 +1176,87 @@ GetProcessorLocationByApicId ( } =20 if (!TopologyLeafSupported) { + // + // Get logical processor count + // AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL); MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL= , NULL); - MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; + + // + // Assume single-core processor + // + MaxCoresPerPackage =3D 1; + + // + // Check for topology extensions on AMD processor + // + if (SignatureEbx =3D=3D CPUID_SIGNATURE_GENUINE_AMD_EBX && + SignatureEcx =3D=3D CPUID_SIGNATURE_GENUINE_AMD_ECX && + SignatureEdx =3D=3D CPUID_SIGNATURE_GENUINE_AMD_EDX) { + if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx= .Uint32, NULL); + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopolo= gyEbx.Uint32, + &AmdProcessorTopologyEcx.Uint32, NULL); + // + // Get cores per processor package + // + MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / (AmdProces= sorTopologyEbx.Bits.ThreadsPerCore + 1); + + // + // Account for actual thread count (e.g., SMT disabled) + // + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddre= ssSizeEcx.Uint32, NULL); + MaxThreadPerPackageMask =3D 1 << AmdVirPhyAddressSizeEcx.Bits.Ap= icIdCoreIdSize; + ActualThreadPerPackageMask =3D 1; + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage= ) { + ActualThreadPerPackageMask <<=3D 1; + } + + // + // Adjust APIC Id to report concatenation of Package|Core|Thread. + // + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { + MaxCoresPerNode =3D MaxCoresPerPackage / (AmdProcessorTopology= Ecx.Bits.NodesPerProcessor + 1); + + CorePerNodeMask =3D 1; + while (CorePerNodeMask < MaxCoresPerNode) { + CorePerNodeMask <<=3D 1; + } + CorePerNodeMask -=3D 1; + + ApicIdShift =3D 0; + do { + ApicIdShift +=3D 1; + ActualThreadPerPackageMask <<=3D 1; + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); + + InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicI= dShift) | (InitialApicId & CorePerNodeMask); + } + } + } } else { // - // Must be a single-core processor. + // Extract core count based on CACHE information // - MaxCoresPerPackage =3D 1; + if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NU= LL, NULL); + if (CacheParamsEax.Uint32 !=3D 0) { + MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIds= ForLogicalProcessors + 1; + } + } } =20 ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / Max= CoresPerPackage - 1) + 1); - CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + } =20 if (Thread !=3D NULL) { - *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); } if (Core !=3D NULL) { - *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); } if (Package !=3D NULL) { *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); --=20 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel