• Subject: [edk2] [PATCH v2] EmbeddedPkg/MmcDxe: Add non-DDR timing mode support
  • Author: Jun Nie
  • Date: June 12, 2017, 2:18 a.m.
  • Patches: 1 / 1
Changeset
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
Git apply log
Switched to a new branch '1497233885-11082-1-git-send-email-jun.nie@linaro.org'
Applying: EmbeddedPkg/MmcDxe: Add non-DDR timing mode support
Using index info to reconstruct a base tree...
error: patch failed: EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c:254
error: EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c: patch does not apply
Did you hand edit your patch?
It does not apply to blobs recorded in its index.
Cannot fall back to three-way merge.
Patch failed at 0001 EmbeddedPkg/MmcDxe: Add non-DDR timing mode support
The copy of the patch that failed is found in:
   /var/tmp/tmpwmnazq9b/.git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Failed to apply patch:
[edk2] [PATCH v2] EmbeddedPkg/MmcDxe: Add non-DDR timing mode support
[edk2] [PATCH v2] EmbeddedPkg/MmcDxe: Add non-DDR timing mode support
Posted by Jun Nie, 5 weeks ago
Only DDR mode is support for 8bit mode currently. Add
non-DDR case when configuring ECSD.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
 EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
index 574a77e..4ce0ddd 100644
--- a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
+++ b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
@@ -254,7 +254,7 @@ InitializeEmmcDevice (
   EFI_MMC_HOST_PROTOCOL *Host;
   EFI_STATUS Status = EFI_SUCCESS;
   ECSD       *ECSDData;
-  UINT32     BusClockFreq, Idx;
+  UINT32     BusClockFreq, Idx, BusMode;
   UINT32     TimingMode[4] = {EMMCHS52DDR1V2, EMMCHS52DDR1V8, EMMCHS52, EMMCHS26};
 
   Host  = MmcHostInstance->MmcHost;
@@ -286,7 +286,19 @@ InitializeEmmcDevice (
     }
     Status = Host->SetIos (Host, BusClockFreq, 8, TimingMode[Idx]);
     if (!EFI_ERROR (Status)) {
-      Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT);
+      switch (TimingMode[Idx]) {
+      case EMMCHS52DDR1V2:
+      case EMMCHS52DDR1V8:
+        BusMode = EMMC_BUS_WIDTH_DDR_8BIT;
+        break;
+      case EMMCHS52:
+      case EMMCHS26:
+        BusMode = EMMC_BUS_WIDTH_8BIT;
+        break;
+      default:
+        return EFI_UNSUPPORTED;
+      }
+      Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, BusMode);
       if (EFI_ERROR (Status)) {
         DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus width, Status:%r\n", Status));
       }
-- 
1.9.1

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Re: [edk2] [PATCH v2] EmbeddedPkg/MmcDxe: Add non-DDR timing mode support
Posted by Leif Lindholm, 5 weeks ago
(olivier.martin@arm.com has not been a valid email target for almost 2
years now, so no need to keep on cc.)

On Mon, Jun 12, 2017 at 10:18:05AM +0800, Jun Nie wrote:
> Only DDR mode is support for 8bit mode currently. Add
> non-DDR case when configuring ECSD.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jun Nie <jun.nie@linaro.org>

This looks good to me:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> ---
>  EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
> index 574a77e..4ce0ddd 100644
> --- a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
> +++ b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
> @@ -254,7 +254,7 @@ InitializeEmmcDevice (
>    EFI_MMC_HOST_PROTOCOL *Host;
>    EFI_STATUS Status = EFI_SUCCESS;
>    ECSD       *ECSDData;
> -  UINT32     BusClockFreq, Idx;
> +  UINT32     BusClockFreq, Idx, BusMode;
>    UINT32     TimingMode[4] = {EMMCHS52DDR1V2, EMMCHS52DDR1V8, EMMCHS52, EMMCHS26};
>  
>    Host  = MmcHostInstance->MmcHost;
> @@ -286,7 +286,19 @@ InitializeEmmcDevice (
>      }
>      Status = Host->SetIos (Host, BusClockFreq, 8, TimingMode[Idx]);
>      if (!EFI_ERROR (Status)) {
> -      Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT);
> +      switch (TimingMode[Idx]) {
> +      case EMMCHS52DDR1V2:
> +      case EMMCHS52DDR1V8:
> +        BusMode = EMMC_BUS_WIDTH_DDR_8BIT;
> +        break;
> +      case EMMCHS52:
> +      case EMMCHS26:
> +        BusMode = EMMC_BUS_WIDTH_8BIT;
> +        break;
> +      default:
> +        return EFI_UNSUPPORTED;
> +      }
> +      Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, BusMode);
>        if (EFI_ERROR (Status)) {
>          DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus width, Status:%r\n", Status));
>        }
> -- 
> 1.9.1
> 
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