From nobody Mon Apr 29 08:46:44 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Authentication-Results: mx.zoho.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1495556179593456.8288170793252; Tue, 23 May 2017 09:16:19 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8369C21A09104; Tue, 23 May 2017 09:16:15 -0700 (PDT) Received: from mx0a-0014ca01.pphosted.com (mx0a-0014ca01.pphosted.com [208.84.65.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BC28C21A09104 for ; Tue, 23 May 2017 09:16:13 -0700 (PDT) Received: from pps.filterd (m0042385.ppops.net [127.0.0.1]) by mx0a-0014ca01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4NGFaBi009869; Tue, 23 May 2017 09:16:12 -0700 Received: from mx-sanjose.cadence.com (mx-sanjose.Cadence.COM [158.140.2.60]) by mx0a-0014ca01.pphosted.com with ESMTP id 2amrep0058-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 23 May 2017 09:16:12 -0700 Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose.cadence.com (8.14.4/8.14.4) with ESMTP id v4NGFFsk005835 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=FAIL); Tue, 23 May 2017 09:15:16 -0700 (PDT) Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Tue, 23 May 2017 18:16:04 +0200 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Tue, 23 May 2017 18:16:03 +0200 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v4NGG2A8007492; Tue, 23 May 2017 17:16:02 +0100 Received: (from stelford@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v4NGG1fn007482; Tue, 23 May 2017 17:16:01 +0100 X-Original-To: edk2-devel@ml01.01.org X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com From: Scott Telford To: , , Date: Tue, 23 May 2017 17:15:47 +0100 Message-ID: <1495556147-6883-1-git-send-email-stelford@cadence.com> X-Mailer: git-send-email 2.2.2 MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-Received: by mx-sanjose.cadence.com as v4NGFFsk005835 at Tue May 23 09:15:16 2017 Subject: [edk2] [PATCH] Copy bus scanning workaround from ARM Juno PCIe driver. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Copy workaround previously in ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciRootBridge.c:PciRbPci= Read() to RootBridgeIoPciAccess(), to avoid spurious multiple detections when scanning buses. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Scott Telford --- MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c b/MdeM= odulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c index a0e7e5b..3cca3c1 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c @@ -945,6 +945,19 @@ RootBridgeIoPciAccess ( PciAddress.ExtendedRegister =3D PciAddress.Register; } =20 + // The UEFI PCI enumerator scans for devices at all possible addresses, + // and ignores some PCI rules - this results in some hardware being + // detected multiple times. We work around this by faking absent + // devices + if ((PciAddress.Bus =3D=3D 0) && ((PciAddress.Device !=3D 0) || (PciAddr= ess.Function !=3D 0))) { + *((UINT32 *)Buffer) =3D 0xffffffff; + return EFI_SUCCESS; + } + if ((PciAddress.Bus =3D=3D 1) && ((PciAddress.Device !=3D 0) || (PciAddr= ess.Function !=3D 0))) { + *((UINT32 *)Buffer) =3D 0xffffffff; + return EFI_SUCCESS; + } + Address =3D PCI_SEGMENT_LIB_ADDRESS ( RootBridge->RootBridgeIo.SegmentNumber, PciAddress.Bus, --=20 2.2.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel