From nobody Tue May 14 03:34:28 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+112802+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112802+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1703143004; cv=none; d=zohomail.com; s=zohoarc; b=JceuBRQPK4v2wCmOOJytbBxciN3HveEyaFYmxOV98PEB/Y1VdnUW/hlk8Gpjx7yM5V9u3if5keZ90GHLdE3WKYc4+Yzno4atE6BbSZ3jY9B8EV5Z7am3tUlih0thOjsVOHl54ZyvDa1aCvQAOB0KDRcfIZHaCPH2A94RCZIahkY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1703143004; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=JRlBu0HW2Md0zcvZ1NxLM8pTaVd8z1N7OZvAuY7pj88=; b=hEUHEo+1Dgc2uZXkA3yW00aDs/fHMYdnKonGWuWAlFoG2uWAZyL7fBBc1o/7OTf06b3BlMBpdZcbo5R2EXZBvHLjFDvcARbdppqzH+NQ/e4LEiGGO174phZI0vmZyhKSfgHooHMOrK7RBVBWFoHw8lmrsZEyqRSyMTAoGxYc40k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+112802+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1703143004951684.2636231048847; Wed, 20 Dec 2023 23:16:44 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=YFj8d4M2lDoDvfTjyGue2p0KEWriB1/OiWdD5Tt0hoE=; c=relaxed/simple; d=groups.io; h=From:To:Cc:References:In-Reply-To:Subject:Date:Message-ID:MIME-Version:Thread-Index:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Language; s=20140610; t=1703143004; v=1; b=etcpTBJyLIG5ZFqDRxd6F6yEPfzeGWFDIuxhczxJqRaieGhbO3VHYBB/HDoN0CIPq19S+ye0 oVfCVLNMQ1zheLM9MFixClcxa5CRCxkoHpGe9/iLu31CZPw5Eq/d74mw4ZOVLtJ3Xk66sINzwyh lXjKax1dbl7BF5KUtW4ZU/Js= X-Received: by 127.0.0.2 with SMTP id HbsiYY1788612x0yPnsBsIQq; Wed, 20 Dec 2023 23:16:44 -0800 X-Received: from cxsh.intel-email.com (cxsh.intel-email.com [121.46.250.151]) by mx.groups.io with SMTP id smtpd.web10.46895.1703143000108637461 for ; Wed, 20 Dec 2023 23:16:43 -0800 X-Received: from cxsh.intel-email.com (localhost [127.0.0.1]) by cxsh.intel-email.com (Postfix) with ESMTP id 38BB3DDA79E for ; Thu, 21 Dec 2023 15:16:38 +0800 (CST) X-Received: from localhost (localhost [127.0.0.1]) by cxsh.intel-email.com (Postfix) with ESMTP id 338A9DDA785 for ; Thu, 21 Dec 2023 15:16:38 +0800 (CST) X-Received: from mail.byosoft.com.cn (mail.byosoft.com.cn [58.240.74.242]) by cxsh.intel-email.com (Postfix) with SMTP id 41429DDA798 for ; Thu, 21 Dec 2023 15:16:34 +0800 (CST) X-Received: from DESKTOPS6D0PVI ([36.98.24.140]) (envelope-sender ) by 192.168.6.13 with ESMTP(SSL) for ; Thu, 21 Dec 2023 15:16:31 +0800 X-WM-Sender: gaoliming@byosoft.com.cn X-Originating-IP: 36.98.24.140 X-WM-AuthFlag: YES X-WM-AuthUser: gaoliming@byosoft.com.cn From: "gaoliming via groups.io" To: "'Chao Li'" , , "'Michael D Kinney'" Cc: "'Zhiguang Liu'" , "'Laszlo Ersek'" References: <20231212130932.2467028-1-lichao@loongson.cn> <17A017B459AD36A8.31409@groups.io> <00f401da327c$4c735010$e559f030$@byosoft.com.cn> <515091b3-35d9-44b0-befe-a2874f56ba75@loongson.cn> In-Reply-To: <515091b3-35d9-44b0-befe-a2874f56ba75@loongson.cn> Subject: =?UTF-8?B?5Zue5aSNOiDlm57lpI06IFtlZGsyLWRldmVsXSBbUEFUQ0ggdjQgMDkvMzddIE1kZVBrZzogQWRkIGEgbmV3IGxpYnJhcnkgbmFtZWQgUGVpU2VydmljZXNUYWJsZVBvaW50ZXJMaWJLczA=?= Date: Thu, 21 Dec 2023 15:16:31 +0800 Message-ID: <00a801da33dd$a06ba890$e142f9b0$@byosoft.com.cn> MIME-Version: 1.0 Thread-Index: AQCEYG8EQWgyRBqnKjP2eTsQI6iJCAOQYeSQAxrmPF8CW8FPCQH3s99HswcBxMA= Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gaoliming@byosoft.com.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: mNaY29O14DxUeFHaaXicAG1mx1787277AA= Content-Type: multipart/alternative; boundary="----=_NextPart_000_00A9_01DA3420.AE921CE0" Content-Language: zh-cn X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1703143006494100003 ------=_NextPart_000_00A9_01DA3420.AE921CE0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Chao: For the changes in MdePkg, I have two comments here.=20 =20 1) DebugSupport.h definition is from UEFI spec. Current definitions ma= tch the latest spec UEFI2.10. And, current definitions follow the same styl= e to other archs.=20 2) CpuLib.h. The patch removes #if defined (MDE_CPU_IA32) || defined (= MDE_CPU_X64), then these APIs are exposed for all archs, but ARM and RISCV = don=E2=80=99t support them. So, I suggest to update it as below. =20 =20 #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) =3D=3D> #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) || defined (MDE_CPU_LOO= NGARCH64)=20 =20 Thanks Liming =E5=8F=91=E4=BB=B6=E4=BA=BA: Chao Li =20 =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2023=E5=B9=B412=E6=9C=8820=E6=97=A5 9= :21 =E6=94=B6=E4=BB=B6=E4=BA=BA: gaoliming ; devel@ed= k2.groups.io; 'Michael D Kinney' =E6=8A=84=E9=80=81: 'Zhiguang Liu' ; 'Laszlo Ersek'= =E4=B8=BB=E9=A2=98: Re: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v4 09/37] M= dePkg: Add a new library named PeiServicesTablePointerLibKs0 =20 Hi Liming, Yes, the code branch is in my private repo, here is the link: https://githu= b.com/kilaterlee/edk2/tree/push1102 =20 Thanks, Chao On 2023/12/19 21:07, gaoliming wrote: Chao: Is there a branch or pull request for this patch set? I would like to chec= k how this new library instance be used. =20 Thanks Liming =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io =E4=BB=A3=E8=A1= =A8 Chao Li =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2023=E5=B9=B412=E6=9C=8819=E6=97=A5 2= 1:01 =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io ; Michael D Kinney ; Liming Gao =E6=8A=84=E9=80=81: Zhiguang Liu ; Laszlo Ersek =E4=B8=BB=E9=A2=98: Re: [edk2-devel] [PATCH v4 09/37] MdePkg: Add a new lib= rary named PeiServicesTablePointerLibKs0 =20 Hi Mike and Liming, Can you please review this patch? Thank you!=20 =20 Thanks, Chao On 2023/12/12 21:11, Chao Li wrote: Adding PeiServicesTablePointerLibKs0 for LoongArch64, which provides setting and getting the PEI service table pointer through the CSR KS0 register. =20 The idea of this library is derived from ArmPkg/Library/PeiServicesTablePointerLib/ =20 BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4584 =20 Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Laszlo Ersek Signed-off-by: Chao Li --- .../Library/PeiServicesTablePointerLib.h | 9 +- .../PeiServicesTablePointer.c | 87 +++++++++++++++++++ .../PeiServicesTablePointerLibKs0.inf | 37 ++++++++ .../PeiServicesTablePointerLibKs0.uni | 20 +++++ MdePkg/MdePkg.dsc | 3 + 5 files changed, 152 insertions(+), 4 deletions(-) create mode 100644 MdePkg/Library/PeiServicesTablePointerLibKs0/PeiService= sTablePointer.c create mode 100644 MdePkg/Library/PeiServicesTablePointerLibKs0/PeiService= sTablePointerLibKs0.inf create mode 100644 MdePkg/Library/PeiServicesTablePointerLibKs0/PeiService= sTablePointerLibKs0.uni =20 diff --git a/MdePkg/Include/Library/PeiServicesTablePointerLib.h b/MdePkg/I= nclude/Library/PeiServicesTablePointerLib.h index 61635eff00..f85c38363c 100644 --- a/MdePkg/Include/Library/PeiServicesTablePointerLib.h +++ b/MdePkg/Include/Library/PeiServicesTablePointerLib.h @@ -52,10 +52,11 @@ SetPeiServicesTablePointer ( immediately preceding the Interrupt Descriptor Table (IDT) in memory. For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes immediately preceding the Interrupt Descriptor Table (IDT) in memory. - For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in - a dedicated CPU register. This means that there is no memory storage - associated with storing the PEI Services Table pointer, so no additional - migration actions are required for Itanium or ARM CPUs. + For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer + is stored in a dedicated CPU register. This means that there is no + memory storage associated with storing the PEI Services Table pointer, + so no additional migration actions are required for Itanium, ARM and + LoongArch CPUs. =20 **/ VOID diff --git a/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTableP= ointer.c b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePoi= nter.c new file mode 100644 index 0000000000..2560b232f9 --- /dev/null +++ b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c @@ -0,0 +1,87 @@ +/** @file + PEI Services Table Pointer Library For Reigseter Mechanism. + + This library is used for PEIM which does executed from flash device dire= ctly but + executed in memory. + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.
+ Copyright (c) 2023 Loongson Technology Corporation Limited. All rights r= eserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +/** + Caches a pointer PEI Services Table. + + Caches the pointer to the PEI Services Table specified by PeiServicesTab= lePointer + in a platform specific manner. + + If PeiServicesTablePointer is NULL, then ASSERT(). + + @param PeiServicesTablePointer The address of PeiServices pointer. +**/ +VOID +EFIAPI +SetPeiServicesTablePointer ( + IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer + ) +{ + ASSERT (PeiServicesTablePointer !=3D NULL); + CsrWrite (LOONGARCH_CSR_KS0, (UINTN)PeiServicesTablePointer); +} + +/** + Retrieves the cached value of the PEI Services Table pointer. + + Returns the cached value of the PEI Services Table pointer in a CPU spec= ific manner + as specified in the CPU binding section of the Platform Initialization P= re-EFI + Initialization Core Interface Specification. + + If the cached PEI Services Table pointer is NULL, then ASSERT(). + + @return The pointer to PeiServices. + +**/ +CONST EFI_PEI_SERVICES ** +EFIAPI +GetPeiServicesTablePointer ( + VOID + ) +{ + CONST EFI_PEI_SERVICES **PeiServices; + + PeiServices =3D (CONST EFI_PEI_SERVICES **)(CsrRead (LOONGARCH_CSR_KS0)); + ASSERT (PeiServices !=3D NULL); + return PeiServices; +} + +/** + Perform CPU specific actions required to migrate the PEI Services Table + pointer from temporary RAM to permanent RAM. + + For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes + immediately preceding the Interrupt Descriptor Table (IDT) in memory. + For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer + is stored in a dedicated CPU register. This means that there is no + memory storage associated with storing the PEI Services Table pointer, + so no additional migration actions are required for Itanium, ARM and + LoongArch CPUs. + +**/ +VOID +EFIAPI +MigratePeiServicesTablePointer ( + VOID + ) +{ + return; +} diff --git a/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTableP= ointerLibKs0.inf b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServices= TablePointerLibKs0.inf new file mode 100644 index 0000000000..e8ecd4616d --- /dev/null +++ b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerL= ibKs0.inf @@ -0,0 +1,37 @@ +## @file +# Instance of PEI Services Table Pointer Library using register CSR KS0 fo= r the table pointer. +# +# PEI Services Table Pointer Library implementation that retrieves a point= er to the +# PEI Services Table from a CPU register. Applies to modules that execute = from +# read-only memory. +# +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.
+# Copyright (c) 2023 Loongson Technology Corporation Limited. All rights r= eserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D PeiServicesTablePointerLib + MODULE_UNI_FILE =3D PeiServicesTablePointerLibKs0.uni + FILE_GUID =3D 619950D1-7C5F-EA1B-D6DD-2FF7B0A4A2B7 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PeiServicesTablePointerLib|PEIM PEI_C= ORE SEC + +# +# VALID_ARCHITECTURES =3D LOONGARCH64 +# + +[Sources] + PeiServicesTablePointer.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib diff --git a/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTableP= ointerLibKs0.uni b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServices= TablePointerLibKs0.uni new file mode 100644 index 0000000000..2539448ce5 --- /dev/null +++ b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerL= ibKs0.uni @@ -0,0 +1,20 @@ +// /** @file +// Instance of PEI Services Table Pointer Library using register CSR KS0 f= or the table pointer. +// +// PEI Services Table Pointer Library implementation that retrieves a poin= ter to the +// PEI Services Table from a CPU register. Applies to modules that execute= from +// read-only memory. +// +// Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+// Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.
+// Copyright (c) 2023 Loongson Technology Corporation Limited. All rights = reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI S= ervices Table Pointer Library using CPU register for the table pointer" + +#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services = Table Pointer Library implementation that retrieves a pointer to the PEI Se= rvices Table from a CPU register. Applies to modules that execute from read= -only memory." + diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index 3abd1a1e23..109224c527 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -200,4 +200,7 @@ MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLib= .inf MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLib= Ram.inf =20 +[Components.LOONGARCH64] + MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibK= s0.inf + [BuildOptions] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112802): https://edk2.groups.io/g/devel/message/112802 Mute This Topic: https://groups.io/mt/103296576/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- ------=_NextPart_000_00A9_01DA3420.AE921CE0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Chao:

=C2=A0F= or the changes in MdePkg, I have two comments here.

<= p class=3DMsoNormal> 

1)      DebugSupport.h definition is from UEFI spec. Current defin= itions match the latest spec UEFI2.10. And, current definitions follow the = same style to other archs.

= 2)      CpuLib.h. The patch removes #if defined (MDE_CPU_IA32) || = defined (MDE_CPU_X64), then these APIs are exposed for all archs, but ARM a= nd RISCV don=E2=80=99t support them. So, I suggest to update it as below. = =C2=A0

 

#if defined (MDE_CPU_IA32) || defined (MDE_CPU= _X64)

=C3=A8<= /p>

#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X6= 4) || defined (MDE_CPU_LOONGARCH64)

 

Thanks

Liming

=E5=8F=91=E4=BB=B6=E4=BA=BA: Chao Li <lichao@loongson.cn>
=E5=8F=91=E9=80=81= =E6=97=B6=E9=97=B4: 2023=E5=B9=B412=E6=9C=8820=E6=97=A5 9:21
=E6=94=B6=E4=BB=B6=E4=BA=BA: gaoliming <gaoliming@byosoft.com.cn>= ; devel@edk2.groups.io; 'Michael D Kinney' <michael.d.kinney@intel.com&g= t;
=E6=8A=84=E9=80=81: 'Zhiguang Liu' <zhiguang.liu@intel.com>; 'Laszlo Ersek' <= ;lersek@redhat.com>
=E4=B8=BB=E9=A2=98:<= /span> Re: =E5=9B=9E=E5=A4=8D: [edk2-devel] [PATCH v4 09/37] MdePkg: Add a new library named PeiServi= cesTablePointerLibKs0

 

Hi Liming,

Yes, the code = branch is in my private repo, here is the link: https://github.com/kilaterlee/edk2/tree/p= ush1102

 

Thanks,
Chao

On = 2023/12/19 21:07, gaoliming wrote:

Chao:<= /span>

 = ;Is there a branch or pull request for this patch set? I would like to chec= k how this new library instance be used.

 

Thanks=

Liming

=E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io <de= vel@edk2.groups.io> =E4=BB=A3=E8=A1=A8 Chao Li
=E5=8F= =91=E9=80=81=E6=97=B6=E9=97=B4: 2023= =E5= =B9=B412=E6=9C=8819=E6= =97=A5 21:01
=E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io; Michael D Kinney <michael.d.kinney@intel.com>; Liming G= ao <gaoliming@byosoft.com.cn= >
=E6=8A=84=E9=80=81: Zhiguang Liu <= zhiguang.liu@intel.com>; Laszlo Ersek <lersek@redhat.com>
=E4=B8=BB=E9=A2=98: Re: [edk2-devel] [PATCH v4 09/3= 7] MdePkg: Add a new library named PeiServicesTablePointerLibKs0

 

Hi Mike and Liming,

Can you please review this patch? Thank you!

 = ;

Thanks,
Chao

On 2023/1= 2/12 21:11, Chao Li wrote:

Adding PeiSer=
vicesTablePointerLibKs0 for LoongArch64, which provides
setting and getting the PEI service table point=
er through the CSR KS0
regis=
ter.
 
The idea of this library is derived from
ArmPkg/Library/PeiServicesTable=
PointerLib/
 
BZ: https://bugzilla.tianocore.org/show_bug.cg=
i?id=3D4584
 <=
/o:p>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com><=
/pre>
Cc: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Chao Li <=
lichao@loongson.cn>
-=
--
 .../Library/PeiServicesT=
ablePointerLib.h      |  9 +-
 .../PeiServicesTablePointer.c  &=
nbsp;           &nbs=
p;  | 87 +++++++++++++++++++
 .../PeiServicesTablePointerLibKs0.inf     &=
nbsp;   | 37 ++++++++
 .../PeiServicesTablePointerLibKs0.uni     &nb=
sp;   | 20 +++++
 =
MdePkg/MdePkg.dsc         &nbs=
p;            &=
nbsp;      |  3 +
 5 files changed, 152 insertions(+), 4 deletions(-)
 create mode 100644 MdePkg/Libr=
ary/PeiServicesTablePointerLibKs0/PeiServicesTablePointer.c
 create mode 100644 MdePkg/Library/PeiServi=
cesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf
 create mode 100644 MdePkg/Library/PeiServicesT=
ablePointerLibKs0/PeiServicesTablePointerLibKs0.uni
=

 
diff --git a/MdePkg/Include/Library/PeiServicesTablePointerLib.h b/MdePk=
g/Include/Library/PeiServicesTablePointerLib.h
=
index 61635eff00..f85c38363c 100644
--- a/MdePkg/Include/Library/PeiServicesTablePoi=
nterLib.h
+++ b/MdePkg/Inclu=
de/Library/PeiServicesTablePointerLib.h
@@ -52,10 +52,11 @@ SetPeiServicesTablePointer (
   immediately preceding the Int=
errupt Descriptor Table (IDT) in memory.
   For X64 CPUs, the PEI Services Table pointer is s=
tored in the 8 bytes
 &=
nbsp; immediately preceding the Interrupt Descriptor Table (IDT) in memory.=

-  For Itanium and ARM=
 CPUs, a the PEI Services Table Pointer is stored in
-  a dedicated CPU register.  This means=
 that there is no memory storage
-  associated with storing the PEI Services Table pointer, so no =
additional
-  migration=
 actions are required for Itanium or ARM CPUs.
=
+  For Itanium, ARM and LoongArch CPUs, a the PEI S=
ervices Table Pointer
+ =
; is stored in a dedicated CPU register.  This means that there is no<=
o:p>
+  memory storage assoc=
iated with storing the PEI Services Table pointer,
<=
pre>+  so no additional migration actions are requi=
red for Itanium, ARM and
+&n=
bsp; LoongArch CPUs.
 <=
/o:p>
 **/
=

 VOID
diff --git a/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTabl=
ePointer.c b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTableP=
ointer.c
new file mode 10064=
4
index 0000000000..2560b232=
f9
--- /dev/null<=
/span>
+++ b/MdePkg/Library/PeiServicesTablePo=
interLibKs0/PeiServicesTablePointer.c
@@ -0,0 +1,87 @@
+=
/** @file
+  PEI Servic=
es Table Pointer Library For Reigseter Mechanism.
+
+&nb=
sp; This library is used for PEIM which does executed from flash device dir=
ectly but
+  executed i=
n memory.
+
+  Copyright (c) 2006 - 2010, Intel Cor=
poration. All rights reserved.<BR>
+  Copyright (c) 2011 Hewlett-Packard Corporation. All ri=
ghts reserved.<BR>
+&n=
bsp; Copyright (c) 2023 Loongson Technology Corporation Limited. All rights=
 reserved.<BR>
+<=
/o:p>
+  SPDX-License-Identifier: =
BSD-2-Clause-Patent
+
+**/
<=
span lang=3DEN-US>+
+#includ=
e <PiPei.h>
+#include =
<Library/DebugLib.h>
+=
#include <Library/PeiServicesTablePointerLib.h>
+#include <Register/LoongArch64/Csr.h>=

+
+/**
+ =
; Caches a pointer PEI Services Table.
+
+  Caches =
the pointer to the PEI Services Table specified by PeiServicesTablePointer<=
o:p>
+  in a platform specif=
ic manner.
+
+  If PeiServicesTablePointer is NULL,=
 then ASSERT().
+=

+  @param    PeiSe=
rvicesTablePointer   The address of PeiServices pointer.
+**/
+VOID
+EFIAP=
I
+SetPeiServicesTablePointe=
r (
+  IN CONST EFI_PEI=
_SERVICES  **PeiServicesTablePointer
+  )
+{
+  ASSERT (PeiServicesTa=
blePointer !=3D NULL);
+&nbs=
p; CsrWrite (LOONGARCH_CSR_KS0, (UINTN)PeiServicesTablePointer);=

+}
+
+/**
+  Retrieves the cached value of=
 the PEI Services Table pointer.
+
+  Returns the c=
ached value of the PEI Services Table pointer in a CPU specific manner=

+  as specified in the CPU =
binding section of the Platform Initialization Pre-EFI
+  Initialization Core Interface Specificat=
ion.
+
+  If the cached PEI Services Table pointer =
is NULL, then ASSERT().
+
+  @return  The poin=
ter to PeiServices.
+
+**/
<=
span lang=3DEN-US>+CONST EFI_PEI_SERVICES **
+EFIAPI
+Ge=
tPeiServicesTablePointer (
+=
  VOID
+  )
+{
+  CONST EFI_PEI_SERVICES  **PeiServices;
+
+  PeiServices =3D (CONST EFI_PEI_SERVICES **)(CsrRead (=
LOONGARCH_CSR_KS0));
+ =
 ASSERT (PeiServices !=3D NULL);
+  return PeiServices;
+}
+<=
/pre>
+/**
+  Perform CPU specific actions required to migrate the PEI Serv=
ices Table
+  pointer f=
rom temporary RAM to permanent RAM.
+
+  For IA32 =
CPUs, the PEI Services Table pointer is stored in the 4 bytes
+  immediately preceding the Interru=
pt Descriptor Table (IDT) in memory.
+  For X64 CPUs, the PEI Services Table pointer is stored in =
the 8 bytes
+  immediat=
ely preceding the Interrupt Descriptor Table (IDT) in memory.
+  For Itanium, ARM and LoongArch CP=
Us, a the PEI Services Table Pointer
+  is stored in a dedicated CPU register.  This means th=
at there is no
+  memor=
y storage associated with storing the PEI Services Table pointer,
+  so no additional migration ac=
tions are required for Itanium, ARM and
+  LoongArch CPUs.
+
+**/
+VOID
+EFIAPI
+Migrat=
ePeiServicesTablePointer (
+=
  VOID
+  )
+{
+  return;
+}
diff --git a/MdePkg/L=
ibrary/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.inf b/Md=
ePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.in=
f
new file mode 100644<=
/o:p>
index 0000000000..e8ecd4616d=

--- /dev/null<=
/pre>
+++ b/MdePkg/Library/PeiServicesTablePointerLi=
bKs0/PeiServicesTablePointerLibKs0.inf
@@ -0,0 +1,37 @@
=
+## @file
+# Instance of PEI=
 Services Table Pointer Library using register CSR KS0 for the table pointe=
r.
+#
+# PEI Services Table Pointer Library implementati=
on that retrieves a pointer to the
+# PEI Services Table from a CPU register. Applies to modules that=
 execute from
+# read-only m=
emory.
+#<=
/pre>
+# Copyright (c) 2007 - 2018, Intel Corporatio=
n. All rights reserved.<BR>
+# Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserve=
d.<BR>
+# Copyright (c=
) 2023 Loongson Technology Corporation Limited. All rights reserved.<BR&=
gt;
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Pa=
tent
+#
+#
+##
+
+[Defines]
+  INF_VERSION       &nbs=
p;            =3D 1.=
29
+  BASE_NAME &n=
bsp;            =
;        =3D PeiServicesTablePointerLib<=
o:p>
+  MODULE_UNI_FILE =
;            &n=
bsp;  =3D PeiServicesTablePointerLibKs0.uni
+  FILE_GUID      &=
nbsp;           &nbs=
p;   =3D 619950D1-7C5F-EA1B-D6DD-2FF7B0A4A2B7
+  MODULE_TYPE    &nbs=
p;            &=
nbsp;  =3D PEIM
+ =
 VERSION_STRING          =
       =3D 1.0
+  LIBRARY_CLASS      &=
nbsp;           =3D PeiSe=
rvicesTablePointerLib|PEIM PEI_CORE SEC
+
+#<=
/span>
+#  VALID_ARCHITECTURES  =
;         =3D LOONGARCH64
+#
+
+[Sources]
+  PeiServicesTablePointe=
r.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]=

+  DebugLib=

diff --git a/MdePkg/Library/PeiService=
sTablePointerLibKs0/PeiServicesTablePointerLibKs0.uni b/MdePkg/Library/PeiS=
ervicesTablePointerLibKs0/PeiServicesTablePointerLibKs0.uni
new file mode 100644
index 0000000000..2539448ce5
--- /dev/null
+++ b/MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServicesT=
ablePointerLibKs0.uni
@@ -0,=
0 +1,20 @@
+// /** @file
+// Instance of PEI Services Ta=
ble Pointer Library using register CSR KS0 for the table pointer.
+//
+// PEI Services Table Pointer Library implementation that re=
trieves a pointer to the
+//=
 PEI Services Table from a CPU register. Applies to modules that execute fr=
om
+// read-only memory.
+//
+// Copyright (c) 2007 - 2018, Intel Corporation. All r=
ights reserved.<BR>
+/=
/ Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.<B=
R>
+// Copyright (c) 2023=
 Loongson Technology Corporation Limited. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent<=
/o:p>
+//
<=
span lang=3DEN-US>+// **/
+<=
o:p>
+
+#string STR_MODULE_ABSTRACT    &n=
bsp;        #language en-US "Instan=
ce of PEI Services Table Pointer Library using CPU register for the table p=
ointer"
+
+#string STR_MODULE_DESCRIPTION &nbs=
p;        #language en-US "The PEI =
Services Table Pointer Library implementation that retrieves a pointer to t=
he PEI Services Table from a CPU register. Applies to modules that execute =
from read-only memory."
+
diff --git a/MdePkg/MdePk=
g.dsc b/MdePkg/MdePkg.dsc
in=
dex 3abd1a1e23..109224c527 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@=
 -200,4 +200,7 @@
 &nbs=
p; MdePkg/Library/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLib=
.inf
   MdePkg/Lib=
rary/BaseSerialPortLibRiscVSbiLib/BaseSerialPortLibRiscVSbiLibRam.inf<=
/o:p>
 
+[Components.LOONGARCH64]
+  MdePkg/Library/PeiServicesTablePointerLibKs0/PeiServi=
cesTablePointerLibKs0.inf
+<=
o:p>
 [BuildOptions]

<= /o:p>

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